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b54e5c689c
Doing this is not only wrong because it acquires the same spinlock twice, it also completely breaks the TLB flushing logic in MiMapPageInHyperSpace. If the PTE with Offset 1 is still valid when a wrap-around to 0 happens, the TLB flush on wrap-around will not clear the entry for this previous page. After another loop around all hyperspace pages, page 1 is re-used but its TLB entry has not been flushed, which may result into incorrect translation. |
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| .. | ||
| amd64 | ||
| arm | ||
| ARM3 | ||
| i386 | ||
| powerpc | ||
| balance.c | ||
| freelist.c | ||
| marea.c | ||
| mmfault.c | ||
| mminit.c | ||
| pagefile.c | ||
| region.c | ||
| rmap.c | ||
| section.c | ||