mirror of
https://github.com/reactos/reactos.git
synced 2024-07-08 13:45:06 +00:00
454 lines
17 KiB
C
454 lines
17 KiB
C
/*
|
||
* PROJECT: ReactOS VGA Miniport Driver
|
||
* LICENSE: Microsoft NT4 DDK Sample Code License
|
||
* FILE: win32ss/drivers/miniport/vga_new/vga.h
|
||
* PURPOSE: Main Header File
|
||
* PROGRAMMERS: Copyright (c) 1992 Microsoft Corporation
|
||
* ReactOS Portable Systems Group
|
||
*/
|
||
|
||
#ifndef _VGA_NEW_PCH_
|
||
#define _VGA_NEW_PCH_
|
||
|
||
#include <ntdef.h>
|
||
#include <dderror.h>
|
||
#include <miniport.h>
|
||
#include <video.h>
|
||
|
||
#include "cmdcnst.h"
|
||
|
||
//
|
||
// Base address of VGA memory range. Also used as base address of VGA
|
||
// memory when loading a font, which is done with the VGA mapped at A0000.
|
||
//
|
||
|
||
#define MEM_VGA 0xA0000
|
||
#define MEM_VGA_SIZE 0x20000
|
||
|
||
//
|
||
// For memory mapped IO
|
||
//
|
||
|
||
#define MEMORY_MAPPED_IO_OFFSET (0xB8000 - 0xA0000)
|
||
|
||
//
|
||
// Port definitions for filling the ACCESS_RANGES structure in the miniport
|
||
// information, defines the range of I/O ports the VGA spans.
|
||
// There is a break in the IO ports - a few ports are used for the parallel
|
||
// port. Those cannot be defined in the ACCESS_RANGE, but are still mapped
|
||
// so all VGA ports are in one address range.
|
||
//
|
||
|
||
#define VGA_BASE_IO_PORT 0x000003B0
|
||
#define VGA_START_BREAK_PORT 0x000003BB
|
||
#define VGA_END_BREAK_PORT 0x000003C0
|
||
#define VGA_MAX_IO_PORT 0x000003DF
|
||
|
||
//
|
||
// VGA register definitions
|
||
//
|
||
// eVb: 3.1 [VGA] - Use offsets from the VGA Port Address instead of absolute
|
||
#define CRTC_ADDRESS_PORT_MONO 0x0004 // CRT Controller Address and
|
||
#define CRTC_DATA_PORT_MONO 0x0005 // Data registers in mono mode
|
||
#define FEAT_CTRL_WRITE_PORT_MONO 0x000A // Feature Control write port
|
||
// in mono mode
|
||
#define INPUT_STATUS_1_MONO 0x000A // Input Status 1 register read
|
||
// port in mono mode
|
||
#define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO
|
||
// Register to read to reset
|
||
// Attribute Controller index/data
|
||
|
||
#define ATT_ADDRESS_PORT 0x0010 // Attribute Controller Address and
|
||
#define ATT_DATA_WRITE_PORT 0x0010 // Data registers share one port
|
||
// for writes, but only Address is
|
||
// readable at 0x3C0
|
||
#define ATT_DATA_READ_PORT 0x0011 // Attribute Controller Data reg is
|
||
// readable here
|
||
#define MISC_OUTPUT_REG_WRITE_PORT 0x0012 // Miscellaneous Output reg write
|
||
// port
|
||
#define INPUT_STATUS_0_PORT 0x0012 // Input Status 0 register read
|
||
// port
|
||
#define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013 // Bit 0 enables/disables the
|
||
// entire VGA subsystem
|
||
#define SEQ_ADDRESS_PORT 0x0014 // Sequence Controller Address and
|
||
#define SEQ_DATA_PORT 0x0015 // Data registers
|
||
#define DAC_PIXEL_MASK_PORT 0x0016 // DAC pixel mask reg
|
||
#define DAC_ADDRESS_READ_PORT 0x0017 // DAC register read index reg,
|
||
// write-only
|
||
#define DAC_STATE_PORT 0x0017 // DAC state (read/write),
|
||
// read-only
|
||
#define DAC_ADDRESS_WRITE_PORT 0x0018 // DAC register write index reg
|
||
#define DAC_DATA_REG_PORT 0x0019 // DAC data transfer reg
|
||
#define FEAT_CTRL_READ_PORT 0x001A // Feature Control read port
|
||
#define MISC_OUTPUT_REG_READ_PORT 0x001C // Miscellaneous Output reg read
|
||
// port
|
||
#define GRAPH_ADDRESS_PORT 0x001E // Graphics Controller Address
|
||
#define GRAPH_DATA_PORT 0x001F // and Data registers
|
||
|
||
#define CRTC_ADDRESS_PORT_COLOR 0x0024 // CRT Controller Address and
|
||
#define CRTC_DATA_PORT_COLOR 0x0025 // Data registers in color mode
|
||
#define FEAT_CTRL_WRITE_PORT_COLOR 0x002A // Feature Control write port
|
||
#define INPUT_STATUS_1_COLOR 0x002A // Input Status 1 register read
|
||
// port in color mode
|
||
// eVb: 3.2 [END]
|
||
#define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR
|
||
// Register to read to reset
|
||
// Attribute Controller index/data
|
||
// toggle in color mode
|
||
|
||
//
|
||
// Offsets in HardwareStateHeader->PortValue[] of save areas for non-indexed
|
||
// VGA registers.
|
||
//
|
||
|
||
#define CRTC_ADDRESS_MONO_OFFSET 0x04
|
||
#define FEAT_CTRL_WRITE_MONO_OFFSET 0x0A
|
||
#define ATT_ADDRESS_OFFSET 0x10
|
||
#define MISC_OUTPUT_REG_WRITE_OFFSET 0x12
|
||
#define VIDEO_SUBSYSTEM_ENABLE_OFFSET 0x13
|
||
#define SEQ_ADDRESS_OFFSET 0x14
|
||
#define DAC_PIXEL_MASK_OFFSET 0x16
|
||
#define DAC_STATE_OFFSET 0x17
|
||
#define DAC_ADDRESS_WRITE_OFFSET 0x18
|
||
#define GRAPH_ADDRESS_OFFSET 0x1E
|
||
#define CRTC_ADDRESS_COLOR_OFFSET 0x24
|
||
#define FEAT_CTRL_WRITE_COLOR_OFFSET 0x2A
|
||
|
||
// toggle in color mode
|
||
//
|
||
// VGA indexed register indexes.
|
||
//
|
||
|
||
// CL-GD542x specific registers:
|
||
//
|
||
#define IND_CL_EXTS_ENB 0x06 // index in Sequencer to enable exts
|
||
#define IND_NORD_SCRATCH_PAD 0x09 // index in Seq of Nordic scratch pad
|
||
#define IND_CL_SCRATCH_PAD 0x0A // index in Seq of 542x scratch pad
|
||
#define IND_ALP_SCRATCH_PAD 0x15 // index in Seq of Alpine scratch pad
|
||
#define IND_CL_REV_REG 0x25 // index in CRTC of ID Register
|
||
#define IND_CL_ID_REG 0x27 // index in CRTC of ID Register
|
||
//
|
||
#define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start
|
||
#define IND_CURSOR_END 0x0B // and End registers
|
||
#define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location
|
||
#define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers
|
||
#define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync
|
||
// End register, which has the bit
|
||
// that protects/unprotects CRTC
|
||
// index registers 0-7
|
||
#define IND_CR2C 0x2C // Nordic LCD Interface Register
|
||
#define IND_CR2D 0x2D // Nordic LCD Display Control
|
||
#define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC
|
||
#define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC
|
||
#define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr
|
||
#define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr
|
||
#define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr
|
||
#define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr
|
||
#define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq
|
||
#define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer
|
||
#define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq
|
||
#define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in
|
||
// CRTC
|
||
#define IND_CRTC_COMPAT 0x34 // index of CRTC Compatibility reg
|
||
// in CRTC
|
||
#define IND_PERF_TUNING 0x16 // index of performance tuning in Seq
|
||
#define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start
|
||
// synchronous reset
|
||
#define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end
|
||
// synchronous reset
|
||
|
||
//
|
||
// Value to write to Extensions Control register values extensions.
|
||
//
|
||
|
||
#define CL64xx_EXTENSION_ENABLE_INDEX 0x0A // GR0A to be exact!
|
||
#define CL64xx_EXTENSION_ENABLE_VALUE 0xEC
|
||
#define CL64xx_EXTENSION_DISABLE_VALUE 0xCE
|
||
#define CL64xx_TRISTATE_CONTROL_REG 0xA1
|
||
|
||
#define CL6340_ENABLE_READBACK_REGISTER 0xE0
|
||
#define CL6340_ENABLE_READBACK_ALLSEL_VALUE 0xF0
|
||
#define CL6340_ENABLE_READBACK_OFF_VALUE 0x00
|
||
#define CL6340_IDENTIFICATION_REGISTER 0xE9
|
||
//
|
||
// Values for Attribute Controller Index register to turn video off
|
||
// and on, by setting bit 5 to 0 (off) or 1 (on).
|
||
//
|
||
|
||
#define VIDEO_DISABLE 0
|
||
#define VIDEO_ENABLE 0x20
|
||
|
||
#define INDEX_ENABLE_AUTO_START 0x31
|
||
|
||
// Masks to keep only the significant bits of the Graphics Controller and
|
||
// Sequencer Address registers. Masking is necessary because some VGAs, such
|
||
// as S3-based ones, don't return unused bits set to 0, and some SVGAs use
|
||
// these bits if extensions are enabled.
|
||
//
|
||
|
||
#define GRAPH_ADDR_MASK 0x0F
|
||
#define SEQ_ADDR_MASK 0x07
|
||
|
||
//
|
||
// Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register.
|
||
//
|
||
|
||
#define CHAIN4_MASK 0x08
|
||
|
||
//
|
||
// Value written to the Read Map register when identifying the existence of
|
||
// a VGA in VgaInitialize. This value must be different from the final test
|
||
// value written to the Bit Mask in that routine.
|
||
//
|
||
|
||
#define READ_MAP_TEST_SETTING 0x03
|
||
|
||
//
|
||
// Default text mode setting for various registers, used to restore their
|
||
// states if VGA detection fails after they've been modified.
|
||
//
|
||
|
||
#define MEMORY_MODE_TEXT_DEFAULT 0x02
|
||
#define BIT_MASK_DEFAULT 0xFF
|
||
#define READ_MAP_DEFAULT 0x00
|
||
|
||
|
||
//
|
||
// Palette-related info.
|
||
//
|
||
|
||
//
|
||
// Highest valid DAC color register index.
|
||
//
|
||
|
||
#define VIDEO_MAX_COLOR_REGISTER 0xFF
|
||
|
||
//
|
||
// Highest valid palette register index
|
||
//
|
||
|
||
#define VIDEO_MAX_PALETTE_REGISTER 0x0F
|
||
|
||
//
|
||
// Driver Specific Attribute Flags
|
||
//
|
||
|
||
#define CAPS_NO_HOST_XFER 0x00000002 // Do not use host xfers to
|
||
// the blt engine.
|
||
#define CAPS_SW_POINTER 0x00000004 // Use software pointer.
|
||
#define CAPS_TRUE_COLOR 0x00000008 // Set upper color registers.
|
||
#define CAPS_MM_IO 0x00000010 // Use memory mapped IO.
|
||
#define CAPS_BLT_SUPPORT 0x00000020 // BLTs are supported
|
||
#define CAPS_IS_542x 0x00000040 // This is a 542x
|
||
#define CAPS_IS_5436 0x00000080 // This is a 5436
|
||
#define CAPS_CURSOR_VERT_EXP 0x00000100 // Flag set if 8x6 panel,
|
||
// but 6x4 resolution
|
||
|
||
//
|
||
// Structure used to describe each video mode in ModesVGA[].
|
||
//
|
||
|
||
typedef struct {
|
||
USHORT fbType; // color or monochrome, text or graphics, via
|
||
// VIDEO_MODE_COLOR and VIDEO_MODE_GRAPHICS
|
||
USHORT numPlanes; // # of video memory planes
|
||
USHORT bitsPerPlane; // # of bits of color in each plane
|
||
SHORT col; // # of text columns across screen with default font
|
||
SHORT row; // # of text rows down screen with default font
|
||
USHORT hres; // # of pixels across screen
|
||
USHORT vres; // # of scan lines down screen
|
||
// eVb: 3.2 [VGA] - Store frequency next to resolution data
|
||
ULONG Frequency; // Vertical Frequency
|
||
// eVb: 3.2 [END]
|
||
USHORT wbytes; // # of bytes from start of one scan line to start of next
|
||
ULONG sbytes; // total size of addressable display memory in bytes
|
||
// eVb: 3.3 [VBE] - Add VBE mode and bank flag
|
||
ULONG NoBankSwitch;
|
||
ULONG Mode;
|
||
// eVb: 3.3 [VBE]
|
||
PUSHORT CmdStream; // pointer to array of register-setting commands to
|
||
// set up mode
|
||
// eVb: 3.4 [VBE] - Add fields to track linear addresses/sizes and flags
|
||
ULONG PhysBase;
|
||
ULONG FrameBufferBase;
|
||
ULONG FrameBufferSize;
|
||
ULONG PhysSize;
|
||
ULONG LogicalWidth;
|
||
ULONG NonVgaMode;
|
||
ULONG Granularity;
|
||
// eVb: 3.4 [END]
|
||
} VIDEOMODE, *PVIDEOMODE;
|
||
|
||
//
|
||
// Mode into which to put the VGA before starting a VDM, so it's a plain
|
||
// vanilla VGA. (This is the mode's index in ModesVGA[], currently standard
|
||
// 80x25 text mode.)
|
||
//
|
||
|
||
#define DEFAULT_MODE 0
|
||
|
||
|
||
//
|
||
// Info used by the Validator functions and save/restore code.
|
||
// Structure used to trap register accesses that must be done atomically.
|
||
//
|
||
|
||
#define VGA_MAX_VALIDATOR_DATA 100
|
||
|
||
#define VGA_VALIDATOR_UCHAR_ACCESS 1
|
||
#define VGA_VALIDATOR_USHORT_ACCESS 2
|
||
#define VGA_VALIDATOR_ULONG_ACCESS 3
|
||
|
||
typedef struct _VGA_VALIDATOR_DATA {
|
||
ULONG Port;
|
||
UCHAR AccessType;
|
||
ULONG Data;
|
||
} VGA_VALIDATOR_DATA, *PVGA_VALIDATOR_DATA;
|
||
|
||
//
|
||
// Number of bytes to save in each plane.
|
||
//
|
||
|
||
#define VGA_PLANE_SIZE 0x10000
|
||
|
||
//
|
||
// Number of each type of indexed register in a standard VGA, used by
|
||
// validator and state save/restore functions.
|
||
//
|
||
// Note: VDMs currently only support basic VGAs only.
|
||
//
|
||
|
||
#define VGA_NUM_SEQUENCER_PORTS 5
|
||
#define VGA_NUM_CRTC_PORTS 25
|
||
#define VGA_NUM_GRAPH_CONT_PORTS 9
|
||
#define VGA_NUM_ATTRIB_CONT_PORTS 21
|
||
#define VGA_NUM_DAC_ENTRIES 256
|
||
|
||
#define EXT_NUM_GRAPH_CONT_PORTS 0
|
||
#define EXT_NUM_SEQUENCER_PORTS 0
|
||
#define EXT_NUM_CRTC_PORTS 0
|
||
#define EXT_NUM_ATTRIB_CONT_PORTS 0
|
||
#define EXT_NUM_DAC_ENTRIES 0
|
||
|
||
//
|
||
// These constants determine the offsets within the
|
||
// VIDEO_HARDWARE_STATE_HEADER structure that are used to save and
|
||
// restore the VGA's state.
|
||
//
|
||
|
||
#define VGA_HARDWARE_STATE_SIZE sizeof(VIDEO_HARDWARE_STATE_HEADER)
|
||
|
||
#define VGA_BASIC_SEQUENCER_OFFSET (VGA_HARDWARE_STATE_SIZE + 0)
|
||
#define VGA_BASIC_CRTC_OFFSET (VGA_BASIC_SEQUENCER_OFFSET + \
|
||
VGA_NUM_SEQUENCER_PORTS)
|
||
#define VGA_BASIC_GRAPH_CONT_OFFSET (VGA_BASIC_CRTC_OFFSET + \
|
||
VGA_NUM_CRTC_PORTS)
|
||
#define VGA_BASIC_ATTRIB_CONT_OFFSET (VGA_BASIC_GRAPH_CONT_OFFSET + \
|
||
VGA_NUM_GRAPH_CONT_PORTS)
|
||
#define VGA_BASIC_DAC_OFFSET (VGA_BASIC_ATTRIB_CONT_OFFSET + \
|
||
VGA_NUM_ATTRIB_CONT_PORTS)
|
||
#define VGA_BASIC_LATCHES_OFFSET (VGA_BASIC_DAC_OFFSET + \
|
||
(3 * VGA_NUM_DAC_ENTRIES))
|
||
|
||
#define VGA_EXT_SEQUENCER_OFFSET (VGA_BASIC_LATCHES_OFFSET + 4)
|
||
#define VGA_EXT_CRTC_OFFSET (VGA_EXT_SEQUENCER_OFFSET + \
|
||
EXT_NUM_SEQUENCER_PORTS)
|
||
#define VGA_EXT_GRAPH_CONT_OFFSET (VGA_EXT_CRTC_OFFSET + \
|
||
EXT_NUM_CRTC_PORTS)
|
||
#define VGA_EXT_ATTRIB_CONT_OFFSET (VGA_EXT_GRAPH_CONT_OFFSET +\
|
||
EXT_NUM_GRAPH_CONT_PORTS)
|
||
#define VGA_EXT_DAC_OFFSET (VGA_EXT_ATTRIB_CONT_OFFSET + \
|
||
EXT_NUM_ATTRIB_CONT_PORTS)
|
||
|
||
#define VGA_VALIDATOR_OFFSET (VGA_EXT_DAC_OFFSET + 4 * EXT_NUM_DAC_ENTRIES)
|
||
|
||
#define VGA_VALIDATOR_AREA_SIZE sizeof (ULONG) + (VGA_MAX_VALIDATOR_DATA * \
|
||
sizeof (VGA_VALIDATOR_DATA)) + \
|
||
sizeof (ULONG) + \
|
||
sizeof (ULONG) + \
|
||
sizeof (PVIDEO_ACCESS_RANGE)
|
||
|
||
#define VGA_MISC_DATA_AREA_OFFSET VGA_VALIDATOR_OFFSET + VGA_VALIDATOR_AREA_SIZE
|
||
|
||
#define VGA_MISC_DATA_AREA_SIZE 0
|
||
|
||
#define VGA_PLANE_0_OFFSET VGA_MISC_DATA_AREA_OFFSET + VGA_MISC_DATA_AREA_SIZE
|
||
|
||
#define VGA_PLANE_1_OFFSET VGA_PLANE_0_OFFSET + VGA_PLANE_SIZE
|
||
#define VGA_PLANE_2_OFFSET VGA_PLANE_1_OFFSET + VGA_PLANE_SIZE
|
||
#define VGA_PLANE_3_OFFSET VGA_PLANE_2_OFFSET + VGA_PLANE_SIZE
|
||
|
||
//
|
||
// Space needed to store all state data.
|
||
//
|
||
|
||
#define VGA_TOTAL_STATE_SIZE VGA_PLANE_3_OFFSET + VGA_PLANE_SIZE
|
||
|
||
|
||
//
|
||
// Device extension for the driver object. This data is only used
|
||
// locally, so this structure can be added to as needed.
|
||
//
|
||
|
||
typedef struct _HW_DEVICE_EXTENSION {
|
||
|
||
PHYSICAL_ADDRESS PhysicalVideoMemoryBase; // physical memory address and
|
||
PHYSICAL_ADDRESS PhysicalFrameOffset; // physical memory address and
|
||
ULONG PhysicalVideoMemoryLength; // length of display memory
|
||
ULONG PhysicalFrameLength; // length of display memory for
|
||
// the current mode.
|
||
|
||
PUCHAR IOAddress; // base I/O address of VGA ports
|
||
PUCHAR VideoMemoryAddress; // base virtual memory address of VGA memory
|
||
ULONG ModeIndex; // index of current mode in ModesVGA[]
|
||
PVIDEOMODE CurrentMode; // pointer to VIDEOMODE structure for
|
||
// current mode
|
||
|
||
VIDEO_CURSOR_POSITION CursorPosition; // current cursor position
|
||
|
||
UCHAR CursorEnable; // whether cursor is enabled or not
|
||
UCHAR CursorTopScanLine; // Cursor Start register setting (top scan)
|
||
UCHAR CursorBottomScanLine; // Cursor End register setting (bottom scan)
|
||
// eVb: 3.5 [VBE] - Add fields for VBE support and XP+ INT10 interface
|
||
VIDEO_PORT_INT10_INTERFACE Int10Interface;
|
||
BOOLEAN VesaBiosOk;
|
||
// eVb: 3.5 [END]
|
||
} HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
|
||
|
||
|
||
//
|
||
// Function prototypes.
|
||
//
|
||
|
||
//
|
||
// Entry points for the VGA validator. Used in VgaEmulatorAccessEntries[].
|
||
//
|
||
|
||
|
||
//
|
||
// Vga init scripts for font loading
|
||
//
|
||
|
||
extern USHORT EnableA000Data[];
|
||
extern USHORT DisableA000Color[];
|
||
|
||
//
|
||
// Mode Information
|
||
//
|
||
|
||
extern ULONG NumVideoModes;
|
||
extern VIDEOMODE ModesVGA[];
|
||
extern PVIDEOMODE VgaModeList;
|
||
|
||
// eVb: 3.5 [VGA] - Add ATI/Mach64 Access Range
|
||
#define NUM_VGA_ACCESS_RANGES 5
|
||
// eVb: 3.5 [END]
|
||
extern VIDEO_ACCESS_RANGE VgaAccessRange[];
|
||
|
||
/* VESA Bios Magic number */
|
||
#define VESA_MAGIC ('V' + ('E' << 8) + ('S' << 16) + ('A' << 24))
|
||
|
||
#include "vbe.h"
|
||
|
||
#endif /* _VGA_NEW_PCH_ */
|