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461 lines
14 KiB
C
461 lines
14 KiB
C
/*
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* PROJECT: ReactOS Storage Stack
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* LICENSE: DDK - see license.txt in the root dir
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* FILE: drivers/storage/atapi/atapi.h
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* PURPOSE: ATAPI IDE miniport driver
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* PROGRAMMERS: Based on a source code sample from Microsoft NT4 DDK
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*/
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#include <srb.h>
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#include <scsi.h>
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//
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// IDE register definition
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//
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typedef struct _IDE_REGISTERS_1 {
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USHORT Data;
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UCHAR BlockCount;
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UCHAR BlockNumber;
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UCHAR CylinderLow;
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UCHAR CylinderHigh;
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UCHAR DriveSelect;
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UCHAR Command;
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} IDE_REGISTERS_1, *PIDE_REGISTERS_1;
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typedef struct _IDE_REGISTERS_2 {
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UCHAR AlternateStatus;
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UCHAR DriveAddress;
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} IDE_REGISTERS_2, *PIDE_REGISTERS_2;
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typedef struct _IDE_REGISTERS_3 {
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ULONG Data;
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UCHAR Others[4];
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} IDE_REGISTERS_3, *PIDE_REGISTERS_3;
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//
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// Device Extension Device Flags
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//
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#define DFLAGS_DEVICE_PRESENT 0x0001 // Indicates that some device is present.
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#define DFLAGS_ATAPI_DEVICE 0x0002 // Indicates whether Atapi commands can be used.
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#define DFLAGS_TAPE_DEVICE 0x0004 // Indicates whether this is a tape device.
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#define DFLAGS_INT_DRQ 0x0008 // Indicates whether device interrupts as DRQ is set after
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// receiving Atapi Packet Command
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#define DFLAGS_REMOVABLE_DRIVE 0x0010 // Indicates that the drive has the 'removable' bit set in
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// identify data (offset 128)
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#define DFLAGS_MEDIA_STATUS_ENABLED 0x0020 // Media status notification enabled
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#define DFLAGS_ATAPI_CHANGER 0x0040 // Indicates atapi 2.5 changer present.
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#define DFLAGS_SANYO_ATAPI_CHANGER 0x0080 // Indicates multi-platter device, not conforming to the 2.5 spec.
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#define DFLAGS_CHANGER_INITED 0x0100 // Indicates that the init path for changers has already been done.
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//
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// Used to disable 'advanced' features.
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//
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#define MAX_ERRORS 4
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//
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// ATAPI command definitions
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//
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#define ATAPI_MODE_SENSE 0x5A
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#define ATAPI_MODE_SELECT 0x55
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#define ATAPI_FORMAT_UNIT 0x24
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//
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// ATAPI Command Descriptor Block
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//
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typedef struct _MODE_SENSE_10 {
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UCHAR OperationCode;
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UCHAR Reserved1;
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UCHAR PageCode : 6;
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UCHAR Pc : 2;
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UCHAR Reserved2[4];
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UCHAR ParameterListLengthMsb;
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UCHAR ParameterListLengthLsb;
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UCHAR Reserved3[3];
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} MODE_SENSE_10, *PMODE_SENSE_10;
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typedef struct _MODE_SELECT_10 {
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UCHAR OperationCode;
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UCHAR Reserved1 : 4;
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UCHAR PFBit : 1;
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UCHAR Reserved2 : 3;
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UCHAR Reserved3[5];
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UCHAR ParameterListLengthMsb;
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UCHAR ParameterListLengthLsb;
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UCHAR Reserved4[3];
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} MODE_SELECT_10, *PMODE_SELECT_10;
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typedef struct _MODE_PARAMETER_HEADER_10 {
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UCHAR ModeDataLengthMsb;
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UCHAR ModeDataLengthLsb;
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UCHAR MediumType;
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UCHAR Reserved[5];
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}MODE_PARAMETER_HEADER_10, *PMODE_PARAMETER_HEADER_10;
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//
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// IDE command definitions
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//
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#define IDE_COMMAND_ATAPI_RESET 0x08
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#define IDE_COMMAND_RECALIBRATE 0x10
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#define IDE_COMMAND_READ 0x20
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#define IDE_COMMAND_WRITE 0x30
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#define IDE_COMMAND_VERIFY 0x40
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#define IDE_COMMAND_SEEK 0x70
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#define IDE_COMMAND_SET_DRIVE_PARAMETERS 0x91
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#define IDE_COMMAND_ATAPI_PACKET 0xA0
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#define IDE_COMMAND_ATAPI_IDENTIFY 0xA1
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#define IDE_COMMAND_READ_MULTIPLE 0xC4
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#define IDE_COMMAND_WRITE_MULTIPLE 0xC5
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#define IDE_COMMAND_SET_MULTIPLE 0xC6
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#define IDE_COMMAND_READ_DMA 0xC8
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#define IDE_COMMAND_WRITE_DMA 0xCA
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#define IDE_COMMAND_GET_MEDIA_STATUS 0xDA
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#define IDE_COMMAND_ENABLE_MEDIA_STATUS 0xEF
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#define IDE_COMMAND_IDENTIFY 0xEC
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#define IDE_COMMAND_MEDIA_EJECT 0xED
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//
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// IDE status definitions
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//
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#define IDE_STATUS_ERROR 0x01
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#define IDE_STATUS_INDEX 0x02
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#define IDE_STATUS_CORRECTED_ERROR 0x04
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#define IDE_STATUS_DRQ 0x08
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#define IDE_STATUS_DSC 0x10
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#define IDE_STATUS_DRDY 0x40
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#define IDE_STATUS_IDLE 0x50
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#define IDE_STATUS_BUSY 0x80
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//
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// IDE drive select/head definitions
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//
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#define IDE_DRIVE_SELECT_1 0xA0
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#define IDE_DRIVE_SELECT_2 0x10
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//
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// IDE drive control definitions
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//
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#define IDE_DC_DISABLE_INTERRUPTS 0x02
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#define IDE_DC_RESET_CONTROLLER 0x04
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#define IDE_DC_REENABLE_CONTROLLER 0x00
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//
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// IDE error definitions
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//
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#define IDE_ERROR_BAD_BLOCK 0x80
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#define IDE_ERROR_DATA_ERROR 0x40
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#define IDE_ERROR_MEDIA_CHANGE 0x20
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#define IDE_ERROR_ID_NOT_FOUND 0x10
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#define IDE_ERROR_MEDIA_CHANGE_REQ 0x08
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#define IDE_ERROR_COMMAND_ABORTED 0x04
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#define IDE_ERROR_END_OF_MEDIA 0x02
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#define IDE_ERROR_ILLEGAL_LENGTH 0x01
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//
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// ATAPI register definition
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//
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typedef struct _ATAPI_REGISTERS_1 {
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USHORT Data;
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UCHAR InterruptReason;
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UCHAR Unused1;
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UCHAR ByteCountLow;
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UCHAR ByteCountHigh;
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UCHAR DriveSelect;
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UCHAR Command;
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} ATAPI_REGISTERS_1, *PATAPI_REGISTERS_1;
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typedef struct _ATAPI_REGISTERS_2 {
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UCHAR AlternateStatus;
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UCHAR DriveAddress;
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} ATAPI_REGISTERS_2, *PATAPI_REGISTERS_2;
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//
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// ATAPI interrupt reasons
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//
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#define ATAPI_IR_COD 0x01
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#define ATAPI_IR_IO 0x02
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//
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// IDENTIFY data
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//
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typedef struct _IDENTIFY_DATA {
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USHORT GeneralConfiguration; // 00 00
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USHORT NumberOfCylinders; // 02 1
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USHORT Reserved1; // 04 2
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USHORT NumberOfHeads; // 06 3
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USHORT UnformattedBytesPerTrack; // 08 4
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USHORT UnformattedBytesPerSector; // 0A 5
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USHORT SectorsPerTrack; // 0C 6
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USHORT VendorUnique1[3]; // 0E 7-9
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USHORT SerialNumber[10]; // 14 10-19
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USHORT BufferType; // 28 20
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USHORT BufferSectorSize; // 2A 21
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USHORT NumberOfEccBytes; // 2C 22
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USHORT FirmwareRevision[4]; // 2E 23-26
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USHORT ModelNumber[20]; // 36 27-46
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UCHAR MaximumBlockTransfer; // 5E 47
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UCHAR VendorUnique2; // 5F
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USHORT DoubleWordIo; // 60 48
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USHORT Capabilities; // 62 49
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USHORT Reserved2; // 64 50
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UCHAR VendorUnique3; // 66 51
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UCHAR PioCycleTimingMode; // 67
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UCHAR VendorUnique4; // 68 52
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UCHAR DmaCycleTimingMode; // 69
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USHORT TranslationFieldsValid:1; // 6A 53
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USHORT Reserved3:15;
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USHORT NumberOfCurrentCylinders; // 6C 54
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USHORT NumberOfCurrentHeads; // 6E 55
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USHORT CurrentSectorsPerTrack; // 70 56
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ULONG CurrentSectorCapacity; // 72 57-58
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USHORT CurrentMultiSectorSetting; // 59
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ULONG UserAddressableSectors; // 60-61
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USHORT SingleWordDMASupport : 8; // 62
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USHORT SingleWordDMAActive : 8;
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USHORT MultiWordDMASupport : 8; // 63
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USHORT MultiWordDMAActive : 8;
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USHORT AdvancedPIOModes : 8; // 64
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USHORT Reserved4 : 8;
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USHORT MinimumMWXferCycleTime; // 65
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USHORT RecommendedMWXferCycleTime; // 66
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USHORT MinimumPIOCycleTime; // 67
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USHORT MinimumPIOCycleTimeIORDY; // 68
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USHORT Reserved5[2]; // 69-70
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USHORT ReleaseTimeOverlapped; // 71
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USHORT ReleaseTimeServiceCommand; // 72
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USHORT MajorRevision; // 73
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USHORT MinorRevision; // 74
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USHORT Reserved6[50]; // 75-126
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USHORT SpecialFunctionsEnabled; // 127
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USHORT Reserved7[128]; // 128-255
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} IDENTIFY_DATA, *PIDENTIFY_DATA;
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//
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// Identify data without the Reserved4.
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//
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typedef struct _IDENTIFY_DATA2 {
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USHORT GeneralConfiguration; // 00
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USHORT NumberOfCylinders; // 02
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USHORT Reserved1; // 04
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USHORT NumberOfHeads; // 06
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USHORT UnformattedBytesPerTrack; // 08
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USHORT UnformattedBytesPerSector; // 0A
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USHORT SectorsPerTrack; // 0C
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USHORT VendorUnique1[3]; // 0E
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USHORT SerialNumber[10]; // 14
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USHORT BufferType; // 28
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USHORT BufferSectorSize; // 2A
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USHORT NumberOfEccBytes; // 2C
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USHORT FirmwareRevision[4]; // 2E
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USHORT ModelNumber[20]; // 36
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UCHAR MaximumBlockTransfer; // 5E
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UCHAR VendorUnique2; // 5F
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USHORT DoubleWordIo; // 60
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USHORT Capabilities; // 62
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USHORT Reserved2; // 64
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UCHAR VendorUnique3; // 66
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UCHAR PioCycleTimingMode; // 67
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UCHAR VendorUnique4; // 68
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UCHAR DmaCycleTimingMode; // 69
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USHORT TranslationFieldsValid:1; // 6A
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USHORT Reserved3:15;
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USHORT NumberOfCurrentCylinders; // 6C
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USHORT NumberOfCurrentHeads; // 6E
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USHORT CurrentSectorsPerTrack; // 70
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ULONG CurrentSectorCapacity; // 72
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} IDENTIFY_DATA2, *PIDENTIFY_DATA2;
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#define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA)
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//
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// IDENTIFY capability bit definitions.
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//
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#define IDENTIFY_CAPABILITIES_DMA_SUPPORTED 0x0100
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#define IDENTIFY_CAPABILITIES_LBA_SUPPORTED 0x0200
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//
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// IDENTIFY DMA timing cycle modes.
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//
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#define IDENTIFY_DMA_CYCLES_MODE_0 0x00
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#define IDENTIFY_DMA_CYCLES_MODE_1 0x01
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#define IDENTIFY_DMA_CYCLES_MODE_2 0x02
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typedef struct _BROKEN_CONTROLLER_INFORMATION {
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PCHAR VendorId;
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ULONG VendorIdLength;
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PCHAR DeviceId;
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ULONG DeviceIdLength;
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}BROKEN_CONTROLLER_INFORMATION, *PBROKEN_CONTROLLER_INFORMATION;
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BROKEN_CONTROLLER_INFORMATION const BrokenAdapters[] = {
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{ "1095", 4, "0640", 4},
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{ "1039", 4, "0601", 4}
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};
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#define BROKEN_ADAPTERS (sizeof(BrokenAdapters) / sizeof(BROKEN_CONTROLLER_INFORMATION))
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typedef struct _NATIVE_MODE_CONTROLLER_INFORMATION {
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PCHAR VendorId;
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ULONG VendorIdLength;
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PCHAR DeviceId;
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ULONG DeviceIdLength;
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}NATIVE_MODE_CONTROLLER_INFORMATION, *PNATIVE_MODE_CONTROLLER_INFORMATION;
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NATIVE_MODE_CONTROLLER_INFORMATION const NativeModeAdapters[] = {
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{ "10ad", 4, "0105", 4}
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};
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#define NUM_NATIVE_MODE_ADAPTERS (sizeof(NativeModeAdapters) / sizeof(NATIVE_MODE_CONTROLLER_INFORMATION))
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//
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// Beautification macros
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//
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#define GetStatus(BaseIoAddress, Status) \
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Status = ScsiPortReadPortUchar(&BaseIoAddress->AlternateStatus);
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#define GetBaseStatus(BaseIoAddress, Status) \
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Status = ScsiPortReadPortUchar(&BaseIoAddress->Command);
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#define WriteCommand(BaseIoAddress, Command) \
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ScsiPortWritePortUchar(&BaseIoAddress->Command, Command);
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#define ReadBuffer(BaseIoAddress, Buffer, Count) \
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ScsiPortReadPortBufferUshort(&BaseIoAddress->Data, \
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Buffer, \
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Count);
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#define WriteBuffer(BaseIoAddress, Buffer, Count) \
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ScsiPortWritePortBufferUshort(&BaseIoAddress->Data, \
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Buffer, \
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Count);
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#define ReadBuffer2(BaseIoAddress, Buffer, Count) \
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ScsiPortReadPortBufferUlong(&BaseIoAddress->Data, \
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Buffer, \
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Count);
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#define WriteBuffer2(BaseIoAddress, Buffer, Count) \
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ScsiPortWritePortBufferUlong(&BaseIoAddress->Data, \
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Buffer, \
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Count);
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#define WaitOnBusy(BaseIoAddress, Status) \
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{ \
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ULONG i; \
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for (i=0; i<20000; i++) { \
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GetStatus(BaseIoAddress, Status); \
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if (Status & IDE_STATUS_BUSY) { \
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ScsiPortStallExecution(150); \
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continue; \
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} else { \
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break; \
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} \
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} \
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}
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#define WaitOnBaseBusy(BaseIoAddress, Status) \
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{ \
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ULONG i; \
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for (i=0; i<20000; i++) { \
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GetBaseStatus(BaseIoAddress, Status); \
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if (Status & IDE_STATUS_BUSY) { \
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ScsiPortStallExecution(150); \
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continue; \
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} else { \
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break; \
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} \
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} \
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}
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#define WaitForDrq(BaseIoAddress, Status) \
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{ \
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ULONG i; \
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for (i=0; i<1000; i++) { \
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GetStatus(BaseIoAddress, Status); \
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if (Status & IDE_STATUS_BUSY) { \
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ScsiPortStallExecution(100); \
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} else if (Status & IDE_STATUS_DRQ) { \
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break; \
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} else { \
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ScsiPortStallExecution(200); \
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} \
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} \
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}
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#define WaitShortForDrq(BaseIoAddress, Status) \
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{ \
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ULONG i; \
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for (i=0; i<2; i++) { \
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GetStatus(BaseIoAddress, Status); \
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if (Status & IDE_STATUS_BUSY) { \
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ScsiPortStallExecution(100); \
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} else if (Status & IDE_STATUS_DRQ) { \
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break; \
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} else { \
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ScsiPortStallExecution(100); \
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} \
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} \
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}
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#define AtapiSoftReset(BaseIoAddress,DeviceNumber) \
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{\
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UCHAR statusByte; \
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ULONG i = 1000*1000;\
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ScsiPortWritePortUchar(&BaseIoAddress->DriveSelect,(UCHAR)(((DeviceNumber & 0x1) << 4) | 0xA0)); \
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ScsiPortStallExecution(500);\
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ScsiPortWritePortUchar(&BaseIoAddress->Command, IDE_COMMAND_ATAPI_RESET); \
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while ((ScsiPortReadPortUchar(&BaseIoAddress->Command) & IDE_STATUS_BUSY) && i--)\
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ScsiPortStallExecution(30);\
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ScsiPortWritePortUchar(&BaseIoAddress->DriveSelect,(UCHAR)((DeviceNumber << 4) | 0xA0)); \
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WaitOnBusy( ((PIDE_REGISTERS_2)((PUCHAR)BaseIoAddress + 0x206)), statusByte); \
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ScsiPortStallExecution(500);\
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}
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#define IdeHardReset(BaseIoAddress,result) \
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{\
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UCHAR statusByte;\
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ULONG i;\
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ScsiPortWritePortUchar(&BaseIoAddress->AlternateStatus,IDE_DC_RESET_CONTROLLER );\
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ScsiPortStallExecution(50 * 1000);\
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ScsiPortWritePortUchar(&BaseIoAddress->AlternateStatus,IDE_DC_REENABLE_CONTROLLER);\
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for (i = 0; i < 1000 * 1000; i++) {\
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statusByte = ScsiPortReadPortUchar(&BaseIoAddress->AlternateStatus);\
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if (statusByte != IDE_STATUS_IDLE && statusByte != 0x0) {\
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ScsiPortStallExecution(5);\
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} else {\
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break;\
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}\
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}\
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if (i == 1000*1000) {\
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result = FALSE;\
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}\
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result = TRUE;\
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}
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#define IS_RDP(OperationCode)\
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((OperationCode == SCSIOP_ERASE)||\
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(OperationCode == SCSIOP_LOAD_UNLOAD)||\
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(OperationCode == SCSIOP_LOCATE)||\
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(OperationCode == SCSIOP_REWIND) ||\
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(OperationCode == SCSIOP_SPACE)||\
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(OperationCode == SCSIOP_SEEK)||\
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(OperationCode == SCSIOP_WRITE_FILEMARKS))
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