reactos/rosapps/devutils/cputointel/OpCodePPC.txt
Magnus Olsen 36a8eccf27 Implement disambler for stwu, left todo add it to the Converter
svn path=/trunk/; revision=25514
2007-01-18 19:33:48 +00:00

74 lines
3.1 KiB
Plaintext

PowerPC 32bits
reg = R0-R31
#imm = a value you set
Bit expain
0 = mean bit is zero
1 = mean bit is set
2 = mean this bit can be 0 or 1
opcode Name Desciptions
0010 0000 0000 0000 1000 0000 0100 1110 blr return from a functions
0222 2222 2222 2222 2222 2222 0011 1000 Li reg,#imm move a value to a register
Here how the primary opcode work
xxxx xxxx xxxx xxxx DDDS SSSS 3333 33DD
3 = it is the primary opcode
D = Destions register
S = Source reigters
opcode
-------------------------
|bit order: 5432 10 67 |
------- ------- ----------- ----
34: | 0c 00 | | e1 93 | stw r31,12(r1) 0000 1100 0000 0000 1110 0001 | 1001 00 | 00
38: | 14 00 | | 01 90 | stw r0,20(r1) 0001 0100 0000 0000 0000 0001 | 1001 00 | 11
------- ------- ---------
| |
| |--> Get source register R0-R31 (0xE1 & 0x1F) = 1
| |
| |--> Get Dest register R0-R31 ((0xE1 & 0xE0)>>5) | ((0x90 & 0x3)<<3) = 31 or 0
| | (The adding the two last bit on the end is maybe wrong need examine it)
| |
| --> Get the opcpde (0x90 & 0xFC)
\ /
The address offset 12 or 20
opcode
---------------------------------------------------------
|bit order: pos 1111 1111 1111 1111 0000 0000 0000 0000 |
| 5432 10 |
|---------------------------------------------------------|
| bits 0000 1100 0000 0000 1110 0001 1001 0000 |
---------------------------------------------------------
| math (opcode>>2) & 0x3F |
---------------------------------------------------------
Dest Register
---------------------------------------------------------
|bit order: pos 1111 1111 1111 1111 0000 0000 0000 0000 |
| 210 43 |
|---------------------------------------------------------|
| bits 0000 1100 0000 0000 1110 0001 1001 0000 |
---------------------------------------------------------
| math (((opcode & 0x3) << 3) | ((opcode & 0xE000) >> 13))|
---------------------------------------------------------
source Register
---------------------------------------------------------
|bit order: pos 1111 1111 1111 1111 0000 0000 0000 0000 |
| x xxxx |
|---------------------------------------------------------|
| bits 0000 1100 0000 0000 1110 0001 1001 0000 |
---------------------------------------------------------
| math |
---------------------------------------------------------