mirror of
https://github.com/reactos/reactos.git
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417 lines
12 KiB
C
417 lines
12 KiB
C
/*
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* PROJECT: ReactOS USB EHCI Miniport Driver
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* LICENSE: GPL-2.0+ (https://spdx.org/licenses/GPL-2.0+)
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* PURPOSE: USBEHCI hardware declarations
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* COPYRIGHT: Copyright 2017-2018 Vadim Galyant <vgal@rambler.ru>
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*/
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#define EHCI_FRAME_LIST_MAX_ENTRIES 1024 // Number of frames in Frame List
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/* EHCI hardware registers */
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#define EHCI_USBCMD 0
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#define EHCI_USBSTS 1
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#define EHCI_USBINTR 2
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#define EHCI_FRINDEX 3
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#define EHCI_CTRLDSSEGMENT 4
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#define EHCI_PERIODICLISTBASE 5
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#define EHCI_ASYNCLISTBASE 6
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#define EHCI_CONFIGFLAG 16
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#define EHCI_PORTSC 17
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#define EHCI_FLADJ_PCI_CONFIG_OFFSET 0x61
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typedef union _EHCI_LEGACY_EXTENDED_CAPABILITY {
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struct {
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ULONG CapabilityID : 8;
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ULONG NextCapabilityPointer : 8;
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ULONG BiosOwnedSemaphore : 1;
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ULONG Reserved1 : 7;
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ULONG OsOwnedSemaphore : 1;
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ULONG Reserved2 : 7;
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};
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ULONG AsULONG;
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} EHCI_LEGACY_EXTENDED_CAPABILITY;
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C_ASSERT(sizeof(EHCI_LEGACY_EXTENDED_CAPABILITY) == sizeof(ULONG));
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typedef union _EHCI_HC_STRUCTURAL_PARAMS {
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struct {
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ULONG PortCount : 4;
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ULONG PortPowerControl : 1;
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ULONG Reserved1 : 2;
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ULONG PortRouteRules : 1;
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ULONG PortsPerCompanion : 4;
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ULONG CompanionControllers : 4;
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ULONG PortIndicators : 1;
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ULONG Reserved2 : 3;
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ULONG DebugPortNumber : 4; //Optional
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ULONG Reserved3 : 8;
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};
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ULONG AsULONG;
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} EHCI_HC_STRUCTURAL_PARAMS;
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C_ASSERT(sizeof(EHCI_HC_STRUCTURAL_PARAMS) == sizeof(ULONG));
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typedef union _EHCI_HC_CAPABILITY_PARAMS {
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struct {
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ULONG Addressing64bitCapability : 1;
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ULONG IsProgrammableFrameList : 1;
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ULONG IsScheduleParkSupport : 1;
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ULONG Reserved1 : 1;
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ULONG IsoSchedulingThreshold : 4;
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ULONG ExtCapabilitiesPointer : 8; // (EECP)
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ULONG Reserved2 : 16;
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};
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ULONG AsULONG;
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} EHCI_HC_CAPABILITY_PARAMS;
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C_ASSERT(sizeof(EHCI_HC_CAPABILITY_PARAMS) == sizeof(ULONG));
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typedef struct _EHCI_HC_CAPABILITY_REGISTERS {
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UCHAR RegistersLength; // RO
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UCHAR Reserved; // RO
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USHORT InterfaceVersion; // RO
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EHCI_HC_STRUCTURAL_PARAMS StructParameters; // RO
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EHCI_HC_CAPABILITY_PARAMS CapParameters; // RO
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UCHAR CompanionPortRouteDesc[8]; // RO
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} EHCI_HC_CAPABILITY_REGISTERS, *PEHCI_HC_CAPABILITY_REGISTERS;
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typedef union _EHCI_USB_COMMAND {
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struct {
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ULONG Run : 1;
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ULONG Reset : 1;
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ULONG FrameListSize : 2;
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ULONG PeriodicEnable : 1;
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ULONG AsynchronousEnable : 1;
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ULONG InterruptAdvanceDoorbell : 1;
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ULONG LightResetHC : 1; // optional
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ULONG AsynchronousParkModeCount : 2; // optional
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ULONG Reserved1 : 1;
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ULONG AsynchronousParkModeEnable : 1; // optional
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ULONG Reserved2 : 4;
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ULONG InterruptThreshold : 8;
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ULONG Reserved3 : 8;
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};
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ULONG AsULONG;
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} EHCI_USB_COMMAND;
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C_ASSERT(sizeof(EHCI_USB_COMMAND) == sizeof(ULONG));
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typedef union _EHCI_USB_STATUS {
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struct {
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ULONG Interrupt : 1;
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ULONG ErrorInterrupt : 1;
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ULONG PortChangeDetect : 1;
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ULONG FrameListRollover : 1;
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ULONG HostSystemError : 1;
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ULONG InterruptOnAsyncAdvance : 1;
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ULONG Reserved1 : 6;
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ULONG HCHalted : 1;
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ULONG Reclamation : 1;
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ULONG PeriodicStatus : 1;
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ULONG AsynchronousStatus : 1;
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ULONG Reserved2 : 16;
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};
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ULONG AsULONG;
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} EHCI_USB_STATUS;
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C_ASSERT(sizeof(EHCI_USB_STATUS) == sizeof(ULONG));
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#define EHCI_INTERRUPT_MASK 0x3F
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typedef union _EHCI_INTERRUPT_ENABLE {
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struct {
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ULONG Interrupt : 1;
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ULONG ErrorInterrupt : 1;
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ULONG PortChangeInterrupt : 1;
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ULONG FrameListRollover : 1;
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ULONG HostSystemError : 1;
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ULONG InterruptOnAsyncAdvance : 1;
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ULONG Reserved : 26;
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};
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ULONG AsULONG;
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} EHCI_INTERRUPT_ENABLE;
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C_ASSERT(sizeof(EHCI_INTERRUPT_ENABLE) == sizeof(ULONG));
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#define EHCI_LINE_STATUS_K_STATE_LOW_SPEED 1
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#define EHCI_PORT_OWNER_COMPANION_CONTROLLER 1
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typedef union _EHCI_PORT_STATUS_CONTROL {
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struct {
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ULONG CurrentConnectStatus : 1;
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ULONG ConnectStatusChange : 1;
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ULONG PortEnabledDisabled : 1;
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ULONG PortEnableDisableChange : 1;
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ULONG OverCurrentActive : 1;
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ULONG OverCurrentChange : 1;
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ULONG ForcePortResume : 1;
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ULONG Suspend : 1;
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ULONG PortReset : 1;
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ULONG Reserved1 : 1;
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ULONG LineStatus : 2;
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ULONG PortPower : 1;
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ULONG PortOwner : 1;
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ULONG PortIndicatorControl : 2;
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ULONG PortTestControl : 4;
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ULONG WakeOnConnectEnable : 1;
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ULONG WakeOnDisconnectEnable : 1;
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ULONG WakeOnOverCurrentEnable : 1;
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ULONG Reserved2 : 9;
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};
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ULONG AsULONG;
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} EHCI_PORT_STATUS_CONTROL;
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C_ASSERT(sizeof(EHCI_PORT_STATUS_CONTROL) == sizeof(ULONG));
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/* FRINDEX Frame Index Register */
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#define EHCI_FRINDEX_FRAME_MASK 0x7FF
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#define EHCI_FRINDEX_INDEX_MASK 0x3FF
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#define EHCI_CONFIG_FLAG_CONFIGURED 1
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typedef struct _EHCI_HW_REGISTERS {
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EHCI_USB_COMMAND HcCommand; // RO, R/W (field dependent), WO
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EHCI_USB_STATUS HcStatus; // RO, R/W, R/WC, (field dependent)
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EHCI_INTERRUPT_ENABLE HcInterruptEnable; // R/W
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ULONG FrameIndex; // R/W (Writes must be DWord Writes)
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ULONG SegmentSelector; // R/W (Writes must be DWord Writes)
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ULONG PeriodicListBase; // R/W (Writes must be DWord Writes)
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ULONG AsyncListBase; // Read/Write (Writes must be DWord Writes)
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ULONG Reserved[9];
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ULONG ConfigFlag; // R/W
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EHCI_PORT_STATUS_CONTROL PortControl[15]; // (1-15) RO, R/W, R/WC (field dependent)
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} EHCI_HW_REGISTERS, *PEHCI_HW_REGISTERS;
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/* Link Pointer */
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#define EHCI_LINK_TYPE_iTD 0 // isochronous transfer descriptor
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#define EHCI_LINK_TYPE_QH 1 // queue head
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#define EHCI_LINK_TYPE_siTD 2 // split transaction isochronous transfer
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#define EHCI_LINK_TYPE_FSTN 3 // frame span traversal node
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/* Used for QHs and qTDs to mark Pointers as the end */
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#define TERMINATE_POINTER 1
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#define LINK_POINTER_MASK 0xFFFFFFE0
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typedef union _EHCI_LINK_POINTER {
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struct {
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ULONG Terminate : 1;
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ULONG Type : 2;
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ULONG Reserved : 2;
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ULONG Address : 27;
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};
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ULONG AsULONG;
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} EHCI_LINK_POINTER;
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C_ASSERT(sizeof(EHCI_LINK_POINTER) == sizeof(ULONG));
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/* Isochronous (High-Speed) Transfer Descriptor (iTD) */
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typedef union _EHCI_TRANSACTION_CONTROL {
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struct {
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ULONG xOffset : 12;
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ULONG PageSelect : 3;
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ULONG InterruptOnComplete : 1;
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ULONG xLength : 12;
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ULONG Status : 4;
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};
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ULONG AsULONG;
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} EHCI_TRANSACTION_CONTROL;
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C_ASSERT(sizeof(EHCI_TRANSACTION_CONTROL) == sizeof(ULONG));
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typedef union _EHCI_TRANSACTION_BUFFER {
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struct {
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ULONG DeviceAddress : 7;
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ULONG Reserved1 : 1;
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ULONG EndpointNumber : 4;
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ULONG DataBuffer0 : 20;
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};
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struct {
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ULONG MaximumPacketSize : 11;
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ULONG Direction : 1;
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ULONG DataBuffer1 : 20;
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};
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struct {
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ULONG Multi : 2;
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ULONG Reserved2 : 10;
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ULONG DataBuffer2 : 20;
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};
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struct {
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ULONG Reserved3 : 12;
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ULONG DataBuffer : 20;
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};
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ULONG AsULONG;
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} EHCI_TRANSACTION_BUFFER;
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C_ASSERT(sizeof(EHCI_TRANSACTION_BUFFER) == sizeof(ULONG));
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typedef struct _EHCI_ISOCHRONOUS_TD { // must be aligned on a 32-byte boundary
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EHCI_LINK_POINTER NextLink;
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EHCI_TRANSACTION_CONTROL Transaction[8];
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EHCI_TRANSACTION_BUFFER Buffer[7];
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ULONG ExtendedBuffer[7];
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} EHCI_ISOCHRONOUS_TD, *PEHCI_ISOCHRONOUS_TD;
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C_ASSERT(sizeof(EHCI_ISOCHRONOUS_TD) == 92);
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/* Split Transaction Isochronous Transfer Descriptor (siTD) */
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typedef union _EHCI_FS_ENDPOINT_PARAMS {
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struct {
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ULONG DeviceAddress : 7;
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ULONG Reserved1 : 1;
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ULONG EndpointNumber : 4;
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ULONG Reserved2 : 4;
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ULONG HubAddress : 7;
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ULONG Reserved3 : 1;
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ULONG PortNumber : 7;
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ULONG Direction : 1;
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};
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ULONG AsULONG;
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} EHCI_FS_ENDPOINT_PARAMS;
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C_ASSERT(sizeof(EHCI_FS_ENDPOINT_PARAMS) == sizeof(ULONG));
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typedef union _EHCI_MICROFRAME_CONTROL {
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struct {
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ULONG StartMask : 8;
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ULONG CompletionMask : 8;
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ULONG Reserved : 16;
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};
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ULONG AsULONG;
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} EHCI_MICROFRAME_CONTROL;
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C_ASSERT(sizeof(EHCI_MICROFRAME_CONTROL) == sizeof(ULONG));
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typedef union _EHCI_SPLIT_TRANSFER_STATE {
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struct {
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ULONG Status : 8;
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ULONG ProgressMask : 8;
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ULONG TotalBytes : 10;
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ULONG Reserved : 4;
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ULONG PageSelect : 1;
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ULONG InterruptOnComplete : 1;
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};
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ULONG AsULONG;
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} EHCI_SPLIT_TRANSFER_STATE;
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C_ASSERT(sizeof(EHCI_SPLIT_TRANSFER_STATE) == sizeof(ULONG));
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typedef union _EHCI_SPLIT_BUFFER_POINTER {
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struct {
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ULONG CurrentOffset : 12;
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ULONG DataBuffer0 : 20;
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};
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struct {
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ULONG TransactionCount : 3;
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ULONG TransactionPosition : 2;
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ULONG Reserved : 7;
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ULONG DataBuffer1 : 20;
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};
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ULONG AsULONG;
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} EHCI_SPLIT_BUFFER_POINTER;
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C_ASSERT(sizeof(EHCI_SPLIT_BUFFER_POINTER) == sizeof(ULONG));
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typedef struct _EHCI_SPLIT_ISOCHRONOUS_TD { // must be aligned on a 32-byte boundary
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EHCI_LINK_POINTER NextLink;
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EHCI_FS_ENDPOINT_PARAMS EndpointCharacteristics;
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EHCI_MICROFRAME_CONTROL MicroFrameControl;
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EHCI_SPLIT_TRANSFER_STATE TransferState;
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EHCI_SPLIT_BUFFER_POINTER Buffer[2];
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ULONG BackPointer;
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ULONG ExtendedBuffer[2];
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} EHCI_SPLIT_ISOCHRONOUS_TD, *PEHCI_SPLIT_ISOCHRONOUS_TD;
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C_ASSERT(sizeof(EHCI_SPLIT_ISOCHRONOUS_TD) == 36);
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/* Queue Element Transfer Descriptor (qTD) */
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#define EHCI_MAX_QTD_BUFFER_PAGES 5
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#define EHCI_TOKEN_STATUS_ACTIVE (1 << 7)
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#define EHCI_TOKEN_STATUS_HALTED (1 << 6)
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#define EHCI_TOKEN_STATUS_DATA_BUFFER_ERROR (1 << 5)
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#define EHCI_TOKEN_STATUS_BABBLE_DETECTED (1 << 4)
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#define EHCI_TOKEN_STATUS_TRANSACTION_ERROR (1 << 3)
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#define EHCI_TOKEN_STATUS_MISSED_MICROFRAME (1 << 2)
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#define EHCI_TOKEN_STATUS_SPLIT_STATE (1 << 1)
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#define EHCI_TOKEN_STATUS_PING_STATE (1 << 0)
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#define EHCI_TD_TOKEN_PID_OUT 0
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#define EHCI_TD_TOKEN_PID_IN 1
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#define EHCI_TD_TOKEN_PID_SETUP 2
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#define EHCI_TD_TOKEN_PID_RESERVED 3
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typedef union _EHCI_TD_TOKEN {
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struct {
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ULONG Status : 8;
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ULONG PIDCode : 2;
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ULONG ErrorCounter : 2;
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ULONG CurrentPage : 3;
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ULONG InterruptOnComplete : 1;
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ULONG TransferBytes : 15;
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ULONG DataToggle : 1;
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};
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ULONG AsULONG;
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} EHCI_TD_TOKEN, *PEHCI_TD_TOKEN;
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C_ASSERT(sizeof(EHCI_TD_TOKEN) == sizeof(ULONG));
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typedef struct _EHCI_QUEUE_TD { // must be aligned on 32-byte boundaries
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ULONG NextTD;
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ULONG AlternateNextTD;
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EHCI_TD_TOKEN Token;
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ULONG Buffer[5];
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ULONG ExtendedBuffer[5];
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} EHCI_QUEUE_TD, *PEHCI_QUEUE_TD;
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C_ASSERT(sizeof(EHCI_QUEUE_TD) == 52);
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/* Queue Head */
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#define EHCI_QH_EP_FULL_SPEED 0
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#define EHCI_QH_EP_LOW_SPEED 1
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#define EHCI_QH_EP_HIGH_SPEED 2
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typedef union _EHCI_QH_EP_PARAMS {
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struct {
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ULONG DeviceAddress : 7;
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ULONG InactivateOnNextTransaction : 1;
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ULONG EndpointNumber : 4;
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ULONG EndpointSpeed : 2;
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ULONG DataToggleControl : 1;
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ULONG HeadReclamationListFlag : 1;
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ULONG MaximumPacketLength : 11; // corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize).
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ULONG ControlEndpointFlag : 1;
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ULONG NakCountReload : 4;
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};
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ULONG AsULONG;
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} EHCI_QH_EP_PARAMS;
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C_ASSERT(sizeof(EHCI_QH_EP_PARAMS) == sizeof(ULONG));
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typedef union _EHCI_QH_EP_CAPS {
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struct {
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ULONG InterruptMask : 8;
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ULONG SplitCompletionMask : 8;
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ULONG HubAddr : 7;
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ULONG PortNumber : 7;
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ULONG PipeMultiplier : 2;
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};
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ULONG AsULONG;
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} EHCI_QH_EP_CAPS;
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C_ASSERT(sizeof(EHCI_QH_EP_CAPS) == sizeof(ULONG));
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typedef struct _EHCI_QUEUE_HEAD { // must be aligned on 32-byte boundaries
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EHCI_LINK_POINTER HorizontalLink;
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EHCI_QH_EP_PARAMS EndpointParams;
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EHCI_QH_EP_CAPS EndpointCaps;
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ULONG CurrentTD;
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ULONG NextTD;
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ULONG AlternateNextTD;
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EHCI_TD_TOKEN Token;
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ULONG Buffer[5];
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ULONG ExtendedBuffer[5];
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} EHCI_QUEUE_HEAD, *PEHCI_QUEUE_HEAD;
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C_ASSERT(sizeof(EHCI_QUEUE_HEAD) == 68);
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