mirror of
https://github.com/reactos/reactos.git
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208 lines
4.5 KiB
C
208 lines
4.5 KiB
C
/*
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* PROJECT: ReactOS Kernel
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* LICENSE: BSD - See COPYING.ARM in the top level directory
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* FILE: ntoskrnl/mm/ARM3/hypermap.c
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* PURPOSE: ARM Memory Manager Hyperspace Mapping Functionality
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* INCLUDES *******************************************************************/
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#include <ntoskrnl.h>
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#define NDEBUG
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#include <debug.h>
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#define MODULE_INVOLVED_IN_ARM3
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#include <mm/ARM3/miarm.h>
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/* GLOBALS ********************************************************************/
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PMMPTE MmFirstReservedMappingPte, MmLastReservedMappingPte;
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PMMPTE MiFirstReservedZeroingPte;
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MMPTE HyperTemplatePte;
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PEPROCESS HyperProcess;
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KIRQL HyperIrql;
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/* PRIVATE FUNCTIONS **********************************************************/
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PVOID
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NTAPI
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MiMapPageInHyperSpace(IN PEPROCESS Process,
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IN PFN_NUMBER Page,
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IN PKIRQL OldIrql)
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{
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MMPTE TempPte;
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PMMPTE PointerPte;
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PFN_NUMBER Offset;
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//
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// Never accept page 0 or non-physical pages
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//
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ASSERT(Page != 0);
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ASSERT(MiGetPfnEntry(Page) != NULL);
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//
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// Build the PTE
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//
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TempPte = ValidKernelPteLocal;
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TempPte.u.Hard.PageFrameNumber = Page;
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//
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// Pick the first hyperspace PTE
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//
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PointerPte = MmFirstReservedMappingPte;
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//
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// Acquire the hyperlock
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//
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ASSERT(Process == PsGetCurrentProcess());
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KeAcquireSpinLock(&Process->HyperSpaceLock, OldIrql);
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//
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// Now get the first free PTE
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//
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Offset = PFN_FROM_PTE(PointerPte);
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if (!Offset)
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{
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//
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// Reset the PTEs
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//
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Offset = MI_HYPERSPACE_PTES;
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KeFlushProcessTb();
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}
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//
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// Prepare the next PTE
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//
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PointerPte->u.Hard.PageFrameNumber = Offset - 1;
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//
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// Write the current PTE
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//
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PointerPte += Offset;
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MI_WRITE_VALID_PTE(PointerPte, TempPte);
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//
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// Return the address
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//
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return MiPteToAddress(PointerPte);
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}
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VOID
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NTAPI
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MiUnmapPageInHyperSpace(IN PEPROCESS Process,
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IN PVOID Address,
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IN KIRQL OldIrql)
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{
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ASSERT(Process == PsGetCurrentProcess());
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//
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// Blow away the mapping
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//
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MiAddressToPte(Address)->u.Long = 0;
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//
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// Release the hyperlock
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//
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ASSERT(KeGetCurrentIrql() == DISPATCH_LEVEL);
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KeReleaseSpinLock(&Process->HyperSpaceLock, OldIrql);
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}
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PVOID
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NTAPI
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MiMapPagesInZeroSpace(IN PMMPFN Pfn1,
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IN PFN_NUMBER NumberOfPages)
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{
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MMPTE TempPte;
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PMMPTE PointerPte;
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PFN_NUMBER Offset, PageFrameIndex;
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//
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// Sanity checks
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//
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ASSERT(KeGetCurrentIrql() == PASSIVE_LEVEL);
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ASSERT(NumberOfPages != 0);
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ASSERT(NumberOfPages <= (MI_ZERO_PTES - 1));
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//
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// Pick the first zeroing PTE
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//
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PointerPte = MiFirstReservedZeroingPte;
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//
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// Now get the first free PTE
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//
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Offset = PFN_FROM_PTE(PointerPte);
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if (NumberOfPages > Offset)
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{
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//
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// Reset the PTEs
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//
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Offset = MI_ZERO_PTES - 1;
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PointerPte->u.Hard.PageFrameNumber = Offset;
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KeFlushProcessTb();
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}
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//
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// Prepare the next PTE
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//
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PointerPte->u.Hard.PageFrameNumber = Offset - NumberOfPages;
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/* Choose the correct PTE to use, and which template */
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PointerPte += (Offset + 1);
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TempPte = ValidKernelPte;
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/* Make sure the list isn't empty and loop it */
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ASSERT(Pfn1 != (PVOID)LIST_HEAD);
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while (Pfn1 != (PVOID)LIST_HEAD)
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{
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/* Get the page index for this PFN */
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PageFrameIndex = MiGetPfnEntryIndex(Pfn1);
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//
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// Write the PFN
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//
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TempPte.u.Hard.PageFrameNumber = PageFrameIndex;
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//
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// Set the correct PTE to write to, and set its new value
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//
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PointerPte--;
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MI_WRITE_VALID_PTE(PointerPte, TempPte);
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/* Move to the next PFN */
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Pfn1 = (PMMPFN)Pfn1->u1.Flink;
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}
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//
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// Return the address
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//
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return MiPteToAddress(PointerPte);
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}
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VOID
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NTAPI
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MiUnmapPagesInZeroSpace(IN PVOID VirtualAddress,
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IN PFN_NUMBER NumberOfPages)
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{
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PMMPTE PointerPte;
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//
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// Sanity checks
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//
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ASSERT(KeGetCurrentIrql() == PASSIVE_LEVEL);
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ASSERT (NumberOfPages != 0);
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ASSERT (NumberOfPages <= (MI_ZERO_PTES - 1));
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//
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// Get the first PTE for the mapped zero VA
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//
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PointerPte = MiAddressToPte(VirtualAddress);
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//
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// Blow away the mapped zero PTEs
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//
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RtlZeroMemory(PointerPte, NumberOfPages * sizeof(MMPTE));
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}
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