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![Timo Kreuzer](/assets/img/avatar_default.png)
[REACTOS] Misc 64 bit fixes * [NTOS:MM] Allow MEM_DOS_LIM in NtMapViewOfSection on x64 as well * [NTOS:MM] Implement x64 version of MmIsDisabledPage * [HAL] Remove obsolete code * [NTOS:KE] Fix amd64 version of KeContextToTrapFrame and KeTrapFrameToContext * [XDK] Fix CONTEXT_XSTATE definition * [PCNET] Convert physical address types from pointers to PHYSICAL_ADDRESS
501 lines
15 KiB
C
501 lines
15 KiB
C
/*
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* PROJECT: ReactOS Kernel
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* LICENSE: GPL - See COPYING in the top level directory
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* FILE: ntoskrnl/ke/amd64/cpu.c
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* PURPOSE: Routines for CPU-level support
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* PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org)
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* Timo Kreuzer (timo.kreuzer@reactos.org)
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*/
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/* INCLUDES *****************************************************************/
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#include <ntoskrnl.h>
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#define NDEBUG
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#include <debug.h>
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/* FIXME: Local EFLAGS defines not used anywhere else */
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#define EFLAGS_IOPL 0x3000
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#define EFLAGS_NF 0x4000
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#define EFLAGS_RF 0x10000
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#define EFLAGS_ID 0x200000
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/* GLOBALS *******************************************************************/
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/* The Boot TSS */
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KTSS64 KiBootTss;
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/* CPU Features and Flags */
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ULONG KeI386CpuType;
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ULONG KeI386CpuStep;
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ULONG KeI386MachineType;
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ULONG KeI386NpxPresent = 1;
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ULONG KeLargestCacheLine = 0x40;
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ULONG KiDmaIoCoherency = 0;
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BOOLEAN KiSMTProcessorsPresent;
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/* Freeze data */
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KIRQL KiOldIrql;
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ULONG KiFreezeFlag;
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/* Flush data */
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volatile LONG KiTbFlushTimeStamp;
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/* CPU Signatures */
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static const CHAR CmpIntelID[] = "GenuineIntel";
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static const CHAR CmpAmdID[] = "AuthenticAMD";
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static const CHAR CmpCyrixID[] = "CyrixInstead";
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static const CHAR CmpTransmetaID[] = "GenuineTMx86";
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static const CHAR CmpCentaurID[] = "CentaurHauls";
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static const CHAR CmpRiseID[] = "RiseRiseRise";
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/* FUNCTIONS *****************************************************************/
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VOID
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NTAPI
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KiSetProcessorType(VOID)
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{
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CPU_INFO CpuInfo;
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ULONG Stepping, Type;
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/* Do CPUID 1 now */
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KiCpuId(&CpuInfo, 1);
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/*
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* Get the Stepping and Type. The stepping contains both the
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* Model and the Step, while the Type contains the returned Type.
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* We ignore the family.
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*
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* For the stepping, we convert this: zzzzzzxy into this: x0y
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*/
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Stepping = CpuInfo.Eax & 0xF0;
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Stepping <<= 4;
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Stepping += (CpuInfo.Eax & 0xFF);
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Stepping &= 0xF0F;
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Type = CpuInfo.Eax & 0xF00;
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Type >>= 8;
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/* Save them in the PRCB */
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KeGetCurrentPrcb()->CpuID = TRUE;
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KeGetCurrentPrcb()->CpuType = (UCHAR)Type;
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KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping;
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}
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ULONG
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NTAPI
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KiGetCpuVendor(VOID)
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{
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PKPRCB Prcb = KeGetCurrentPrcb();
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CPU_INFO CpuInfo;
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/* Get the Vendor ID and null-terminate it */
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KiCpuId(&CpuInfo, 0);
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/* Copy it to the PRCB and null-terminate it */
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*(ULONG*)&Prcb->VendorString[0] = CpuInfo.Ebx;
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*(ULONG*)&Prcb->VendorString[4] = CpuInfo.Edx;
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*(ULONG*)&Prcb->VendorString[8] = CpuInfo.Ecx;
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Prcb->VendorString[12] = 0;
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/* Now check the CPU Type */
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if (!strcmp((PCHAR)Prcb->VendorString, CmpIntelID))
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{
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return CPU_INTEL;
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}
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else if (!strcmp((PCHAR)Prcb->VendorString, CmpAmdID))
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{
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return CPU_AMD;
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}
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else if (!strcmp((PCHAR)Prcb->VendorString, CmpCentaurID))
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{
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DPRINT1("VIA CPUs not fully supported\n");
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return CPU_VIA;
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}
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else if (!strcmp((PCHAR)Prcb->VendorString, CmpRiseID))
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{
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DPRINT1("Rise CPUs not fully supported\n");
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return 0;
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}
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/* Invalid CPU */
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return CPU_UNKNOWN;
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}
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ULONG
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NTAPI
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KiGetFeatureBits(VOID)
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{
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PKPRCB Prcb = KeGetCurrentPrcb();
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ULONG Vendor;
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ULONG FeatureBits = KF_WORKING_PTE;
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CPU_INFO CpuInfo;
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/* Get the Vendor ID */
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Vendor = KiGetCpuVendor();
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/* Make sure we got a valid vendor ID at least. */
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if (!Vendor) return FeatureBits;
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/* Get the CPUID Info. */
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KiCpuId(&CpuInfo, 1);
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/* Set the initial APIC ID */
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Prcb->InitialApicId = (UCHAR)(CpuInfo.Ebx >> 24);
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/* Convert all CPUID Feature bits into our format */
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if (CpuInfo.Edx & X86_FEATURE_VME) FeatureBits |= KF_V86_VIS | KF_CR4;
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if (CpuInfo.Edx & X86_FEATURE_PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4;
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if (CpuInfo.Edx & X86_FEATURE_TSC) FeatureBits |= KF_RDTSC;
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if (CpuInfo.Edx & X86_FEATURE_CX8) FeatureBits |= KF_CMPXCHG8B;
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if (CpuInfo.Edx & X86_FEATURE_SYSCALL) FeatureBits |= KF_FAST_SYSCALL;
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if (CpuInfo.Edx & X86_FEATURE_MTTR) FeatureBits |= KF_MTRR;
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if (CpuInfo.Edx & X86_FEATURE_PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4;
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if (CpuInfo.Edx & X86_FEATURE_CMOV) FeatureBits |= KF_CMOV;
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if (CpuInfo.Edx & X86_FEATURE_PAT) FeatureBits |= KF_PAT;
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if (CpuInfo.Edx & X86_FEATURE_DS) FeatureBits |= KF_DTS;
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if (CpuInfo.Edx & X86_FEATURE_MMX) FeatureBits |= KF_MMX;
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if (CpuInfo.Edx & X86_FEATURE_FXSR) FeatureBits |= KF_FXSR;
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if (CpuInfo.Edx & X86_FEATURE_SSE) FeatureBits |= KF_XMMI;
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if (CpuInfo.Edx & X86_FEATURE_SSE2) FeatureBits |= KF_XMMI64;
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if (CpuInfo.Ecx & X86_FEATURE_SSE3) FeatureBits |= KF_SSE3;
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//if (CpuInfo.Ecx & X86_FEATURE_MONITOR) FeatureBits |= KF_MONITOR;
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//if (CpuInfo.Ecx & X86_FEATURE_SSSE3) FeatureBits |= KF_SSE3SUP;
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if (CpuInfo.Ecx & X86_FEATURE_CX16) FeatureBits |= KF_CMPXCHG16B;
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//if (CpuInfo.Ecx & X86_FEATURE_SSE41) FeatureBits |= KF_SSE41;
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//if (CpuInfo.Ecx & X86_FEATURE_POPCNT) FeatureBits |= KF_POPCNT;
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if (CpuInfo.Ecx & X86_FEATURE_XSAVE) FeatureBits |= KF_XSTATE;
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/* Check if the CPU has hyper-threading */
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if (CpuInfo.Edx & X86_FEATURE_HT)
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{
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/* Set the number of logical CPUs */
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Prcb->LogicalProcessorsPerPhysicalProcessor = (UCHAR)(CpuInfo.Ebx >> 16);
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if (Prcb->LogicalProcessorsPerPhysicalProcessor > 1)
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{
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/* We're on dual-core */
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KiSMTProcessorsPresent = TRUE;
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}
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}
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else
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{
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/* We only have a single CPU */
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Prcb->LogicalProcessorsPerPhysicalProcessor = 1;
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}
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/* Check extended cpuid features */
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KiCpuId(&CpuInfo, 0x80000000);
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if ((CpuInfo.Eax & 0xffffff00) == 0x80000000)
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{
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/* Check if CPUID 0x80000001 is supported */
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if (CpuInfo.Eax >= 0x80000001)
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{
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/* Check which extended features are available. */
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KiCpuId(&CpuInfo, 0x80000001);
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/* Check if NX-bit is supported */
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if (CpuInfo.Edx & X86_FEATURE_NX) FeatureBits |= KF_NX_BIT;
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/* Now handle each features for each CPU Vendor */
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switch (Vendor)
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{
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case CPU_AMD:
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if (CpuInfo.Edx & 0x80000000) FeatureBits |= KF_3DNOW;
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break;
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}
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}
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}
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/* Return the Feature Bits */
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return FeatureBits;
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}
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VOID
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NTAPI
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KiGetCacheInformation(VOID)
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{
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PKIPCR Pcr = (PKIPCR)KeGetPcr();
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ULONG Vendor;
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ULONG CacheRequests = 0, i;
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ULONG CurrentRegister;
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UCHAR RegisterByte;
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BOOLEAN FirstPass = TRUE;
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CPU_INFO CpuInfo;
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/* Set default L2 size */
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Pcr->SecondLevelCacheSize = 0;
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/* Get the Vendor ID and make sure we support CPUID */
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Vendor = KiGetCpuVendor();
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if (!Vendor) return;
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/* Check the Vendor ID */
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switch (Vendor)
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{
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/* Handle Intel case */
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case CPU_INTEL:
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/*Check if we support CPUID 2 */
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KiCpuId(&CpuInfo, 0);
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if (CpuInfo.Eax >= 2)
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{
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/* We need to loop for the number of times CPUID will tell us to */
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do
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{
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/* Do the CPUID call */
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KiCpuId(&CpuInfo, 2);
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/* Check if it was the first call */
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if (FirstPass)
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{
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/*
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* The number of times to loop is the first byte. Read
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* it and then destroy it so we don't get confused.
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*/
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CacheRequests = CpuInfo.Eax & 0xFF;
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CpuInfo.Eax &= 0xFFFFFF00;
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/* Don't go over this again */
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FirstPass = FALSE;
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}
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/* Loop all 4 registers */
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for (i = 0; i < 4; i++)
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{
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/* Get the current register */
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CurrentRegister = CpuInfo.AsUINT32[i];
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/*
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* If the upper bit is set, then this register should
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* be skipped.
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*/
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if (CurrentRegister & 0x80000000) continue;
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/* Keep looping for every byte inside this register */
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while (CurrentRegister)
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{
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/* Read a byte, skip a byte. */
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RegisterByte = (UCHAR)(CurrentRegister & 0xFF);
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CurrentRegister >>= 8;
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if (!RegisterByte) continue;
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/*
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* Valid values are from 0x40 (0 bytes) to 0x49
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* (32MB), or from 0x80 to 0x89 (same size but
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* 8-way associative.
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*/
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if (((RegisterByte > 0x40) &&
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(RegisterByte <= 0x49)) ||
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((RegisterByte > 0x80) &&
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(RegisterByte <= 0x89)))
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{
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/* Mask out only the first nibble */
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RegisterByte &= 0x0F;
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/* Set the L2 Cache Size */
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Pcr->SecondLevelCacheSize = 0x10000 <<
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RegisterByte;
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}
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}
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}
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} while (--CacheRequests);
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}
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break;
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case CPU_AMD:
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/* Check if we support CPUID 0x80000006 */
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KiCpuId(&CpuInfo, 0x80000000);
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if (CpuInfo.Eax >= 6)
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{
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/* Get 2nd level cache and tlb size */
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KiCpuId(&CpuInfo, 0x80000006);
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/* Set the L2 Cache Size */
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Pcr->SecondLevelCacheSize = (CpuInfo.Ecx & 0xFFFF0000) >> 6;
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}
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break;
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}
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}
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VOID
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NTAPI
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KeFlushCurrentTb(VOID)
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{
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/* Flush the TLB by resetting CR3 */
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__writecr3(__readcr3());
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}
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VOID
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NTAPI
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KiRestoreProcessorControlState(PKPROCESSOR_STATE ProcessorState)
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{
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/* Restore the CR registers */
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__writecr0(ProcessorState->SpecialRegisters.Cr0);
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// __writecr2(ProcessorState->SpecialRegisters.Cr2);
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__writecr3(ProcessorState->SpecialRegisters.Cr3);
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__writecr4(ProcessorState->SpecialRegisters.Cr4);
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__writecr8(ProcessorState->SpecialRegisters.Cr8);
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/* Restore the DR registers */
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__writedr(0, ProcessorState->SpecialRegisters.KernelDr0);
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__writedr(1, ProcessorState->SpecialRegisters.KernelDr1);
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__writedr(2, ProcessorState->SpecialRegisters.KernelDr2);
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__writedr(3, ProcessorState->SpecialRegisters.KernelDr3);
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__writedr(6, ProcessorState->SpecialRegisters.KernelDr6);
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__writedr(7, ProcessorState->SpecialRegisters.KernelDr7);
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/* Restore GDT, IDT, LDT and TSS */
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__lgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
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// __lldt(&ProcessorState->SpecialRegisters.Ldtr);
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// __ltr(&ProcessorState->SpecialRegisters.Tr);
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__lidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
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// __ldmxcsr(&ProcessorState->SpecialRegisters.MxCsr); // FIXME
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// ProcessorState->SpecialRegisters.DebugControl
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// ProcessorState->SpecialRegisters.LastBranchToRip
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// ProcessorState->SpecialRegisters.LastBranchFromRip
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// ProcessorState->SpecialRegisters.LastExceptionToRip
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// ProcessorState->SpecialRegisters.LastExceptionFromRip
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/* Restore MSRs */
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__writemsr(X86_MSR_GSBASE, ProcessorState->SpecialRegisters.MsrGsBase);
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__writemsr(X86_MSR_KERNEL_GSBASE, ProcessorState->SpecialRegisters.MsrGsSwap);
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__writemsr(X86_MSR_STAR, ProcessorState->SpecialRegisters.MsrStar);
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__writemsr(X86_MSR_LSTAR, ProcessorState->SpecialRegisters.MsrLStar);
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__writemsr(X86_MSR_CSTAR, ProcessorState->SpecialRegisters.MsrCStar);
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__writemsr(X86_MSR_SFMASK, ProcessorState->SpecialRegisters.MsrSyscallMask);
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}
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VOID
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NTAPI
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KiSaveProcessorControlState(OUT PKPROCESSOR_STATE ProcessorState)
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{
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/* Save the CR registers */
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ProcessorState->SpecialRegisters.Cr0 = __readcr0();
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ProcessorState->SpecialRegisters.Cr2 = __readcr2();
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ProcessorState->SpecialRegisters.Cr3 = __readcr3();
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ProcessorState->SpecialRegisters.Cr4 = __readcr4();
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ProcessorState->SpecialRegisters.Cr8 = __readcr8();
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/* Save the DR registers */
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ProcessorState->SpecialRegisters.KernelDr0 = __readdr(0);
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ProcessorState->SpecialRegisters.KernelDr1 = __readdr(1);
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ProcessorState->SpecialRegisters.KernelDr2 = __readdr(2);
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ProcessorState->SpecialRegisters.KernelDr3 = __readdr(3);
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ProcessorState->SpecialRegisters.KernelDr6 = __readdr(6);
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ProcessorState->SpecialRegisters.KernelDr7 = __readdr(7);
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/* Save GDT, IDT, LDT and TSS */
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__sgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
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__sldt(&ProcessorState->SpecialRegisters.Ldtr);
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__str(&ProcessorState->SpecialRegisters.Tr);
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__sidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
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// __stmxcsr(&ProcessorState->SpecialRegisters.MxCsr);
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// ProcessorState->SpecialRegisters.DebugControl =
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// ProcessorState->SpecialRegisters.LastBranchToRip =
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// ProcessorState->SpecialRegisters.LastBranchFromRip =
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// ProcessorState->SpecialRegisters.LastExceptionToRip =
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// ProcessorState->SpecialRegisters.LastExceptionFromRip =
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/* Save MSRs */
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ProcessorState->SpecialRegisters.MsrGsBase = __readmsr(X86_MSR_GSBASE);
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ProcessorState->SpecialRegisters.MsrGsSwap = __readmsr(X86_MSR_KERNEL_GSBASE);
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ProcessorState->SpecialRegisters.MsrStar = __readmsr(X86_MSR_STAR);
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ProcessorState->SpecialRegisters.MsrLStar = __readmsr(X86_MSR_LSTAR);
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ProcessorState->SpecialRegisters.MsrCStar = __readmsr(X86_MSR_CSTAR);
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ProcessorState->SpecialRegisters.MsrSyscallMask = __readmsr(X86_MSR_SFMASK);
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}
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VOID
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NTAPI
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KeFlushEntireTb(IN BOOLEAN Invalid,
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IN BOOLEAN AllProcessors)
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{
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KIRQL OldIrql;
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// FIXME: halfplemented
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/* Raise the IRQL for the TB Flush */
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OldIrql = KeRaiseIrqlToSynchLevel();
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/* Flush the TB for the Current CPU, and update the flush stamp */
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KeFlushCurrentTb();
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/* Update the flush stamp and return to original IRQL */
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InterlockedExchangeAdd(&KiTbFlushTimeStamp, 1);
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KeLowerIrql(OldIrql);
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}
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KAFFINITY
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NTAPI
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KeQueryActiveProcessors(VOID)
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{
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PAGED_CODE();
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/* Simply return the number of active processors */
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return KeActiveProcessors;
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}
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NTSTATUS
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NTAPI
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KxSaveFloatingPointState(OUT PKFLOATING_SAVE FloatingState)
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{
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UNREFERENCED_PARAMETER(FloatingState);
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return STATUS_SUCCESS;
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}
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NTSTATUS
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NTAPI
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KxRestoreFloatingPointState(IN PKFLOATING_SAVE FloatingState)
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{
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UNREFERENCED_PARAMETER(FloatingState);
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return STATUS_SUCCESS;
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}
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BOOLEAN
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NTAPI
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KeInvalidateAllCaches(VOID)
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{
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/* Invalidate all caches */
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__wbinvd();
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return TRUE;
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}
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/*
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* @implemented
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*/
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ULONG
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NTAPI
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KeGetRecommendedSharedDataAlignment(VOID)
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{
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/* Return the global variable */
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return KeLargestCacheLine;
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}
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/*
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* @implemented
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*/
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VOID
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__cdecl
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KeSaveStateForHibernate(IN PKPROCESSOR_STATE State)
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{
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/* Capture the context */
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RtlCaptureContext(&State->ContextFrame);
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/* Capture the control state */
|
|
KiSaveProcessorControlState(State);
|
|
}
|
|
|
|
/*
|
|
* @implemented
|
|
*/
|
|
VOID
|
|
NTAPI
|
|
KeSetDmaIoCoherency(IN ULONG Coherency)
|
|
{
|
|
/* Save the coherency globally */
|
|
KiDmaIoCoherency = Coherency;
|
|
}
|