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69 lines
3.1 KiB
C
69 lines
3.1 KiB
C
/*
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* ReactOS AMD PCNet Driver
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*
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* Copyright (C) 2003 Vizzini <vizzini@plasmic.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* PURPOSE:
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* PCI configuration constants
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* REVISIONS:
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* 01-Sept-2003 vizzini - Created
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*/
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#pragma once
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/* PCI Config Space Offset Definitions */
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#define PCI_PCIID 0x0 /* pci id - query 32 bits */
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#define PCI_VENID 0x0 /* vendor ID */
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#define PCI_DEVID 0x2 /* device ID */
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#define PCI_COMMAND 0x4 /* command register */
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#define PCI_STATUS 0x6 /* status register */
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#define PCI_REVID 0x8 /* revision ID */
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#define PCI_PIR 0x9 /* programming interface register */
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#define PCI_SCR 0xa /* sub-class register */
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#define PCI_BCR 0xb /* base-class register */
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#define PCI_LTR 0xd /* latency timer register */
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#define PCI_HTR 0xe /* header type register */
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#define PCI_IOBAR 0x10 /* i/o base address register */
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#define PCI_MMBAR 0x14 /* i/o memory-mapped base address register */
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#define PCI_ERBAR 0x30 /* expansion rom base address register */
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#define PCI_ILR 0x3c /* interrupt line register */
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#define PCI_IPR 0x3d /* interrupt pin register */
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#define PCI_MINGNT 0x3e /* min_gnt register */
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#define PCI_MAXLAT 0x3f /* max_lat register */
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/* PCI Command Register Bits */
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#define PCI_IOEN 0x1 /* i/o space access enable */
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#define PCI_MEMEN 0x2 /* memory space access enable */
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#define PCI_BMEN 0x4 /* bus master enable */
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#define PCI_SCYCEN 0x8 /* special cycle enable */
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#define PCI_MWIEN 0X10 /* memory write and invalidate cycle enable */
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#define PCI_VGASNOOP 0x20 /* vga palette snoop */
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#define PCI_PERREN 0x40 /* parity error response enable */
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#define PCI_ADSTEP 0x80 /* address/data stepping */
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#define PCI_SERREN 0x100 /* signalled error enable */
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#define PCI_FBTBEN 0X200 /* fast back-to-back enable */
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/* PCI Status Register Bits */
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#define PCI_FBTBC 0x80 /* fast back-to-back capable */
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#define PCI_DATAPERR 0x100 /* data parity error detected */
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#define PCI_DEVSEL1 0x200 /* device select timing lsb */
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#define PCI_DEVSEL2 0x400 /* device select timing msb */
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#define PCI_STABORT 0x800 /* send target abort */
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#define PCI_RTABORT 0x1000 /* received target abort */
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#define PCI_SERR 0x2000 /* signalled error */
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#define PCI_PERR 0x4000 /* parity error */
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