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390 lines
13 KiB
C
390 lines
13 KiB
C
/*
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* This file contains NDIS driver VirtIO callbacks
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*
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* Copyright (c) 2008-2017 Red Hat, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met :
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and / or other materials provided with the distribution.
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* 3. Neither the names of the copyright holders nor the names of their contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED.IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "ndis56common.h"
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/////////////////////////////////////////////////////////////////////////////////////
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//
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// ReadVirtIODeviceRegister\WriteVirtIODeviceRegister
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// NDIS specific implementation of the IO and memory space read\write
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//
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// The lower 64k of memory is never mapped so we can use the same routines
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// for both port I/O and memory access and use the address alone to decide
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// which space to use.
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/////////////////////////////////////////////////////////////////////////////////////
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#define PORT_MASK 0xFFFF
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static u32 ReadVirtIODeviceRegister(ULONG_PTR ulRegister)
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{
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ULONG ulValue;
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if (ulRegister & ~PORT_MASK) {
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NdisReadRegisterUlong(ulRegister, &ulValue);
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} else {
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NdisRawReadPortUlong(ulRegister, &ulValue);
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}
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DPrintf(6, ("[%s]R[%x]=%x", __FUNCTION__, (ULONG)ulRegister, ulValue));
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return ulValue;
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}
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static void WriteVirtIODeviceRegister(ULONG_PTR ulRegister, u32 ulValue)
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{
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DPrintf(6, ("[%s]R[%x]=%x", __FUNCTION__, (ULONG)ulRegister, ulValue));
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if (ulRegister & ~PORT_MASK) {
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NdisWriteRegisterUlong((PULONG)ulRegister, ulValue);
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} else {
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NdisRawWritePortUlong(ulRegister, ulValue);
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}
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}
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static u8 ReadVirtIODeviceByte(ULONG_PTR ulRegister)
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{
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u8 bValue;
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if (ulRegister & ~PORT_MASK) {
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NdisReadRegisterUchar(ulRegister, &bValue);
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} else {
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NdisRawReadPortUchar(ulRegister, &bValue);
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}
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DPrintf(6, ("[%s]R[%x]=%x", __FUNCTION__, (ULONG)ulRegister, bValue));
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return bValue;
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}
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static void WriteVirtIODeviceByte(ULONG_PTR ulRegister, u8 bValue)
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{
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DPrintf(6, ("[%s]R[%x]=%x", __FUNCTION__, (ULONG)ulRegister, bValue));
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if (ulRegister & ~PORT_MASK) {
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NdisWriteRegisterUchar((PUCHAR)ulRegister, bValue);
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} else {
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NdisRawWritePortUchar(ulRegister, bValue);
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}
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}
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static u16 ReadVirtIODeviceWord(ULONG_PTR ulRegister)
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{
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u16 wValue;
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if (ulRegister & ~PORT_MASK) {
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NdisReadRegisterUshort(ulRegister, &wValue);
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} else {
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NdisRawReadPortUshort(ulRegister, &wValue);
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}
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DPrintf(6, ("[%s]R[%x]=%x\n", __FUNCTION__, (ULONG)ulRegister, wValue));
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return wValue;
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}
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static void WriteVirtIODeviceWord(ULONG_PTR ulRegister, u16 wValue)
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{
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#if 1
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if (ulRegister & ~PORT_MASK) {
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NdisWriteRegisterUshort((PUSHORT)ulRegister, wValue);
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} else {
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NdisRawWritePortUshort(ulRegister, wValue);
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}
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#else
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// test only to cause long TX waiting queue of NDIS packets
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// to recognize it and request for reset via Hang handler
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static int nCounterToFail = 0;
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static const int StartFail = 200, StopFail = 600;
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BOOLEAN bFail = FALSE;
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DPrintf(6, ("%s> R[%x] = %x\n", __FUNCTION__, (ULONG)ulRegister, wValue));
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if ((ulRegister & 0x1F) == 0x10)
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{
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nCounterToFail++;
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bFail = nCounterToFail >= StartFail && nCounterToFail < StopFail;
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}
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if (!bFail) NdisRawWritePortUshort(ulRegister, wValue);
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else
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{
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DPrintf(0, ("%s> FAILING R[%x] = %x\n", __FUNCTION__, (ULONG)ulRegister, wValue));
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}
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#endif
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}
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static void *mem_alloc_contiguous_pages(void *context, size_t size)
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{
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PARANDIS_ADAPTER *pContext = (PARANDIS_ADAPTER *)context;
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PVOID retVal = NULL;
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ULONG i;
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/* find the first unused memory range of the requested size */
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for (i = 0; i < MAX_NUM_OF_QUEUES; i++) {
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if (pContext->SharedMemoryRanges[i].pBase != NULL &&
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pContext->SharedMemoryRanges[i].bUsed == FALSE &&
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pContext->SharedMemoryRanges[i].uLength == (ULONG)size) {
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retVal = pContext->SharedMemoryRanges[i].pBase;
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pContext->SharedMemoryRanges[i].bUsed = TRUE;
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break;
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}
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}
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if (!retVal) {
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/* find the first null memory range descriptor and allocate */
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for (i = 0; i < MAX_NUM_OF_QUEUES; i++) {
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if (pContext->SharedMemoryRanges[i].pBase == NULL) {
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break;
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}
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}
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if (i < MAX_NUM_OF_QUEUES) {
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NdisMAllocateSharedMemory(
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pContext->MiniportHandle,
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(ULONG)size,
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TRUE /* Cached */,
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&pContext->SharedMemoryRanges[i].pBase,
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&pContext->SharedMemoryRanges[i].BasePA);
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retVal = pContext->SharedMemoryRanges[i].pBase;
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if (retVal) {
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NdisZeroMemory(retVal, size);
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pContext->SharedMemoryRanges[i].uLength = (ULONG)size;
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pContext->SharedMemoryRanges[i].bUsed = TRUE;
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}
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}
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}
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if (retVal) {
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DPrintf(6, ("[%s] returning %p, size %x\n", __FUNCTION__, retVal, (ULONG)size));
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} else {
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DPrintf(0, ("[%s] failed to allocate size %x\n", __FUNCTION__, (ULONG)size));
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}
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return retVal;
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}
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static void mem_free_contiguous_pages(void *context, void *virt)
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{
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PARANDIS_ADAPTER *pContext = (PARANDIS_ADAPTER *)context;
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ULONG i;
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for (i = 0; i < MAX_NUM_OF_QUEUES; i++) {
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if (pContext->SharedMemoryRanges[i].pBase == virt) {
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pContext->SharedMemoryRanges[i].bUsed = FALSE;
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break;
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}
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}
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if (i < MAX_NUM_OF_QUEUES) {
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DPrintf(6, ("[%s] freed %p at index %d\n", __FUNCTION__, virt, i));
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} else {
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DPrintf(0, ("[%s] failed to free %p\n", __FUNCTION__, virt));
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}
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}
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static ULONGLONG mem_get_physical_address(void *context, void *virt)
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{
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PARANDIS_ADAPTER *pContext = (PARANDIS_ADAPTER *)context;
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ULONG_PTR uAddr = (ULONG_PTR)virt;
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ULONG i;
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for (i = 0; i < MAX_NUM_OF_QUEUES; i++) {
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ULONG_PTR uBase = (ULONG_PTR)pContext->SharedMemoryRanges[i].pBase;
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if (uAddr >= uBase && uAddr < (uBase + pContext->SharedMemoryRanges[i].uLength)) {
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ULONGLONG retVal = pContext->SharedMemoryRanges[i].BasePA.QuadPart + (uAddr - uBase);
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DPrintf(6, ("[%s] translated %p to %I64X\n", __FUNCTION__, virt, retVal));
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return retVal;
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}
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}
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DPrintf(0, ("[%s] failed to translate %p\n", __FUNCTION__, virt));
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return 0;
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}
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static void *mem_alloc_nonpaged_block(void *context, size_t size)
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{
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PVOID retVal;
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if (NdisAllocateMemoryWithTag(
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&retVal,
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(UINT)size,
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PARANDIS_MEMORY_TAG) != NDIS_STATUS_SUCCESS) {
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retVal = NULL;
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}
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if (retVal) {
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NdisZeroMemory(retVal, size);
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DPrintf(6, ("[%s] returning %p, len %x\n", __FUNCTION__, retVal, (ULONG)size));
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} else {
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DPrintf(0, ("[%s] failed to allocate size %x\n", __FUNCTION__, (ULONG)size));
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}
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return retVal;
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}
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static void mem_free_nonpaged_block(void *context, void *addr)
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{
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UNREFERENCED_PARAMETER(context);
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NdisFreeMemory(addr, 0, 0);
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DPrintf(6, ("[%s] freed %p\n", __FUNCTION__, addr));
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}
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static int PCIReadConfig(PPARANDIS_ADAPTER pContext,
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int where,
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void *buffer,
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size_t length)
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{
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ULONG read;
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read = NdisReadPciSlotInformation(
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pContext->MiniportHandle,
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0 /* SlotNumber */,
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where,
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buffer,
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(ULONG)length);
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if (read == length) {
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DPrintf(6, ("[%s] read %d bytes at %d\n", __FUNCTION__, read, where));
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return 0;
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} else {
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DPrintf(0, ("[%s] failed to read %d bytes at %d\n", __FUNCTION__, read, where));
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return -1;
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}
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}
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static int pci_read_config_byte(void *context, int where, u8 *bVal)
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{
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return PCIReadConfig((PPARANDIS_ADAPTER)context, where, bVal, sizeof(*bVal));
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}
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static int pci_read_config_word(void *context, int where, u16 *wVal)
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{
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return PCIReadConfig((PPARANDIS_ADAPTER)context, where, wVal, sizeof(*wVal));
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}
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static int pci_read_config_dword(void *context, int where, u32 *dwVal)
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{
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return PCIReadConfig((PPARANDIS_ADAPTER)context, where, dwVal, sizeof(*dwVal));
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}
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static size_t pci_get_resource_len(void *context, int bar)
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{
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PARANDIS_ADAPTER *pContext = (PARANDIS_ADAPTER *)context;
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if (bar < PCI_TYPE0_ADDRESSES) {
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return pContext->AdapterResources.PciBars[bar].uLength;
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}
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DPrintf(0, ("[%s] queried invalid BAR %d\n", __FUNCTION__, bar));
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return 0;
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}
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static void *pci_map_address_range(void *context, int bar, size_t offset, size_t maxlen)
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{
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PARANDIS_ADAPTER *pContext = (PARANDIS_ADAPTER *)context;
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if (bar < PCI_TYPE0_ADDRESSES) {
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tBusResource *pRes = &pContext->AdapterResources.PciBars[bar];
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if (pRes->pBase == NULL) {
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/* BAR not mapped yet */
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if (pRes->bPortSpace) {
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if (NDIS_STATUS_SUCCESS == NdisMRegisterIoPortRange(
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&pRes->pBase,
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pContext->MiniportHandle,
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pRes->BasePA.LowPart,
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pRes->uLength)) {
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DPrintf(6, ("[%s] mapped port BAR at %x\n", __FUNCTION__, pRes->BasePA.LowPart));
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} else {
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pRes->pBase = NULL;
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DPrintf(0, ("[%s] failed to map port BAR at %x\n", __FUNCTION__, pRes->BasePA.LowPart));
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}
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} else {
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if (NDIS_STATUS_SUCCESS == NdisMMapIoSpace(
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&pRes->pBase,
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pContext->MiniportHandle,
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pRes->BasePA,
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pRes->uLength)) {
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DPrintf(6, ("[%s] mapped memory BAR at %I64x\n", __FUNCTION__, pRes->BasePA.QuadPart));
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} else {
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pRes->pBase = NULL;
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DPrintf(0, ("[%s] failed to map memory BAR at %I64x\n", __FUNCTION__, pRes->BasePA.QuadPart));
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}
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}
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}
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if (pRes->pBase != NULL && offset < pRes->uLength) {
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if (pRes->bPortSpace) {
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/* use physical address for port I/O */
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return (PUCHAR)(ULONG_PTR)pRes->BasePA.LowPart + offset;
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} else {
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/* use virtual address for memory I/O */
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return (PUCHAR)pRes->pBase + offset;
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}
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} else {
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DPrintf(0, ("[%s] failed to get map BAR %d, offset %x\n", __FUNCTION__, bar, offset));
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}
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} else {
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DPrintf(0, ("[%s] queried invalid BAR %d\n", __FUNCTION__, bar));
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}
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return NULL;
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}
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static u16 vdev_get_msix_vector(void *context, int queue)
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{
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PARANDIS_ADAPTER *pContext = (PARANDIS_ADAPTER *)context;
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u16 vector = VIRTIO_MSI_NO_VECTOR;
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/* we don't run on MSI support so this will never be true */
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if (pContext->bUsingMSIX && queue >= 0) {
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vector = (u16)pContext->AdapterResources.Vector;
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}
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return vector;
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}
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static void vdev_sleep(void *context, unsigned int msecs)
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{
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UNREFERENCED_PARAMETER(context);
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NdisMSleep(1000 * msecs);
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}
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VirtIOSystemOps ParaNdisSystemOps = {
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/* .vdev_read_byte = */ ReadVirtIODeviceByte,
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/* .vdev_read_word = */ ReadVirtIODeviceWord,
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/* .vdev_read_dword = */ ReadVirtIODeviceRegister,
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/* .vdev_write_byte = */ WriteVirtIODeviceByte,
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/* .vdev_write_word = */ WriteVirtIODeviceWord,
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/* .vdev_write_dword = */ WriteVirtIODeviceRegister,
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/* .mem_alloc_contiguous_pages = */ mem_alloc_contiguous_pages,
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/* .mem_free_contiguous_pages = */ mem_free_contiguous_pages,
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/* .mem_get_physical_address = */ mem_get_physical_address,
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/* .mem_alloc_nonpaged_block = */ mem_alloc_nonpaged_block,
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/* .mem_free_nonpaged_block = */ mem_free_nonpaged_block,
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/* .pci_read_config_byte = */ pci_read_config_byte,
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/* .pci_read_config_word = */ pci_read_config_word,
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/* .pci_read_config_dword = */ pci_read_config_dword,
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/* .pci_get_resource_len = */ pci_get_resource_len,
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/* .pci_map_address_range = */ pci_map_address_range,
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/* .vdev_get_msix_vector = */ vdev_get_msix_vector,
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/*.vdev_sleep = */ vdev_sleep,
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};
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