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https://github.com/reactos/reactos.git
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639 lines
15 KiB
C
639 lines
15 KiB
C
#pragma once
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#define PCI_ADDRESS_MEMORY_SPACE 0x00000000
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//
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// Helper Macros
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//
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#define PASTE2(x,y) x ## y
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#define POINTER_TO_(x) PASTE2(P,x)
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#define READ_FROM(x) PASTE2(READ_PORT_, x)
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#define WRITE_TO(x) PASTE2(WRITE_PORT_, x)
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//
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// Declares a PCI Register Read/Write Routine
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//
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#define TYPE_DEFINE(x, y) \
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ULONG \
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NTAPI \
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x( \
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IN PPCIPBUSDATA BusData, \
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IN y PciCfg, \
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IN PUCHAR Buffer, \
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IN ULONG Offset \
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)
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#define TYPE1_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS);
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#define TYPE2_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS);
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//
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// Defines a PCI Register Read/Write Type 1 Routine Prologue and Epilogue
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//
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#define TYPE1_START(x, y) \
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TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS) \
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{ \
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ULONG i = Offset % sizeof(ULONG); \
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PciCfg->u.bits.RegisterNumber = Offset / sizeof(ULONG); \
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WRITE_PORT_ULONG(BusData->Config.Type1.Address, PciCfg->u.AsULONG);
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#define TYPE1_END(y) \
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return sizeof(y); }
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#define TYPE2_END TYPE1_END
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//
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// PCI Register Read Type 1 Routine
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//
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#define TYPE1_READ(x, y) \
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TYPE1_START(x, y) \
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*((POINTER_TO_(y))Buffer) = \
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READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i)); \
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TYPE1_END(y)
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//
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// PCI Register Write Type 1 Routine
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//
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#define TYPE1_WRITE(x, y) \
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TYPE1_START(x, y) \
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WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i), \
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*((POINTER_TO_(y))Buffer)); \
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TYPE1_END(y)
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//
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// Defines a PCI Register Read/Write Type 2 Routine Prologue and Epilogue
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//
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#define TYPE2_START(x, y) \
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TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS) \
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{ \
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PciCfg->u.bits.RegisterNumber = (USHORT)Offset;
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//
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// PCI Register Read Type 2 Routine
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//
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#define TYPE2_READ(x, y) \
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TYPE2_START(x, y) \
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*((POINTER_TO_(y))Buffer) = \
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READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT); \
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TYPE2_END(y)
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//
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// PCI Register Write Type 2 Routine
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//
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#define TYPE2_WRITE(x, y) \
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TYPE2_START(x, y) \
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WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT, \
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*((POINTER_TO_(y))Buffer)); \
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TYPE2_END(y)
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typedef NTSTATUS
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(NTAPI *PciIrqRange)(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER PciSlot,
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OUT PSUPPORTED_RANGE *Interrupt
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);
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typedef struct _PCIPBUSDATA
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{
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PCIBUSDATA CommonData;
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union
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{
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struct
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{
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PULONG Address;
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ULONG Data;
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} Type1;
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struct
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{
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PUCHAR CSE;
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PUCHAR Forward;
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ULONG Base;
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} Type2;
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} Config;
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ULONG MaxDevice;
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PciIrqRange GetIrqRange;
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BOOLEAN BridgeConfigRead;
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UCHAR ParentBus;
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UCHAR Subtractive;
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UCHAR reserved[1];
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UCHAR SwizzleIn[4];
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RTL_BITMAP DeviceConfigured;
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ULONG ConfiguredBits[PCI_MAX_DEVICES * PCI_MAX_FUNCTION / 32];
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} PCIPBUSDATA, *PPCIPBUSDATA;
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typedef ULONG
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(NTAPI *FncConfigIO)(
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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typedef VOID
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(NTAPI *FncSync)(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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IN PVOID State
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);
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typedef VOID
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(NTAPI *FncReleaseSync)(
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IN PBUS_HANDLER BusHandler,
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IN KIRQL Irql
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);
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typedef struct _PCI_CONFIG_HANDLER
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{
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FncSync Synchronize;
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FncReleaseSync ReleaseSynchronzation;
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FncConfigIO ConfigRead[3];
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FncConfigIO ConfigWrite[3];
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} PCI_CONFIG_HANDLER, *PPCI_CONFIG_HANDLER;
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typedef struct _PCI_REGISTRY_INFO_INTERNAL
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{
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UCHAR MajorRevision;
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UCHAR MinorRevision;
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UCHAR NoBuses; // Number Of Buses
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UCHAR HardwareMechanism;
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ULONG ElementCount;
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PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY];
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} PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL;
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//
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// PCI Type 1 Ports
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//
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#define PCI_TYPE1_ADDRESS_PORT (PULONG)0xCF8
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#define PCI_TYPE1_DATA_PORT 0xCFC
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//
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// PCI Type 2 Ports
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//
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#define PCI_TYPE2_CSE_PORT (PUCHAR)0xCF8
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#define PCI_TYPE2_FORWARD_PORT (PUCHAR)0xCFA
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#define PCI_TYPE2_ADDRESS_BASE 0xC
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//
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// PCI Type 1 Configuration Register
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//
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typedef struct _PCI_TYPE1_CFG_BITS
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{
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union
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{
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struct
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{
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ULONG Reserved1:2;
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ULONG RegisterNumber:6;
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ULONG FunctionNumber:3;
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ULONG DeviceNumber:5;
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ULONG BusNumber:8;
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ULONG Reserved2:7;
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ULONG Enable:1;
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} bits;
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ULONG AsULONG;
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} u;
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} PCI_TYPE1_CFG_BITS, *PPCI_TYPE1_CFG_BITS;
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//
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// PCI Type 2 CSE Register
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//
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typedef struct _PCI_TYPE2_CSE_BITS
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{
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union
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{
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struct
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{
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UCHAR Enable:1;
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UCHAR FunctionNumber:3;
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UCHAR Key:4;
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} bits;
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UCHAR AsUCHAR;
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} u;
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} PCI_TYPE2_CSE_BITS, PPCI_TYPE2_CSE_BITS;
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//
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// PCI Type 2 Address Register
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//
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typedef struct _PCI_TYPE2_ADDRESS_BITS
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{
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union
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{
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struct
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{
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USHORT RegisterNumber:8;
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USHORT Agent:4;
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USHORT AddressBase:4;
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} bits;
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USHORT AsUSHORT;
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} u;
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} PCI_TYPE2_ADDRESS_BITS, *PPCI_TYPE2_ADDRESS_BITS;
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typedef struct _PCI_TYPE0_CFG_CYCLE_BITS
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{
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union
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{
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struct
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{
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ULONG Reserved1:2;
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ULONG RegisterNumber:6;
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ULONG FunctionNumber:3;
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ULONG Reserved2:21;
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} bits;
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ULONG AsULONG;
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} u;
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} PCI_TYPE0_CFG_CYCLE_BITS, *PPCI_TYPE0_CFG_CYCLE_BITS;
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typedef union _PCI_TYPE1_CFG_CYCLE_BITS
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{
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struct
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{
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ULONG InUse:2;
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ULONG RegisterNumber:6;
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ULONG FunctionNumber:3;
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ULONG DeviceNumber:5;
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ULONG BusNumber:8;
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ULONG Reserved2:8;
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};
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ULONG AsULONG;
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} PCI_TYPE1_CFG_CYCLE_BITS, *PPCI_TYPE1_CFG_CYCLE_BITS;
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typedef struct _ARRAY
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{
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ULONG ArraySize;
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PVOID Element[ANYSIZE_ARRAY];
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} ARRAY, *PARRAY;
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typedef struct _HAL_BUS_HANDLER
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{
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LIST_ENTRY AllHandlers;
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ULONG ReferenceCount;
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BUS_HANDLER Handler;
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} HAL_BUS_HANDLER, *PHAL_BUS_HANDLER;
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/* FUNCTIONS *****************************************************************/
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/* SHARED (Fake PCI-BUS HANDLER) */
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extern PCI_CONFIG_HANDLER PCIConfigHandler;
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extern PCI_CONFIG_HANDLER PCIConfigHandlerType1;
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extern PCI_CONFIG_HANDLER PCIConfigHandlerType2;
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CODE_SEG("INIT")
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PPCI_REGISTRY_INFO_INTERNAL
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NTAPI
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HalpQueryPciRegistryInfo(
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VOID
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);
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VOID
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NTAPI
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HalpPCISynchronizeType1(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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IN PPCI_TYPE1_CFG_BITS PciCfg
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);
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VOID
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NTAPI
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HalpPCIReleaseSynchronzationType1(
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IN PBUS_HANDLER BusHandler,
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IN KIRQL Irql
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);
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VOID
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NTAPI
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HalpPCISynchronizeType2(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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IN PPCI_TYPE2_ADDRESS_BITS PciCfg
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);
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VOID
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NTAPI
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HalpPCIReleaseSynchronizationType2(
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IN PBUS_HANDLER BusHandler,
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IN KIRQL Irql
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);
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TYPE1_DEFINE(HalpPCIReadUcharType1);
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TYPE1_DEFINE(HalpPCIReadUshortType1);
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TYPE1_DEFINE(HalpPCIReadUlongType1);
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TYPE2_DEFINE(HalpPCIReadUcharType2);
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TYPE2_DEFINE(HalpPCIReadUshortType2);
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TYPE2_DEFINE(HalpPCIReadUlongType2);
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TYPE1_DEFINE(HalpPCIWriteUcharType1);
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TYPE1_DEFINE(HalpPCIWriteUshortType1);
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TYPE1_DEFINE(HalpPCIWriteUlongType1);
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TYPE2_DEFINE(HalpPCIWriteUcharType2);
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TYPE2_DEFINE(HalpPCIWriteUshortType2);
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TYPE2_DEFINE(HalpPCIWriteUlongType2);
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BOOLEAN
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NTAPI
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HalpValidPCISlot(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot
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);
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VOID
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NTAPI
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HalpReadPCIConfig(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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VOID
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NTAPI
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HalpWritePCIConfig(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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ULONG
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NTAPI
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HalpGetPCIData(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootBusHandler,
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IN ULONG SlotNumber,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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ULONG
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NTAPI
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HalpSetPCIData(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootBusHandler,
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IN ULONG SlotNumber,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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NTSTATUS
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NTAPI
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HalpAssignPCISlotResources(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PUNICODE_STRING RegistryPath,
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IN PUNICODE_STRING DriverClassName OPTIONAL,
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IN PDRIVER_OBJECT DriverObject,
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IN PDEVICE_OBJECT DeviceObject OPTIONAL,
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IN ULONG Slot,
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IN OUT PCM_RESOURCE_LIST *pAllocatedResources
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);
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CODE_SEG("INIT")
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ULONG
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HalpPhase0GetPciDataByOffset(
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_In_ ULONG Bus,
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_In_ PCI_SLOT_NUMBER PciSlot,
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_Out_writes_bytes_all_(Length) PVOID Buffer,
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_In_ ULONG Offset,
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_In_ ULONG Length);
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CODE_SEG("INIT")
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ULONG
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HalpPhase0SetPciDataByOffset(
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_In_ ULONG Bus,
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_In_ PCI_SLOT_NUMBER PciSlot,
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_In_reads_bytes_(Length) PVOID Buffer,
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_In_ ULONG Offset,
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_In_ ULONG Length);
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/* NON-LEGACY */
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ULONG
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NTAPI
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HalpGetRootInterruptVector(
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_In_ ULONG BusInterruptLevel,
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_In_ ULONG BusInterruptVector,
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_Out_ PKIRQL Irql,
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_Out_ PKAFFINITY Affinity);
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ULONG
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NTAPI
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HalpGetCmosData(
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_In_ ULONG BusNumber,
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_In_ ULONG SlotNumber,
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_Out_writes_bytes_(Length) PVOID Buffer,
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_In_ ULONG Length);
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ULONG
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NTAPI
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HalpSetCmosData(
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_In_ ULONG BusNumber,
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_In_ ULONG SlotNumber,
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_In_reads_bytes_(Length) PVOID Buffer,
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_In_ ULONG Length);
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CODE_SEG("INIT")
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VOID
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NTAPI
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HalpInitializePciBus(
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VOID
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);
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CODE_SEG("INIT")
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VOID
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NTAPI
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HalpInitializePciStubs(
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VOID
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);
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BOOLEAN
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NTAPI
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HalpTranslateBusAddress(
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IN INTERFACE_TYPE InterfaceType,
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IN ULONG BusNumber,
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IN PHYSICAL_ADDRESS BusAddress,
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IN OUT PULONG AddressSpace,
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OUT PPHYSICAL_ADDRESS TranslatedAddress
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);
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NTSTATUS
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NTAPI
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HalpAssignSlotResources(
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IN PUNICODE_STRING RegistryPath,
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IN PUNICODE_STRING DriverClassName,
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IN PDRIVER_OBJECT DriverObject,
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IN PDEVICE_OBJECT DeviceObject,
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IN INTERFACE_TYPE BusType,
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IN ULONG BusNumber,
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IN ULONG SlotNumber,
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IN OUT PCM_RESOURCE_LIST *AllocatedResources
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);
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BOOLEAN
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NTAPI
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HalpFindBusAddressTranslation(
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IN PHYSICAL_ADDRESS BusAddress,
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IN OUT PULONG AddressSpace,
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OUT PPHYSICAL_ADDRESS TranslatedAddress,
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IN OUT PULONG_PTR Context,
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IN BOOLEAN NextBus
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);
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CODE_SEG("INIT")
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VOID
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NTAPI
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HalpRegisterPciDebuggingDeviceInfo(
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VOID
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);
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/* LEGACY */
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BOOLEAN
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NTAPI
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HaliTranslateBusAddress(
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IN INTERFACE_TYPE InterfaceType,
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IN ULONG BusNumber,
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IN PHYSICAL_ADDRESS BusAddress,
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IN OUT PULONG AddressSpace,
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OUT PPHYSICAL_ADDRESS TranslatedAddress
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);
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BOOLEAN
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NTAPI
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HaliFindBusAddressTranslation(
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IN PHYSICAL_ADDRESS BusAddress,
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IN OUT PULONG AddressSpace,
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OUT PPHYSICAL_ADDRESS TranslatedAddress,
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IN OUT PULONG_PTR Context,
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IN BOOLEAN NextBus
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);
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NTSTATUS
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NTAPI
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HalpAdjustPCIResourceList(IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *pResourceList);
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ULONG
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NTAPI
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HalpGetPCIIntOnISABus(IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN ULONG BusInterruptLevel,
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IN ULONG BusInterruptVector,
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OUT PKIRQL Irql,
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OUT PKAFFINITY Affinity);
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VOID
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NTAPI
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HalpPCIPin2ISALine(IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PPCI_COMMON_CONFIG PciData);
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VOID
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NTAPI
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HalpPCIISALine2Pin(IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PPCI_COMMON_CONFIG PciNewData,
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IN PPCI_COMMON_CONFIG PciOldData);
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NTSTATUS
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NTAPI
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HalpGetISAFixedPCIIrq(IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER PciSlot,
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OUT PSUPPORTED_RANGE *Range);
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VOID
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NTAPI
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HalpInitBusHandler(
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VOID
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);
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PBUS_HANDLER
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NTAPI
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HalpContextToBusHandler(
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IN ULONG_PTR ContextValue
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);
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PBUS_HANDLER
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FASTCALL
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HaliReferenceHandlerForConfigSpace(
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IN BUS_DATA_TYPE ConfigType,
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IN ULONG BusNumber
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);
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ULONG
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NTAPI
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HalpNoBusData(
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_In_ PBUS_HANDLER BusHandler,
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_In_ PBUS_HANDLER RootHandler,
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|
_In_ ULONG SlotNumber,
|
|
_In_ PVOID Buffer,
|
|
_In_ ULONG Offset,
|
|
_In_ ULONG Length);
|
|
|
|
ULONG
|
|
NTAPI
|
|
HalpcGetCmosData(
|
|
_In_ PBUS_HANDLER BusHandler,
|
|
_In_ PBUS_HANDLER RootHandler,
|
|
_In_ ULONG SlotNumber,
|
|
_Out_writes_bytes_(Length) PVOID Buffer,
|
|
_In_ ULONG Offset,
|
|
_In_ ULONG Length);
|
|
|
|
ULONG
|
|
NTAPI
|
|
HalpcSetCmosData(
|
|
_In_ PBUS_HANDLER BusHandler,
|
|
_In_ PBUS_HANDLER RootHandler,
|
|
_In_ ULONG SlotNumber,
|
|
_In_reads_bytes_(Length) PVOID Buffer,
|
|
_In_ ULONG Offset,
|
|
_In_ ULONG Length);
|
|
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpTranslateSystemBusAddress(
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PBUS_HANDLER RootHandler,
|
|
IN PHYSICAL_ADDRESS BusAddress,
|
|
IN OUT PULONG AddressSpace,
|
|
OUT PPHYSICAL_ADDRESS TranslatedAddress
|
|
);
|
|
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpTranslateIsaBusAddress(
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PBUS_HANDLER RootHandler,
|
|
IN PHYSICAL_ADDRESS BusAddress,
|
|
IN OUT PULONG AddressSpace,
|
|
OUT PPHYSICAL_ADDRESS TranslatedAddress
|
|
);
|
|
|
|
ULONG
|
|
NTAPI
|
|
HalpGetSystemInterruptVector(
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PBUS_HANDLER RootHandler,
|
|
IN ULONG BusInterruptLevel,
|
|
IN ULONG BusInterruptVector,
|
|
OUT PKIRQL Irql,
|
|
OUT PKAFFINITY Affinity
|
|
);
|
|
|
|
extern ULONG HalpBusType;
|
|
extern BOOLEAN HalpPCIConfigInitialized;
|
|
extern BUS_HANDLER HalpFakePciBusHandler;
|
|
extern ULONG HalpMinPciBus, HalpMaxPciBus;
|
|
extern LIST_ENTRY HalpAllBusHandlers;
|
|
|
|
/* EOF */
|