mirror of
https://github.com/reactos/reactos.git
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115 lines
2.9 KiB
C
115 lines
2.9 KiB
C
/*
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* PROJECT: ReactOS Boot Loader
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* LICENSE: BSD - See COPYING.ARM in the top level directory
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* FILE: boot/armllb/hw/versatile/hwuart.c
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* PURPOSE: LLB UART Initialization Routines for Versatile
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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#include "precomp.h"
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//
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// UART Registers
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//
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#define UART_PL01x_DR (LlbHwVersaUartBase + 0x00)
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#define UART_PL01x_RSR (LlbHwVersaUartBase + 0x04)
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#define UART_PL01x_ECR (LlbHwVersaUartBase + 0x04)
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#define UART_PL01x_FR (LlbHwVersaUartBase + 0x18)
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#define UART_PL011_IBRD (LlbHwVersaUartBase + 0x24)
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#define UART_PL011_FBRD (LlbHwVersaUartBase + 0x28)
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#define UART_PL011_LCRH (LlbHwVersaUartBase + 0x2C)
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#define UART_PL011_CR (LlbHwVersaUartBase + 0x30)
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#define UART_PL011_IMSC (LlbHwVersaUartBase + 0x38)
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//
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// LCR Values
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//
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#define UART_PL011_LCRH_WLEN_8 0x60
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#define UART_PL011_LCRH_FEN 0x10
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//
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// FCR Values
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//
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#define UART_PL011_CR_UARTEN 0x01
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#define UART_PL011_CR_TXE 0x100
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#define UART_PL011_CR_RXE 0x200
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//
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// LSR Values
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//
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#define UART_PL01x_FR_RXFE 0x10
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#define UART_PL01x_FR_TXFF 0x20
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static const ULONG LlbHwVersaUartBase = 0x101F1000;
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/* FUNCTIONS ******************************************************************/
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VOID
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NTAPI
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LlbHwVersaUartInitialize(VOID)
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{
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ULONG Divider, Remainder, Fraction, ClockRate, Baudrate;
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/* Query peripheral rate, hardcore baudrate */
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ClockRate = LlbHwGetPClk();
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Baudrate = 115200;
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/* Calculate baudrate clock divider and remainder */
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Divider = ClockRate / (16 * Baudrate);
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Remainder = ClockRate % (16 * Baudrate);
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/* Calculate the fractional part */
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Fraction = (8 * Remainder / Baudrate) >> 1;
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Fraction += (8 * Remainder / Baudrate) & 1;
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/* Disable interrupts */
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WRITE_REGISTER_ULONG(UART_PL011_CR, 0);
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/* Set the baud rate to 115200 bps */
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WRITE_REGISTER_ULONG(UART_PL011_IBRD, Divider);
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WRITE_REGISTER_ULONG(UART_PL011_FBRD, Fraction);
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/* Set 8 bits for data, 1 stop bit, no parity, FIFO enabled */
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WRITE_REGISTER_ULONG(UART_PL011_LCRH,
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UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN);
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/* Clear and enable FIFO */
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WRITE_REGISTER_ULONG(UART_PL011_CR,
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UART_PL011_CR_UARTEN |
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UART_PL011_CR_TXE |
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UART_PL011_CR_RXE);
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}
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VOID
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NTAPI
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LlbHwUartSendChar(IN CHAR Char)
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{
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/* Send the character */
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WRITE_REGISTER_ULONG(UART_PL01x_DR, Char);
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}
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BOOLEAN
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NTAPI
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LlbHwUartTxReady(VOID)
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{
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/* TX output buffer is ready? */
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return ((READ_REGISTER_ULONG(UART_PL01x_FR) & UART_PL01x_FR_TXFF) == 0);
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}
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ULONG
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NTAPI
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LlbHwGetUartBase(IN ULONG Port)
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{
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if (Port == 0)
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{
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return 0x101F1000;
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}
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else if (Port == 1)
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{
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return 0x101F2000;
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}
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return 0;
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}
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/* EOF */
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