mirror of
https://github.com/reactos/reactos.git
synced 2024-10-30 03:27:31 +00:00
429 lines
12 KiB
C
429 lines
12 KiB
C
/*
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* PROJECT: ReactOS Kernel
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* LICENSE: BSD - See COPYING.ARM in the top level directory
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* FILE: ntoskrnl/ke/arm/kiinit.c
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* PURPOSE: Implements the kernel entry point for ARM machines
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* INCLUDES *******************************************************************/
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#include <ntoskrnl.h>
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#define NDEBUG
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#include <debug.h>
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/* GLOBALS ********************************************************************/
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KINTERRUPT KxUnexpectedInterrupt;
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BOOLEAN KeIsArmV6;
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ULONG KeNumberProcessIds;
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ULONG KeNumberTbEntries;
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ULONG ProcessCount; // PERF
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extern PVOID KiArmVectorTable;
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#define __ARMV6__ KeIsArmV6
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/* FUNCTIONS ******************************************************************/
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VOID
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NTAPI
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KiInitMachineDependent(VOID)
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{
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/* There is nothing to do on ARM */
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return;
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}
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VOID
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NTAPI
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KiInitializeKernel(IN PKPROCESS InitProcess,
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IN PKTHREAD InitThread,
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IN PVOID IdleStack,
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IN PKPRCB Prcb,
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IN CCHAR Number,
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IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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{
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PKIPCR Pcr = (PKIPCR)KeGetPcr();
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ULONG PageDirectory[2];
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ULONG i;
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/* Set the default NX policy (opt-in) */
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SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_OPTIN;
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/* Initialize spinlocks and DPC data */
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KiInitSpinLocks(Prcb, Number);
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/* Set stack pointers */
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Pcr->InitialStack = IdleStack;
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/* Check if this is the Boot CPU */
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if (!Number)
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{
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/* Setup the unexpected interrupt */
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KxUnexpectedInterrupt.DispatchAddress = KiUnexpectedInterrupt;
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for (i = 0; i < 4; i++)
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{
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/* Copy the template code */
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KxUnexpectedInterrupt.DispatchCode[i] = ((PULONG)KiInterruptTemplate)[i];
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}
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/* Set DMA coherency */
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KiDmaIoCoherency = 0;
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/* Sweep D-Cache */
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HalSweepDcache();
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/* Set boot-level flags */
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KeProcessorArchitecture = PROCESSOR_ARCHITECTURE_ARM;
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KeFeatureBits = 0;
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KeProcessorLevel = (USHORT)(Pcr->ProcessorId >> 8);
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KeProcessorRevision = (USHORT)(Pcr->ProcessorId & 0xFF);
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/* Set the current MP Master KPRCB to the Boot PRCB */
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Prcb->MultiThreadSetMaster = Prcb;
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/* Lower to APC_LEVEL */
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KeLowerIrql(APC_LEVEL);
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/* Initialize portable parts of the OS */
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KiInitSystem();
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/* Initialize the Idle Process and the Process Listhead */
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InitializeListHead(&KiProcessListHead);
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PageDirectory[0] = 0;
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PageDirectory[1] = 0;
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KeInitializeProcess(InitProcess,
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0,
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0xFFFFFFFF,
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PageDirectory,
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FALSE);
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InitProcess->QuantumReset = MAXCHAR;
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}
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else
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{
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/* FIXME-V6: See if we want to support MP */
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DPRINT1("ARM MPCore not supported\n");
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}
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/* Setup the Idle Thread */
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KeInitializeThread(InitProcess,
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InitThread,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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IdleStack);
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InitThread->NextProcessor = Number;
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InitThread->Priority = HIGH_PRIORITY;
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InitThread->State = Running;
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InitThread->Affinity = 1 << Number;
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InitThread->WaitIrql = DISPATCH_LEVEL;
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InitProcess->ActiveProcessors = 1 << Number;
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/* HACK for MmUpdatePageDir */
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((PETHREAD)InitThread)->ThreadsProcess = (PEPROCESS)InitProcess;
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/* Set up the thread-related fields in the PRCB */
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Prcb->CurrentThread = InitThread;
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Prcb->NextThread = NULL;
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Prcb->IdleThread = InitThread;
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/* Initialize the Kernel Executive */
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ExpInitializeExecutive(Number, LoaderBlock);
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/* Only do this on the boot CPU */
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if (!Number)
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{
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/* Calculate the time reciprocal */
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KiTimeIncrementReciprocal =
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KiComputeReciprocal(KeMaximumIncrement,
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&KiTimeIncrementShiftCount);
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/* Update DPC Values in case they got updated by the executive */
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Prcb->MaximumDpcQueueDepth = KiMaximumDpcQueueDepth;
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Prcb->MinimumDpcRate = KiMinimumDpcRate;
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Prcb->AdjustDpcThreshold = KiAdjustDpcThreshold;
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}
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/* Raise to Dispatch */
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KfRaiseIrql(DISPATCH_LEVEL);
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/* Set the Idle Priority to 0. This will jump into Phase 1 */
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KeSetPriorityThread(InitThread, 0);
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/* If there's no thread scheduled, put this CPU in the Idle summary */
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KiAcquirePrcbLock(Prcb);
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if (!Prcb->NextThread) KiIdleSummary |= 1 << Number;
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KiReleasePrcbLock(Prcb);
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/* Raise back to HIGH_LEVEL and clear the PRCB for the loader block */
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KfRaiseIrql(HIGH_LEVEL);
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LoaderBlock->Prcb = 0;
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}
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C_ASSERT((PKIPCR)KeGetPcr() == (PKIPCR)0xFFDFF000);
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C_ASSERT((FIELD_OFFSET(KIPCR, FirstLevelDcacheSize) & 4) == 0);
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C_ASSERT(sizeof(KIPCR) <= PAGE_SIZE);
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VOID
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NTAPI
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KiInitializePcr(IN ULONG ProcessorNumber,
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IN PKIPCR Pcr,
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IN PKTHREAD IdleThread,
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IN PVOID PanicStack,
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IN PVOID InterruptStack)
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{
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ULONG i;
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/* Set the Current Thread */
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Pcr->PrcbData.CurrentThread = IdleThread;
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/* Set pointers to ourselves */
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Pcr->Self = (PKPCR)Pcr;
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Pcr->Prcb = &Pcr->PrcbData;
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/* Set the PCR Version */
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Pcr->MajorVersion = PCR_MAJOR_VERSION;
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Pcr->MinorVersion = PCR_MINOR_VERSION;
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/* Set the PCRB Version */
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Pcr->PrcbData.MajorVersion = 1;
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Pcr->PrcbData.MinorVersion = 1;
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/* Set the Build Type */
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Pcr->PrcbData.BuildType = 0;
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#ifndef CONFIG_SMP
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Pcr->PrcbData.BuildType |= PRCB_BUILD_UNIPROCESSOR;
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#endif
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#if DBG
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Pcr->PrcbData.BuildType |= PRCB_BUILD_DEBUG;
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#endif
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/* Set the Processor Number and current Processor Mask */
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Pcr->PrcbData.Number = (UCHAR)ProcessorNumber;
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Pcr->PrcbData.SetMember = 1 << ProcessorNumber;
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/* Set the PRCB for this Processor */
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KiProcessorBlock[ProcessorNumber] = Pcr->Prcb;
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/* Start us out at PASSIVE_LEVEL */
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Pcr->Irql = PASSIVE_LEVEL;
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/* Set the stacks */
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Pcr->PanicStack = PanicStack;
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Pcr->InterruptStack = InterruptStack;
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/* Setup the processor set */
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Pcr->PrcbData.MultiThreadProcessorSet = Pcr->PrcbData.SetMember;
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/* Copy cache information from the loader block */
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Pcr->FirstLevelDcacheSize = KeLoaderBlock->u.Arm.FirstLevelDcacheSize;
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Pcr->SecondLevelDcacheSize = KeLoaderBlock->u.Arm.SecondLevelDcacheSize;
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Pcr->FirstLevelIcacheSize = KeLoaderBlock->u.Arm.FirstLevelIcacheSize;
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Pcr->SecondLevelIcacheSize = KeLoaderBlock->u.Arm.SecondLevelIcacheSize;
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Pcr->FirstLevelDcacheFillSize = KeLoaderBlock->u.Arm.FirstLevelDcacheFillSize;
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Pcr->SecondLevelDcacheFillSize = KeLoaderBlock->u.Arm.SecondLevelDcacheFillSize;
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Pcr->FirstLevelIcacheFillSize = KeLoaderBlock->u.Arm.FirstLevelIcacheFillSize;
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Pcr->SecondLevelIcacheFillSize = KeLoaderBlock->u.Arm.SecondLevelIcacheFillSize;
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/* Set global d-cache fill and alignment values */
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if (!Pcr->SecondLevelDcacheSize)
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{
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/* Use the first level */
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Pcr->DcacheFillSize = Pcr->FirstLevelDcacheSize;
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}
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else
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{
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/* Use the second level */
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Pcr->DcacheFillSize = Pcr->SecondLevelDcacheSize;
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}
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/* Set the alignment */
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Pcr->DcacheAlignment = Pcr->DcacheFillSize - 1;
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/* Set global i-cache fill and alignment values */
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if (!Pcr->SecondLevelIcacheSize)
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{
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/* Use the first level */
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Pcr->IcacheFillSize = Pcr->FirstLevelIcacheSize;
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}
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else
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{
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/* Use the second level */
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Pcr->IcacheFillSize = Pcr->SecondLevelIcacheSize;
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}
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/* Set the alignment */
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Pcr->IcacheAlignment = Pcr->IcacheFillSize - 1;
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/* Set processor information */
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Pcr->ProcessorId = KeArmIdCodeRegisterGet().AsUlong;
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/* Set all interrupt routines to unexpected interrupts as well */
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for (i = 0; i < MAXIMUM_VECTOR; i++)
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{
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/* Point to the same template */
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Pcr->InterruptRoutine[i] = (PVOID)&KxUnexpectedInterrupt.DispatchCode;
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}
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/* Set default stall factor */
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Pcr->StallScaleFactor = 50;
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/* Setup software interrupts */
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Pcr->InterruptRoutine[PASSIVE_LEVEL] = KiPassiveRelease;
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Pcr->InterruptRoutine[APC_LEVEL] = KiApcInterrupt;
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Pcr->InterruptRoutine[DISPATCH_LEVEL] = KiDispatchInterrupt;
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Pcr->ReservedVectors = (1 << PASSIVE_LEVEL) |
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(1 << APC_LEVEL) |
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(1 << DISPATCH_LEVEL) |
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(1 << IPI_LEVEL);
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}
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VOID
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KiInitializeMachineType(VOID)
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{
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/* Detect ARM version */
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KeIsArmV6 = KeArmIdCodeRegisterGet().Architecture >= 7;
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/* Set the number of TLB entries and ASIDs */
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KeNumberTbEntries = 64;
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if (__ARMV6__)
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{
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/* 256 ASIDs on v6/v7 */
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KeNumberProcessIds = 256;
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}
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else
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{
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/* The TLB is VIVT on v4/v5 */
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KeNumberProcessIds = 0;
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}
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}
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VOID
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KiInitializeSystem(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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{
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ULONG Cpu;
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PKTHREAD InitialThread;
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PKPROCESS InitialProcess;
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ARM_CONTROL_REGISTER ControlRegister;
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PKIPCR Pcr = (PKIPCR)KeGetPcr();
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PKTHREAD Thread;
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/* Flush the TLB */
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KeFlushTb();
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/* Save the loader block and get the current CPU */
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KeLoaderBlock = LoaderBlock;
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Cpu = KeNumberProcessors;
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/* Save the initial thread and process */
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InitialThread = (PKTHREAD)LoaderBlock->Thread;
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InitialProcess = (PKPROCESS)LoaderBlock->Process;
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/* Clean the APC List Head */
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InitializeListHead(&InitialThread->ApcState.ApcListHead[KernelMode]);
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/* Initialize the machine type */
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KiInitializeMachineType();
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/* Skip initial setup if this isn't the Boot CPU */
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if (Cpu) goto AppCpuInit;
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/* Initialize the PCR */
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RtlZeroMemory(Pcr, PAGE_SIZE);
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KiInitializePcr(Cpu,
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Pcr,
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InitialThread,
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(PVOID)LoaderBlock->u.Arm.PanicStack,
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(PVOID)LoaderBlock->u.Arm.InterruptStack);
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/* Now sweep caches */
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HalSweepIcache();
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HalSweepDcache();
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/* Set us as the current process */
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InitialThread->ApcState.Process = InitialProcess;
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AppCpuInit:
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/* Setup CPU-related fields */
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Pcr->Number = Cpu;
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Pcr->SetMember = 1 << Cpu;
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Pcr->SetMemberCopy = 1 << Cpu;
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Pcr->PrcbData.SetMember = 1 << Cpu;
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/* Initialize the Processor with HAL */
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HalInitializeProcessor(Cpu, KeLoaderBlock);
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/* Set active processors */
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KeActiveProcessors |= Pcr->SetMember;
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KeNumberProcessors++;
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/* Check if this is the boot CPU */
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if (!Cpu)
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{
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/* Initialize debugging system */
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KdInitSystem(0, KeLoaderBlock);
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/* Check for break-in */
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if (KdPollBreakIn()) DbgBreakPointWithStatus(DBG_STATUS_CONTROL_C);
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}
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/* Raise to HIGH_LEVEL */
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KfRaiseIrql(HIGH_LEVEL);
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/* Set the exception address to high */
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ControlRegister = KeArmControlRegisterGet();
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ControlRegister.HighVectors = TRUE;
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KeArmControlRegisterSet(ControlRegister);
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/* Setup the exception vector table */
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RtlCopyMemory((PVOID)0xFFFF0000, &KiArmVectorTable, 14 * sizeof(PVOID));
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/* Initialize the rest of the kernel now */
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KiInitializeKernel((PKPROCESS)LoaderBlock->Process,
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(PKTHREAD)LoaderBlock->Thread,
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(PVOID)LoaderBlock->KernelStack,
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Pcr->Prcb,
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Pcr->Prcb->Number,
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KeLoaderBlock);
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/* Set the priority of this thread to 0 */
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Thread = KeGetCurrentThread();
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Thread->Priority = 0;
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/* Force interrupts enabled and lower IRQL back to DISPATCH_LEVEL */
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_enable();
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KfLowerIrql(DISPATCH_LEVEL);
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/* Set the right wait IRQL */
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Thread->WaitIrql = DISPATCH_LEVEL;
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/* Jump into the idle loop */
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KiIdleLoop();
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}
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ULONG
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DbgPrintEarly(const char *fmt, ...)
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{
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va_list args;
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unsigned int i;
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char Buffer[1024];
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PCHAR String = Buffer;
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va_start(args, fmt);
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i = vsprintf(Buffer, fmt, args);
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va_end(args);
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/* Output the message */
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while (*String != 0)
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{
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if (*String == '\n')
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{
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KdPortPutByteEx(NULL, '\r');
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}
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KdPortPutByteEx(NULL, *String);
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String++;
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}
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return STATUS_SUCCESS;
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}
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