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192 lines
6.1 KiB
C
192 lines
6.1 KiB
C
/*
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* Copyright 2004-2006, Haiku Inc. All rights reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Michael Lotz <mmlr@mlotz.ch>
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* Niels S. Reedijk
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*/
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#ifndef UHCI_HARDWARE_H
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#define UHCI_HARDWARE_H
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/************************************************************
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* The Registers *
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************************************************************/
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// R/W -- Read/Write
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// R/WC -- Read/Write Clear
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// ** -- Only writable with words!
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// PCI register
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#define PCI_LEGSUP 0xC0
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#define PCI_LEGSUP_USBPIRQDEN 0x2000
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#define PCI_LEGSUP_CLEAR_SMI 0x8f00
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// Registers
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#define UHCI_USBCMD 0x00 // USB Command - word - R/W
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#define UHCI_USBSTS 0x02 // USB Status - word - R/WC
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#define UHCI_USBINTR 0x04 // USB Interrupt Enable - word - R/W
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#define UHCI_FRNUM 0x06 // Frame number - word - R/W**
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#define UHCI_FRBASEADD 0x08 // Frame List BAse Address - dword - R/W
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#define UHCI_SOFMOD 0x0c // Start of Frame Modify - byte - R/W
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#define UHCI_PORTSC1 0x10 // Port 1 Status/Control - word - R/WC**
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#define UHCI_PORTSC2 0x12 // Port 2 Status/Control - word - R/WC**
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// USBCMD
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#define UHCI_USBCMD_RS 0x01 // Run/Stop
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#define UHCI_USBCMD_HCRESET 0x02 // Host Controller Reset
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#define UHCI_USBCMD_GRESET 0x04 // Global Reset
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#define UHCI_USBCMD_EGSM 0x08 // Enter Global Suspend mode
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#define UHCI_USBCMD_FGR 0x10 // Force Global resume
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#define UHCI_USBCMD_SWDBG 0x20 // Software Debug
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#define UHCI_USBCMD_CF 0x40 // Configure Flag
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#define UHCI_USBCMD_MAXP 0x80 // Max packet
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//USBSTS
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#define UHCI_USBSTS_USBINT 0x01 // USB interrupt
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#define UHCI_USBSTS_ERRINT 0x02 // USB error interrupt
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#define UHCI_USBSTS_RESDET 0x04 // Resume Detect
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#define UHCI_USBSTS_HOSTERR 0x08 // Host System Error
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#define UHCI_USBSTS_HCPRERR 0x10 // Host Controller Process error
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#define UHCI_USBSTS_HCHALT 0x20 // HCHalted
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//USBINTR
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#define UHCI_USBINTR_CRC 0x01 // Timeout/ CRC interrupt enable
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#define UHCI_USBINTR_RESUME 0x02 // Resume interrupt enable
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#define UHCI_USBINTR_IOC 0x04 // Interrupt on complete enable
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#define UHCI_USBINTR_SHORT 0x08 // Short packet interrupt enable
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//PORTSC
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#define UHCI_PORTSC_CURSTAT 0x0001 // Current connect status
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#define UHCI_PORTSC_STATCHA 0x0002 // Current connect status change
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#define UHCI_PORTSC_ENABLED 0x0004 // Port enabled/disabled
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#define UHCI_PORTSC_ENABCHA 0x0008 // Change in enabled/disabled
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#define UHCI_PORTSC_LINE_0 0x0010 // The status of D+
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#define UHCI_PORTSC_LINE_1 0x0020 // The status of D-
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#define UHCI_PORTSC_RESUME 0x0040 // Something with the suspend state ???
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#define UHCI_PORTSC_LOWSPEED 0x0100 // Low speed device attached?
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#define UHCI_PORTSC_RESET 0x0200 // Port is in reset
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#define UHCI_PORTSC_SUSPEND 0x1000 // Set port in suspend state
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#define UHCI_PORTSC_DATAMASK 0x13f5 // Mask that excludes the change bits
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/************************************************************
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* Hardware structs *
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************************************************************/
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// Framelist flags
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#define FRAMELIST_TERMINATE 0x1
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#define FRAMELIST_NEXT_IS_QH 0x2
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// Number of frames
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#define NUMBER_OF_FRAMES 1024
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#define MAX_AVAILABLE_BANDWIDTH 900 // Microseconds
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// Represents a Transfer Descriptor (TD)
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typedef struct _UHCI_TRANSFER_DESCRIPTOR
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{
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ULONG LinkPhysical; // Link to next transfer descriptor / queue head
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ULONG Status; // status
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ULONG Token; // packet header
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ULONG BufferPhysical; // pointer to the buffer
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// Software part
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ULONG PhysicalAddress; // Physical address of this descriptor
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PVOID NextLogicalDescriptor;
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ULONG BufferSize; // Size of the buffer
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PVOID BufferLogical; // Logical pointer to the buffer
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PVOID UserBuffer;
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}UHCI_TRANSFER_DESCRIPTOR, *PUHCI_TRANSFER_DESCRIPTOR;
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#define TD_NEXT_IS_QH 0x02
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// Control and Status
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#define TD_CONTROL_SPD (1 << 29)
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#define TD_CONTROL_3_ERRORS (3 << 27)
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#define TD_CONTROL_LOWSPEED (1 << 26)
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#define TD_CONTROL_ISOCHRONOUS (1 << 25)
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#define TD_CONTROL_IOC (1 << 24)
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#define TD_STATUS_ACTIVE (1 << 23)
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#define TD_STATUS_ERROR_STALLED (1 << 22)
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#define TD_STATUS_ERROR_BUFFER (1 << 21)
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#define TD_STATUS_ERROR_BABBLE (1 << 20)
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#define TD_STATUS_ERROR_NAK (1 << 19)
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#define TD_STATUS_ERROR_CRC (1 << 18)
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#define TD_STATUS_ERROR_TIMEOUT (1 << 18)
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#define TD_STATUS_ERROR_BITSTUFF (1 << 17)
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#define TD_STATUS_ACTLEN_MASK 0x07ff
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#define TD_STATUS_ACTLEN_NULL 0x07ff
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// Token
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#define TD_TOKEN_MAXLEN_SHIFT 21
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#define TD_TOKEN_NULL_DATA (0x07ff << TD_TOKEN_MAXLEN_SHIFT)
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#define TD_TOKEN_DATA_TOGGLE_SHIFT 19
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#define TD_TOKEN_DATA1 (1 << TD_TOKEN_DATA_TOGGLE_SHIFT)
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#define TD_TOKEN_SETUP 0x2d
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#define TD_TOKEN_IN 0x69
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#define TD_TOKEN_OUT 0xe1
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#define TD_TOKEN_ENDPTADDR_SHIFT 15
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#define TD_TOKEN_DEVADDR_SHIFT 8
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#define TD_DEPTH_FIRST 0x04
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#define TD_TERMINATE 0x01
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#define TD_ERROR_MASK 0x440000
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#define TD_ERROR_COUNT_SHIFT 27
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#define TD_ERROR_COUNT_MASK 0x03
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#define TD_LINK_MASK 0xfffffff0
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static
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inline
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ULONG
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UHCI_TRANSFER_DESCRIPTOR_MAXIMUM_LENGTH(PUHCI_TRANSFER_DESCRIPTOR Descriptor)
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{
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ULONG Length = (Descriptor->Token >> TD_TOKEN_MAXLEN_SHIFT) + 1;
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if (Length == TD_STATUS_ACTLEN_NULL + 1)
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return 0;
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return Length;
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}
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static
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inline
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ULONG
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UHCI_TRANSFER_DESCRIPTOR_LENGTH(PUHCI_TRANSFER_DESCRIPTOR Descriptor)
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{
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ULONG Length = (Descriptor->Status & TD_STATUS_ACTLEN_MASK) + 1;
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if (Length == TD_STATUS_ACTLEN_NULL + 1)
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return 0;
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return Length;
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}
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// Represents a Queue Head (QH)
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typedef struct _UHCI_QUEUE_HEAD
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{
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// hardware part
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ULONG LinkPhysical; // address
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ULONG ElementPhysical; // next descriptor
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// Software part
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ULONG PhysicalAddress;
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PVOID NextLogicalDescriptor;
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PVOID Request;
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PVOID NextElementDescriptor;
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}UHCI_QUEUE_HEAD, *PUHCI_QUEUE_HEAD;
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#define QH_TERMINATE 0x01
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#define QH_NEXT_IS_QH 0x02
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#define QH_LINK_MASK 0xfffffff0
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#define UHCI_INTERRUPT_QUEUE 0
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#define UHCI_LOW_SPEED_CONTROL_QUEUE 1
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#define UHCI_FULL_SPEED_CONTROL_QUEUE 2
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#define UHCI_BULK_QUEUE 3
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#define UHCI_DEBUG_QUEUE 4
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#endif /* UHCI_HARDWARE_H */
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