mirror of
https://github.com/reactos/reactos.git
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326 lines
8.9 KiB
C
326 lines
8.9 KiB
C
#pragma once
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//
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// Host Controller Capability Registers
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//
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#define EHCI_CAPLENGTH 0x00
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#define EHCI_HCIVERSION 0x02
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#define EHCI_HCSPARAMS 0x04
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#define EHCI_HCCPARAMS 0x08
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#define EHCI_HCSP_PORTROUTE 0x0c
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//
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// Extended Capabilities
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//
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#define EHCI_ECP_SHIFT 8
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#define EHCI_ECP_MASK 0xff
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#define EHCI_LEGSUP_CAPID_MASK 0xff
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#define EHCI_LEGSUP_CAPID 0x01
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#define EHCI_LEGSUP_OSOWNED (1 << 24)
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#define EHCI_LEGSUP_BIOSOWNED (1 << 16)
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//
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// EHCI Operational Registers
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//
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#define EHCI_USBCMD 0x00
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#define EHCI_USBSTS 0x04
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#define EHCI_USBINTR 0x08
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#define EHCI_FRINDEX 0x0C
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#define EHCI_CTRLDSSEGMENT 0x10
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#define EHCI_PERIODICLISTBASE 0x14
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#define EHCI_ASYNCLISTBASE 0x18
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#define EHCI_CONFIGFLAG 0x40
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#define EHCI_PORTSC 0x44
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//
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// Interrupt Register Flags
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//
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#define EHCI_USBINTR_INTE 0x01
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#define EHCI_USBINTR_ERR 0x02
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#define EHCI_USBINTR_PC 0x04
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#define EHCI_USBINTR_FLROVR 0x08
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#define EHCI_USBINTR_HSERR 0x10
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#define EHCI_USBINTR_ASYNC 0x20
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// Bits 6:31 Reserved
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//
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// Status Register Flags
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//
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#define EHCI_STS_INT 0x01
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#define EHCI_STS_ERR 0x02
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#define EHCI_STS_PCD 0x04
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#define EHCI_STS_FLR 0x08
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#define EHCI_STS_FATAL 0x10
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#define EHCI_STS_IAA 0x20
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// Bits 11:6 Reserved
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#define EHCI_STS_HALT 0x1000
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#define EHCI_STS_RECL 0x2000
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#define EHCI_STS_PSS 0x4000
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#define EHCI_STS_ASS 0x8000
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#define EHCI_ERROR_INT (EHCI_STS_FATAL | EHCI_STS_ERR)
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//
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// Port Register Flags
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//
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#define EHCI_PRT_CONNECTED 0x01
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#define EHCI_PRT_CONNECTSTATUSCHANGE 0x02
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#define EHCI_PRT_ENABLED 0x04
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#define EHCI_PRT_ENABLEDSTATUSCHANGE 0x08
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#define EHCI_PRT_OVERCURRENTACTIVE 0x10
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#define EHCI_PRT_OVERCURRENTCHANGE 0x20
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#define EHCI_PRT_FORCERESUME 0x40
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#define EHCI_PRT_SUSPEND 0x80
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#define EHCI_PRT_RESET 0x100
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#define EHCI_PRT_LINESTATUSA 0x400
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#define EHCI_PRT_LINESTATUSB 0x800
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#define EHCI_PRT_POWER 0x1000
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#define EHCI_PRT_RELEASEOWNERSHIP 0x2000
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#define EHCI_PORTSC_DATAMASK 0xffffffd1
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#define EHCI_IS_LOW_SPEED(x) (((x) & EHCI_PRT_LINESTATUSA) && !((x) & EHCI_PRT_LINESTATUSB))
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//
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// Terminate Pointer used for QueueHeads and Element Transfer Descriptors to mark Pointers as the end
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//
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#define TERMINATE_POINTER 0x01
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//
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// QUEUE ELEMENT TRANSFER DESCRIPTOR, defines and structs
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//
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//
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// Token Flags
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//
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#define PID_CODE_OUT_TOKEN 0x00
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#define PID_CODE_IN_TOKEN 0x01
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#define PID_CODE_SETUP_TOKEN 0x02
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#define DO_START_SPLIT 0x00
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#define DO_COMPLETE_SPLIT 0x01
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#define PING_STATE_DO_OUT 0x00
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#define PING_STATE_DO_PING 0x01
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typedef struct _PERIODICFRAMELIST
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{
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PULONG VirtualAddr;
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PHYSICAL_ADDRESS PhysicalAddr;
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ULONG Size;
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} PERIODICFRAMELIST, *PPERIODICFRAMELIST;
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//
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// QUEUE ELEMENT TRANSFER DESCRIPTOR TOKEN
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//
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typedef struct _QETD_TOKEN_BITS
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{
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ULONG PingState:1;
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ULONG SplitTransactionState:1;
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ULONG MissedMicroFrame:1;
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ULONG TransactionError:1;
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ULONG BabbleDetected:1;
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ULONG DataBufferError:1;
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ULONG Halted:1;
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ULONG Active:1;
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ULONG PIDCode:2;
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ULONG ErrorCounter:2;
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ULONG CurrentPage:3;
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ULONG InterruptOnComplete:1;
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ULONG TotalBytesToTransfer:15;
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ULONG DataToggle:1;
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} QETD_TOKEN_BITS, *PQETD_TOKEN_BITS;
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//
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// QUEUE ELEMENT TRANSFER DESCRIPTOR
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//
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typedef struct _QUEUE_TRANSFER_DESCRIPTOR
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{
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//Hardware
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ULONG NextPointer;
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ULONG AlternateNextPointer;
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union
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{
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QETD_TOKEN_BITS Bits;
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ULONG DWord;
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} Token;
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ULONG BufferPointer[5];
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ULONG ExtendedBufferPointer[5];
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//Software
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ULONG PhysicalAddr;
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LIST_ENTRY DescriptorEntry;
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ULONG TotalBytesToTransfer;
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} QUEUE_TRANSFER_DESCRIPTOR, *PQUEUE_TRANSFER_DESCRIPTOR;
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C_ASSERT(FIELD_OFFSET(QUEUE_TRANSFER_DESCRIPTOR, PhysicalAddr) == 0x34);
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//
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// EndPointSpeeds Flags and END_POINT_CHARACTERISTICS
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//
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#define QH_ENDPOINT_FULLSPEED 0x00
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#define QH_ENDPOINT_LOWSPEED 0x01
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#define QH_ENDPOINT_HIGHSPEED 0x02
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typedef struct _END_POINT_CHARACTERISTICS
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{
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ULONG DeviceAddress:7;
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ULONG InactiveOnNextTransaction:1;
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ULONG EndPointNumber:4;
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ULONG EndPointSpeed:2;
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ULONG QEDTDataToggleControl:1;
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ULONG HeadOfReclamation:1;
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ULONG MaximumPacketLength:11;
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ULONG ControlEndPointFlag:1;
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ULONG NakCountReload:4;
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} END_POINT_CHARACTERISTICS, *PEND_POINT_CHARACTERISTICS;
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//
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// Capabilities
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//
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typedef struct _END_POINT_CAPABILITIES
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{
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ULONG InterruptScheduleMask:8;
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ULONG SplitCompletionMask:8;
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ULONG HubAddr:7;
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ULONG PortNumber:7;
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ULONG NumberOfTransactionPerFrame:2;
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} END_POINT_CAPABILITIES, *PEND_POINT_CAPABILITIES;
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//
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// QUEUE HEAD Flags and Struct
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//
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#define QH_TYPE_IDT 0x00
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#define QH_TYPE_QH 0x02
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#define QH_TYPE_SITD 0x04
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#define QH_TYPE_FSTN 0x06
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typedef struct _QUEUE_HEAD
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{
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//Hardware
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ULONG HorizontalLinkPointer;
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END_POINT_CHARACTERISTICS EndPointCharacteristics;
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END_POINT_CAPABILITIES EndPointCapabilities;
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// TERMINATE_POINTER not valid for this member
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ULONG CurrentLinkPointer;
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// TERMINATE_POINTER valid
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ULONG NextPointer;
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// TERMINATE_POINTER valid, bits 1:4 is NAK_COUNTERd
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ULONG AlternateNextPointer;
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// Only DataToggle, InterruptOnComplete, ErrorCounter, PingState valid
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union
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{
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QETD_TOKEN_BITS Bits;
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ULONG DWord;
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} Token;
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ULONG BufferPointer[5];
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ULONG ExtendedBufferPointer[5];
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//Software
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ULONG PhysicalAddr;
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LIST_ENTRY LinkedQueueHeads;
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LIST_ENTRY TransferDescriptorListHead;
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PVOID NextQueueHead;
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PVOID Request;
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} QUEUE_HEAD, *PQUEUE_HEAD;
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C_ASSERT(sizeof(END_POINT_CHARACTERISTICS) == 4);
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C_ASSERT(sizeof(END_POINT_CAPABILITIES) == 4);
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C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, HorizontalLinkPointer) == 0x00);
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C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, EndPointCharacteristics) == 0x04);
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C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, EndPointCapabilities) == 0x08);
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C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, CurrentLinkPointer) == 0xC);
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C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, NextPointer) == 0x10);
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C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, AlternateNextPointer) == 0x14);
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C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, Token) == 0x18);
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C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, BufferPointer) == 0x1C);
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C_ASSERT(FIELD_OFFSET(QUEUE_HEAD, PhysicalAddr) == 0x44);
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//
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// Command register content
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//
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typedef struct _EHCI_USBCMD_CONTENT
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{
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ULONG Run : 1;
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ULONG HCReset : 1;
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ULONG FrameListSize : 2;
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ULONG PeriodicEnable : 1;
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ULONG AsyncEnable : 1;
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ULONG DoorBell : 1;
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ULONG LightReset : 1;
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ULONG AsyncParkCount : 2;
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ULONG Reserved : 1;
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ULONG AsyncParkEnable : 1;
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ULONG Reserved1 : 4;
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ULONG IntThreshold : 8;
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ULONG Reserved2 : 8;
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} EHCI_USBCMD_CONTENT, *PEHCI_USBCMD_CONTENT;
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typedef struct _EHCI_HCS_CONTENT
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{
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ULONG PortCount : 4;
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ULONG PortPowerControl: 1;
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ULONG Reserved : 2;
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ULONG PortRouteRules : 1;
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ULONG PortPerCHC : 4;
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ULONG CHCCount : 4;
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ULONG PortIndicator : 1;
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ULONG Reserved2 : 3;
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ULONG DbgPortNum : 4;
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ULONG Reserved3 : 8;
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} EHCI_HCS_CONTENT, *PEHCI_HCS_CONTENT;
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typedef struct _EHCI_HCC_CONTENT
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{
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ULONG CurAddrBits : 1;
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ULONG VarFrameList : 1;
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ULONG ParkMode : 1;
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ULONG Reserved : 1;
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ULONG IsoSchedThreshold : 4;
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ULONG EECPCapable : 8;
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ULONG Reserved2 : 16;
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} EHCI_HCC_CONTENT, *PEHCI_HCC_CONTENT;
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typedef struct _EHCI_CAPS {
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UCHAR Length;
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UCHAR Reserved;
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USHORT HCIVersion;
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union
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{
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EHCI_HCS_CONTENT HCSParams;
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ULONG HCSParamsLong;
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};
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union
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{
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EHCI_HCC_CONTENT HCCParams;
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ULONG HCCParamsLong;
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};
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UCHAR PortRoute [15];
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} EHCI_CAPS, *PEHCI_CAPS;
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typedef struct
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{
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ULONG PortStatus;
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ULONG PortChange;
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}EHCI_PORT_STATUS;
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#define EHCI_INTERRUPT_ENTRIES_COUNT (10 + 1)
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#define EHCI_VFRAMELIST_ENTRIES_COUNT 128
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#define EHCI_FRAMELIST_ENTRIES_COUNT 1024
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#define MAX_AVAILABLE_BANDWIDTH 125 // Microseconds
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#define EHCI_QH_CAPS_MULT_SHIFT 30 // Transactions per Micro-Frame
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#define EHCI_QH_CAPS_MULT_MASK 0x03
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#define EHCI_QH_CAPS_PORT_SHIFT 23 // Hub Port (Split-Transaction)
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#define EHCI_QH_CAPS_PORT_MASK 0x7f
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#define EHCI_QH_CAPS_HUB_SHIFT 16 // Hub Address (Split-Transaction)
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#define EHCI_QH_CAPS_HUB_MASK 0x7f
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#define EHCI_QH_CAPS_SCM_SHIFT 8 // Split Completion Mask
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#define EHCI_QH_CAPS_SCM_MASK 0xff
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#define EHCI_QH_CAPS_ISM_SHIFT 0 // Interrupt Schedule Mask
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#define EHCI_QH_CAPS_ISM_MASK 0xff
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