mirror of
https://github.com/reactos/reactos.git
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287 lines
7.4 KiB
C
287 lines
7.4 KiB
C
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#pragma once
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#ifdef _M_AMD64
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#define IOAPIC_BASE 0xFFFFFFFFFFFE1000ULL // checkme
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#define ZERO_VECTOR 0x00 // IRQL 00
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#define APC_VECTOR 0x3D // IRQL 01
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#define APIC_SPURIOUS_VECTOR 0x3f
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#define DISPATCH_VECTOR 0x41 // IRQL 02
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#define APIC_GENERIC_VECTOR 0xC1 // IRQL 27
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#define APIC_CLOCK_VECTOR 0xD1 // IRQL 28
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#define APIC_SYNCH_VECTOR 0xD1 // IRQL 28
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#define APIC_IPI_VECTOR 0xE1 // IRQL 29
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#define APIC_ERROR_VECTOR 0xE3
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#define POWERFAIL_VECTOR 0xEF // IRQL 30
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#define APIC_PROFILE_VECTOR 0xFD // IRQL 31
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#define APIC_NMI_VECTOR 0xFF
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#define IrqlToTpr(Irql) (Irql << 4)
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#define IrqlToSoftVector(Irql) ((Irql << 4)|0xf)
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#define TprToIrql(Tpr) ((KIRQL)(Tpr >> 4))
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#define CLOCK2_LEVEL CLOCK_LEVEL
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#else
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#define IOAPIC_BASE 0xFFFE1000 // checkme
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#define ZERO_VECTOR 0x00 // IRQL 00
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#define APIC_SPURIOUS_VECTOR 0x1f
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#define APC_VECTOR 0x3D // IRQL 01
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#define DISPATCH_VECTOR 0x41 // IRQL 02
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#define APIC_GENERIC_VECTOR 0xC1 // IRQL 27
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#define APIC_CLOCK_VECTOR 0xD1 // IRQL 28
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#define APIC_SYNCH_VECTOR 0xD1 // IRQL 28
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#define APIC_IPI_VECTOR 0xE1 // IRQL 29
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#define APIC_ERROR_VECTOR 0xE3
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#define POWERFAIL_VECTOR 0xEF // IRQL 30
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#define APIC_PROFILE_VECTOR 0xFD // IRQL 31
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#define APIC_NMI_VECTOR 0xFF
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#define IrqlToTpr(Irql) (HalpIRQLtoTPR[Irql])
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#define IrqlToSoftVector(Irql) IrqlToTpr(Irql)
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#define TprToIrql(Tpr) (HalVectorToIRQL[Tpr >> 4])
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#endif
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#define MSR_APIC_BASE 0x0000001B
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#define IOAPIC_PHYS_BASE 0xFEC00000
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#define APIC_CLOCK_INDEX 8
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#define ApicLogicalId(Cpu) ((UCHAR)(1<< Cpu))
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/* APIC Register Address Map */
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#define APIC_ID 0x0020 /* Local APIC ID Register (R/W) */
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#define APIC_VER 0x0030 /* Local APIC Version Register (R) */
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#define APIC_TPR 0x0080 /* Task Priority Register (R/W) */
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#define APIC_APR 0x0090 /* Arbitration Priority Register (R) */
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#define APIC_PPR 0x00A0 /* Processor Priority Register (R) */
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#define APIC_EOI 0x00B0 /* EOI Register (W) */
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#define APIC_RRR 0x00C0 /* Remote Read Register () */
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#define APIC_LDR 0x00D0 /* Logical Destination Register (R/W) */
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#define APIC_DFR 0x00E0 /* Destination Format Register (0-27 R, 28-31 R/W) */
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#define APIC_SIVR 0x00F0 /* Spurious Interrupt Vector Register (0-3 R, 4-9 R/W) */
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#define APIC_ISR 0x0100 /* Interrupt Service Register 0-255 (R) */
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#define APIC_TMR 0x0180 /* Trigger Mode Register 0-255 (R) */
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#define APIC_IRR 0x0200 /* Interrupt Request Register 0-255 (r) */
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#define APIC_ESR 0x0280 /* Error Status Register (R) */
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#define APIC_ICR0 0x0300 /* Interrupt Command Register 0-31 (R/W) */
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#define APIC_ICR1 0x0310 /* Interrupt Command Register 32-63 (R/W) */
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#define APIC_TMRLVTR 0x0320 /* Timer Local Vector Table (R/W) */
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#define APIC_THRMLVTR 0x0330 /* Thermal Local Vector Table */
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#define APIC_PCLVTR 0x0340 /* Performance Counter Local Vector Table (R/W) */
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#define APIC_LINT0 0x0350 /* LINT0 Local Vector Table (R/W) */
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#define APIC_LINT1 0x0360 /* LINT1 Local Vector Table (R/W) */
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#define APIC_ERRLVTR 0x0370 /* Error Local Vector Table (R/W) */
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#define APIC_TICR 0x0380 /* Initial Count Register for Timer (R/W) */
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#define APIC_TCCR 0x0390 /* Current Count Register for Timer (R) */
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#define APIC_TDCR 0x03E0 /* Timer Divide Configuration Register (R/W) */
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#define APIC_EAFR 0x0400 /* extended APIC Feature register (R/W) */
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#define APIC_EACR 0x0410 /* Extended APIC Control Register (R/W) */
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#define APIC_SEOI 0x0420 /* Specific End Of Interrupt Register (W) */
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#define APIC_EXT0LVTR 0x0500 /* Extended Interrupt 0 Local Vector Table */
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#define APIC_EXT1LVTR 0x0510 /* Extended Interrupt 1 Local Vector Table */
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#define APIC_EXT2LVTR 0x0520 /* Extended Interrupt 2 Local Vector Table */
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#define APIC_EXT3LVTR 0x0530 /* Extended Interrupt 3 Local Vector Table */
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enum
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{
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APIC_MT_Fixed = 0,
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APIC_MT_LowestPriority = 1,
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APIC_MT_SMI = 2,
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APIC_MT_RemoteRead = 3,
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APIC_MT_NMI = 4,
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APIC_MT_INIT = 5,
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APIC_MT_Startup = 6,
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APIC_MT_ExtInt = 7,
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};
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enum
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{
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APIC_TGM_Edge,
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APIC_TGM_Level
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};
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enum
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{
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APIC_DM_Physical,
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APIC_DM_Logical
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};
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enum
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{
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APIC_DSH_Destination,
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APIC_DSH_Self,
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APIC_DSH_AllIncludingSelf,
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APIC_DSH_AllExclusingSelf
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};
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enum
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{
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APIC_DF_Flat = 0xFFFFFFFF,
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APIC_DF_Cluster = 0x0FFFFFFF
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};
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enum
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{
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TIMER_DV_DivideBy2 = 0,
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TIMER_DV_DivideBy4 = 1,
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TIMER_DV_DivideBy8 = 2,
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TIMER_DV_DivideBy16 = 3,
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TIMER_DV_DivideBy32 = 8,
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TIMER_DV_DivideBy64 = 9,
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TIMER_DV_DivideBy128 = 10,
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TIMER_DV_DivideBy1 = 11,
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};
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typedef union _APIC_BASE_ADRESS_REGISTER
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{
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ULONG64 Long;
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struct
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{
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ULONG64 Reserved1:8;
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ULONG64 BootStrapCPUCore:1;
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ULONG64 Reserved2:2;
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ULONG64 Enable:1;
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ULONG64 BaseAddress:40;
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ULONG64 ReservedMBZ:12;
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};
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} APIC_BASE_ADRESS_REGISTER;
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typedef union _APIC_SPURIOUS_INERRUPT_REGISTER
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{
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ULONG Long;
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struct
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{
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ULONG Vector:8;
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ULONG SoftwareEnable:1;
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ULONG FocusCPUCoreChecking:1;
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ULONG ReservedMBZ:22;
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};
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} APIC_SPURIOUS_INERRUPT_REGISTER;
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typedef union
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{
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ULONG Long;
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struct
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{
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ULONG Version:8;
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ULONG ReservedMBZ:8;
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ULONG MaxLVT:8;
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ULONG ReservedMBZ1:7;
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ULONG ExtRegSpacePresent:1;
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};
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} APIC_VERSION_REGISTER;
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typedef union
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{
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ULONG Long;
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struct
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{
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ULONG Version:1;
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ULONG SEOIEnable:1;
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ULONG ExtApicIdEnable:1;
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ULONG ReservedMBZ:29;
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};
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} APIC_EXTENDED_CONTROL_REGISTER;
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typedef union _APIC_COMMAND_REGISTER
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{
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ULONGLONG LongLong;
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struct
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{
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ULONG Long0;
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ULONG Long1;
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};
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struct
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{
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ULONGLONG Vector:8;
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ULONGLONG MessageType:3;
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ULONGLONG DestinationMode:1;
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ULONGLONG DeliveryStatus:1;
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ULONGLONG ReservedMBZ:1;
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ULONGLONG Level:1;
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ULONGLONG TriggerMode:1;
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ULONGLONG RemoteReadStatus:2;
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ULONGLONG DestinationShortHand:2;
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ULONGLONG Reserved2MBZ:36;
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ULONGLONG Destination:8;
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};
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} APIC_COMMAND_REGISTER;
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typedef union
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{
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ULONG Long;
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struct
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{
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ULONG Vector:8;
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ULONG MessageType:3;
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ULONG ReservedMBZ:1;
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ULONG DeliveryStatus:1;
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ULONG Reserved1MBZ:1;
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ULONG RemoteIRR:1;
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ULONG TriggerMode:1;
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ULONG Mask:1;
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ULONG TimerMode:1;
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ULONG Reserved2MBZ:13;
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};
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} LVT_REGISTER;
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enum
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{
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IOAPIC_IOREGSEL = 0x00,
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IOAPIC_IOWIN = 0x10
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};
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enum
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{
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IOAPIC_ID = 0x00,
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IOAPIC_VER = 0x01,
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IOAPIC_ARB = 0x02,
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IOAPIC_REDTBL = 0x10
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};
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typedef union _IOAPIC_REDIRECTION_REGISTER
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{
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ULONGLONG LongLong;
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struct
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{
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ULONG Long0;
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ULONG Long1;
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};
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struct
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{
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ULONGLONG Vector:8;
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ULONGLONG DeliveryMode:3;
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ULONGLONG DestinationMode:1;
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ULONGLONG DeliveryStatus:1;
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ULONGLONG Polarity:1;
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ULONGLONG RemoteIRR:1;
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ULONGLONG TriggerMode:1;
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ULONGLONG Mask:1;
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ULONGLONG Reserved:39;
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ULONGLONG Destination:8;
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};
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} IOAPIC_REDIRECTION_REGISTER;
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FORCEINLINE
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ULONG
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ApicRead(ULONG Offset)
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{
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return *(volatile ULONG *)(APIC_BASE + Offset);
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}
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FORCEINLINE
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VOID
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ApicWrite(ULONG Offset, ULONG Value)
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{
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*(volatile ULONG *)(APIC_BASE + Offset) = Value;
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}
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VOID
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NTAPI
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ApicInitializeTimer(ULONG Cpu);
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VOID
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NTAPI
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HalInitializeProfiling(VOID);
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VOID __cdecl ApicSpuriousService(VOID);
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