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168 lines
5 KiB
C
168 lines
5 KiB
C
#pragma once
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#define _MI_PAGING_LEVELS 2
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#define PDE_SHIFT 20
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//
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// Number of bits corresponding to the area that a coarse page table entry represents (4KB)
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//
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#define PTE_SHIFT 12
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#define PTE_SIZE (1 << PTE_SHIFT)
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//
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// Number of bits corresponding to the area that a coarse page table occupies (1KB)
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//
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#define CPT_SHIFT 10
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#define CPT_SIZE (1 << CPT_SHIFT)
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//
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// Base Addresses
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//
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#define PTE_BASE 0xC0000000
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#define PTE_TOP 0xC03FFFFF
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#define PDE_BASE 0xC0400000
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#define PDE_TOP 0xC04FFFFF
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#define HYPER_SPACE 0xC0500000
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#if 0
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typedef struct _HARDWARE_PDE_ARMV6
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{
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ULONG Valid:1; // Only for small pages
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ULONG LargePage:1; // Note, if large then Valid = 0
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ULONG Buffered:1;
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ULONG Cached:1;
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ULONG NoExecute:1;
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ULONG Domain:4;
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ULONG Ecc:1;
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ULONG PageFrameNumber:22;
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} HARDWARE_PDE_ARMV6, *PHARDWARE_PDE_ARMV6;
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typedef struct _HARDWARE_LARGE_PTE_ARMV6
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{
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ULONG Valid:1; // Only for small pages
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ULONG LargePage:1; // Note, if large then Valid = 0
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ULONG Buffered:1;
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ULONG Cached:1;
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ULONG NoExecute:1;
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ULONG Domain:4;
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ULONG Ecc:1;
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ULONG Accessed:1;
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ULONG Owner:1;
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ULONG CacheAttributes:3;
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ULONG ReadOnly:1;
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ULONG Shared:1;
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ULONG NonGlobal:1;
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ULONG SuperLagePage:1;
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ULONG Reserved:1;
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ULONG PageFrameNumber:12;
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} HARDWARE_LARGE_PTE_ARMV6, *PHARDWARE_LARGE_PTE_ARMV6;
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typedef struct _HARDWARE_PTE_ARMV6
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{
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ULONG NoExecute:1;
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ULONG Valid:1;
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ULONG Buffered:1;
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ULONG Cached:1;
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ULONG Accessed:1;
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ULONG Owner:1;
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ULONG CacheAttributes:3;
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ULONG ReadOnly:1;
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ULONG Shared:1;
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ULONG NonGlobal:1;
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ULONG PageFrameNumber:20;
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} HARDWARE_PTE_ARMV6, *PHARDWARE_PTE_ARMV6;
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C_ASSERT(sizeof(HARDWARE_PDE_ARMV6) == sizeof(ULONG));
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C_ASSERT(sizeof(HARDWARE_LARGE_PTE_ARMV6) == sizeof(ULONG));
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C_ASSERT(sizeof(HARDWARE_PTE_ARMV6) == sizeof(ULONG));
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#endif
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/* For FreeLDR */
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typedef struct _PAGE_TABLE_ARM
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{
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HARDWARE_PTE_ARMV6 Pte[1024];
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} PAGE_TABLE_ARM, *PPAGE_TABLE_ARM;
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typedef struct _PAGE_DIRECTORY_ARM
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{
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union
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{
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HARDWARE_PDE_ARMV6 Pde[4096];
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HARDWARE_LARGE_PTE_ARMV6 Pte[4096];
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};
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} PAGE_DIRECTORY_ARM, *PPAGE_DIRECTORY_ARM;
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C_ASSERT(sizeof(PAGE_TABLE_ARM) == PAGE_SIZE);
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C_ASSERT(sizeof(PAGE_DIRECTORY_ARM) == (4 * PAGE_SIZE));
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typedef enum _ARM_DOMAIN
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{
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FaultDomain,
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ClientDomain,
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InvalidDomain,
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ManagerDomain
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} ARM_DOMAIN;
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struct _EPROCESS;
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PULONG MmGetPageDirectory(VOID);
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#define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.NonGlobal = 1)
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#define MI_MAKE_DIRTY_PAGE(x)
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#define MI_MAKE_ACCESSED_PAGE(x)
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#define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
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#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.ReadOnly = 0)
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#define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.Cached = 0)
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#define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.Buffered = 0)
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#define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.Buffered = 1)
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#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.ReadOnly == 0)
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#define MI_IS_PAGE_COPY_ON_WRITE(x)FALSE
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#define MI_IS_PAGE_DIRTY(x) TRUE
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#define MI_IS_PAGE_LARGE(x) FALSE
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/* Easy accessing PFN in PTE */
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#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
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#define NR_SECTION_PAGE_TABLES 1024
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#define NR_SECTION_PAGE_ENTRIES 256
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/* See PDR definition */
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#define MI_HYPERSPACE_PTES (256 - 1)
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#define MI_ZERO_PTES (32)
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#define MI_MAPPING_RANGE_START ((ULONG)HYPER_SPACE)
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#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
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MI_HYPERSPACE_PTES * PAGE_SIZE)
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#define MI_ZERO_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \
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PAGE_SIZE)
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#define MI_DUMMY_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \
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PAGE_SIZE)
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#define MI_VAD_BITMAP (PMMPTE)(MI_DUMMY_PTE + \
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PAGE_SIZE)
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#define MI_WORKING_SET_LIST (PMMPTE)(MI_VAD_BITMAP + \
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PAGE_SIZE)
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/* Retrives the PDE entry for the given VA */
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#define MiGetPdeAddress(x) ((PMMPDE)(PDE_BASE + (((ULONG)(x) >> 20) << 2)))
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#define MiAddressToPde(x) MiGetPdeAddress(x)
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/* Retrieves the PTE entry for the given VA */
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#define MiGetPteAddress(x) ((PMMPTE)(PTE_BASE + (((ULONG)(x) >> 12) << 2)))
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#define MiAddressToPte(x) MiGetPteAddress(x)
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/* Retrives the PDE offset for the given VA */
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#define MiGetPdeOffset(x) (((ULONG)(x)) >> 20)
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#define MiGetPteOffset(x) ((((ULONG)(x)) << 12) >> 24)
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#define MiAddressToPteOffset(x) MiGetPteOffset(x)
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/* Convert a PTE into a corresponding address */
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#define MiPteToAddress(x) ((PVOID)((ULONG)(x) << 10))
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#define MiPdeToAddress(x) ((PVOID)((ULONG)(x) << 18))
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#define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
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((x) / (4*1024*1024))
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#define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
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((((x)) % (4*1024*1024)) / (4*1024))
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#define MM_CACHE_LINE_SIZE 64
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