mirror of
https://github.com/reactos/reactos.git
synced 2024-11-05 22:26:39 +00:00
342 lines
8.9 KiB
C
342 lines
8.9 KiB
C
/*
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* COPYRIGHT: GPL - See COPYING in the top level directory
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* PROJECT: ReactOS Virtual DOS Machine
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* FILE: pic.c
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* PURPOSE: Programmable Interrupt Controller emulation
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* (Interrupt Controller Adapter (ICA) in Windows terminology)
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* PROGRAMMERS: Aleksandar Andrejevic <theflash AT sdf DOT lonestar DOT org>
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*/
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/* INCLUDES *******************************************************************/
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#define NDEBUG
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#include "emulator.h"
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#include "io.h"
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#include "pic.h"
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/* PRIVATE VARIABLES **********************************************************/
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static PIC MasterPic, SlavePic;
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/* PRIVATE FUNCTIONS **********************************************************/
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static BYTE PicReadCommand(BYTE Port)
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{
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PPIC Pic;
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/* Which PIC are we accessing? */
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if (Port == PIC_MASTER_CMD) Pic = &MasterPic;
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else Pic = &SlavePic;
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if (Pic->ReadIsr)
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{
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/* Read the in-service register */
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Pic->ReadIsr = FALSE;
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return Pic->InServiceRegister;
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}
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else
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{
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/* Read the interrupt request register */
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return Pic->IntRequestRegister;
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}
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}
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static VOID PicWriteCommand(BYTE Port, BYTE Value)
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{
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PPIC Pic;
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/* Which PIC are we accessing? */
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if (Port == PIC_MASTER_CMD) Pic = &MasterPic;
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else Pic = &SlavePic;
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if (Value & PIC_ICW1)
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{
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/* Start initialization */
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Pic->Initialization = TRUE;
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Pic->IntOffset = 0xFF;
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Pic->CascadeRegisterSet = FALSE;
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Pic->ConfigRegister = Value;
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return;
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}
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if (Value & PIC_OCW3)
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{
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/* This is an OCR3 */
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if (Value == PIC_OCW3_READ_ISR)
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{
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/* Return the ISR on next read from command port */
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Pic->ReadIsr = TRUE;
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}
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return;
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}
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/* This is an OCW2 */
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if (Value & PIC_OCW2_EOI)
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{
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if (Value & PIC_OCW2_SL)
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{
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/* If the SL bit is set, clear a specific IRQ */
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Pic->InServiceRegister &= ~(1 << (Value & PIC_OCW2_NUM_MASK));
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}
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else
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{
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/* Otherwise, clear all of them */
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Pic->InServiceRegister = 0;
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}
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}
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}
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static BYTE PicReadData(BYTE Port)
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{
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/* Read the mask register */
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if (Port == PIC_MASTER_DATA) return MasterPic.MaskRegister;
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else return SlavePic.MaskRegister;
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}
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static VOID PicWriteData(BYTE Port, BYTE Value)
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{
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PPIC Pic;
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/* Which PIC are we accessing? */
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if (Port == PIC_MASTER_DATA) Pic = &MasterPic;
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else Pic = &SlavePic;
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/* Is the PIC ready? */
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if (!Pic->Initialization)
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{
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/* Yes, this is an OCW1 */
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Pic->MaskRegister = Value;
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return;
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}
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/* Has the interrupt offset been set? */
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if (Pic->IntOffset == 0xFF)
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{
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/* This is an ICW2, set the offset (last three bits always zero) */
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Pic->IntOffset = Value & 0xF8;
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/* Check if we are in single mode and don't need an ICW4 */
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if ((Pic->ConfigRegister & PIC_ICW1_SINGLE)
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&& !(Pic->ConfigRegister & PIC_ICW1_ICW4))
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{
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/* Yes, done initializing */
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Pic->Initialization = FALSE;
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}
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return;
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}
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/* Check if we are in cascade mode and the cascade register was not set */
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if (!(Pic->ConfigRegister & PIC_ICW1_SINGLE) && !Pic->CascadeRegisterSet)
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{
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/* This is an ICW3 */
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Pic->CascadeRegister = Value;
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Pic->CascadeRegisterSet = TRUE;
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/* Check if we need an ICW4 */
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if (!(Pic->ConfigRegister & PIC_ICW1_ICW4))
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{
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/* No, done initializing */
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Pic->Initialization = FALSE;
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}
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return;
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}
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/* This must be an ICW4, we will ignore the 8086 bit (assume always set) */
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if (Value & PIC_ICW4_AEOI)
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{
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/* Use automatic end-of-interrupt */
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Pic->AutoEoi = TRUE;
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}
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/* Done initializing */
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Pic->Initialization = FALSE;
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}
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static BYTE WINAPI PicReadPort(ULONG Port)
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{
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switch (Port)
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{
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case PIC_MASTER_CMD:
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case PIC_SLAVE_CMD:
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{
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return PicReadCommand(Port);
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}
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case PIC_MASTER_DATA:
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case PIC_SLAVE_DATA:
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{
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return PicReadData(Port);
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}
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}
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return 0;
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}
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static VOID WINAPI PicWritePort(ULONG Port, BYTE Data)
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{
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switch (Port)
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{
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case PIC_MASTER_CMD:
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case PIC_SLAVE_CMD:
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{
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PicWriteCommand(Port, Data);
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break;
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}
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case PIC_MASTER_DATA:
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case PIC_SLAVE_DATA:
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{
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PicWriteData(Port, Data);
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break;
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}
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}
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}
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/* PUBLIC FUNCTIONS ***********************************************************/
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VOID PicInterruptRequest(BYTE Number)
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{
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BYTE i;
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if (/* Number >= 0 && */ Number < 8)
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{
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/* Check if any of the higher-priority interrupts are busy */
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for (i = 0; i <= Number; i++)
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{
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if (MasterPic.InServiceRegister & (1 << Number)) return;
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}
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/* Check if the interrupt is masked */
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if (MasterPic.MaskRegister & (1 << Number)) return;
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/* Set the appropriate bit in the IRR and interrupt the CPU */
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MasterPic.IntRequestRegister |= 1 << Number;
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EmulatorInterruptSignal();
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}
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else if (Number >= 8 && Number < 16)
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{
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Number -= 8;
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/*
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* The slave PIC is connected to IRQ 2, always! If the master PIC
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* was misconfigured, don't do anything.
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*/
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if (!(MasterPic.CascadeRegister & (1 << 2))
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|| SlavePic.CascadeRegister != 2)
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{
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return;
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}
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/* Check if any of the higher-priority interrupts are busy */
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if (MasterPic.InServiceRegister != 0) return;
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for (i = 0; i <= Number; i++)
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{
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if (SlavePic.InServiceRegister & (1 << Number)) return;
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}
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/* Check if the interrupt is masked */
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if (SlavePic.MaskRegister & (1 << Number)) return;
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/* Set the IRQ 2 bit in the master ISR */
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if (!MasterPic.AutoEoi) MasterPic.InServiceRegister |= (1 << 2);
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/* Set the appropriate bit in the IRR and interrupt the CPU */
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SlavePic.IntRequestRegister |= 1 << Number;
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EmulatorInterruptSignal();
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}
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}
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BYTE PicGetInterrupt(VOID)
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{
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INT i, j;
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/* Search interrupts by priority */
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for (i = 0; i < 8; i++)
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{
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/* Check if this line is cascaded to the slave PIC */
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if ((i == 2)
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&& MasterPic.CascadeRegister & (1 << 2)
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&& SlavePic.Slave
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&& (SlavePic.CascadeRegister == 2))
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{
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/* Search the slave PIC interrupts by priority */
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for (j = 0; j < 8; j++) if ((j != 1) && SlavePic.IntRequestRegister & (1 << j))
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{
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/* Clear the IRR flag */
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SlavePic.IntRequestRegister &= ~(1 << j);
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/* Set the ISR flag, unless AEOI is enabled */
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if (!SlavePic.AutoEoi) SlavePic.InServiceRegister |= (1 << j);
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/* Return the interrupt number */
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return SlavePic.IntOffset + j;
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}
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}
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if (MasterPic.IntRequestRegister & (1 << i))
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{
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/* Clear the IRR flag */
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MasterPic.IntRequestRegister &= ~(1 << i);
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/* Set the ISR flag, unless AEOI is enabled */
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if (!MasterPic.AutoEoi) MasterPic.InServiceRegister |= (1 << i);
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/* Return the interrupt number */
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return MasterPic.IntOffset + i;
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}
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}
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/* Spurious interrupt */
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if (MasterPic.InServiceRegister & (1 << 2)) return SlavePic.IntOffset + 7;
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else return MasterPic.IntOffset + 7;
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}
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VOID PicInitialize(VOID)
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{
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/* Register the I/O Ports */
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RegisterIoPort(PIC_MASTER_CMD , PicReadPort, PicWritePort);
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RegisterIoPort(PIC_SLAVE_CMD , PicReadPort, PicWritePort);
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RegisterIoPort(PIC_MASTER_DATA, PicReadPort, PicWritePort);
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RegisterIoPort(PIC_SLAVE_DATA , PicReadPort, PicWritePort);
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}
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VOID
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WINAPI
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call_ica_hw_interrupt(INT ms,
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BYTE line,
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INT count)
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{
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BYTE InterruptNumber = line;
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/* Check for PIC validity */
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if (ms != ICA_MASTER && ms != ICA_SLAVE) return;
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/*
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* Adjust the interrupt request number according to the parameters,
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* by adding an offset == 8 to the interrupt number.
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*
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* Indeed VDDs calling this function usually subtracts 8 so that they give:
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*
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* ms | line | corresponding interrupt number
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* ------------+--------+--------------------------------
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* ICA_MASTER | 0 -- 7 | 0 -- 7
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* ICA_SLAVE | 0 -- 7 | 8 -- 15
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*
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* and PicInterruptRequest subtracts again 8 to the interrupt number
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* if it is greater or equal than 8 (so that it determines which PIC
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* to use via the interrupt number).
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*/
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if (ms == ICA_SLAVE) InterruptNumber += 8;
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/* Send the specified number of interrupt requests */
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while (count-- > 0)
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{
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PicInterruptRequest(InterruptNumber);
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}
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}
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/* EOF */
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