mirror of
https://github.com/reactos/reactos.git
synced 2024-09-05 10:17:16 +00:00
1290 lines
32 KiB
C
1290 lines
32 KiB
C
/*
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* PROJECT: ReactOS HAL
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* LICENSE: BSD - See COPYING.ARM in the top level directory
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* PURPOSE: HAL PIC Management and Control Code
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* INCLUDES *******************************************************************/
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#include <hal.h>
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#define NDEBUG
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#include <debug.h>
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VOID
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NTAPI
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HalpEndSoftwareInterrupt(IN KIRQL OldIrql,
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IN PKTRAP_FRAME TrapFrame);
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/* GLOBALS ********************************************************************/
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#ifndef _MINIHAL_
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/*
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* This table basically keeps track of level vs edge triggered interrupts.
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* Windows has 250+ entries, but it seems stupid to replicate that since the PIC
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* can't actually have that many.
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*
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* When a level interrupt is registered, the respective pointer in this table is
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* modified to point to a dimiss routine for level interrupts instead.
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*
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* The other thing this table does is special case IRQ7, IRQ13 and IRQ15:
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*
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* - If an IRQ line is deasserted before it is acknowledged due to a noise spike
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* generated by an expansion device (since the IRQ line is low during the 1st
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* acknowledge bus cycle), the i8259 will keep the line low for at least 100ns
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* When the spike passes, a pull-up resistor will return the IRQ line to high.
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* Since the PIC requires the input be high until the first acknowledge, the
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* i8259 knows that this was a spurious interrupt, and on the second interrupt
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* acknowledge cycle, it reports this to the CPU. Since no valid interrupt has
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* actually happened Intel hardcoded the chip to report IRQ7 on the master PIC
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* and IRQ15 on the slave PIC (IR7 either way).
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*
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* "ISA System Architecture", 3rd Edition, states that these cases should be
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* handled by reading the respective Interrupt Service Request (ISR) bits from
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* the affected PIC, and validate whether or not IR7 is set. If it isn't, then
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* the interrupt is spurious and should be ignored.
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*
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* Note that for a spurious IRQ15, we DO have to send an EOI to the master for
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* IRQ2 since the line was asserted by the slave when it received the spurious
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* IRQ15!
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*
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* - When the 80287/80387 math co-processor generates an FPU/NPX trap, this is
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* connected to IRQ13, so we have to clear the busy latch on the NPX port.
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*/
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PHAL_DISMISS_INTERRUPT HalpSpecialDismissTable[16] =
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{
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrq07,
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#if defined(SARCH_PC98)
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HalpDismissIrq08,
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#else
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HalpDismissIrqGeneric,
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#endif
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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HalpDismissIrqGeneric,
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#if defined(SARCH_PC98)
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HalpDismissIrqGeneric,
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#else
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HalpDismissIrq13,
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#endif
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HalpDismissIrqGeneric,
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HalpDismissIrq15
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};
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/*
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* These are the level IRQ dismissal functions that get copied in the table
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* above if the given IRQ is actually level triggered.
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*/
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PHAL_DISMISS_INTERRUPT HalpSpecialDismissLevelTable[16] =
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{
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HalpDismissIrqLevel,
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HalpDismissIrqLevel,
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HalpDismissIrqLevel,
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HalpDismissIrqLevel,
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HalpDismissIrqLevel,
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HalpDismissIrqLevel,
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HalpDismissIrqLevel,
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HalpDismissIrq07Level,
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#if defined(SARCH_PC98)
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HalpDismissIrq08Level,
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#else
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HalpDismissIrqLevel,
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#endif
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HalpDismissIrqLevel,
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HalpDismissIrqLevel,
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HalpDismissIrqLevel,
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HalpDismissIrqLevel,
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#if defined(SARCH_PC98)
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HalpDismissIrqLevel,
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#else
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HalpDismissIrq13Level,
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#endif
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HalpDismissIrqLevel,
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HalpDismissIrq15Level
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};
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/* This table contains the static x86 PIC mapping between IRQLs and IRQs */
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extern ULONG KiI8259MaskTable[32];
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/* This table indicates which IRQs, if pending, can preempt a given IRQL level */
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extern ULONG FindHigherIrqlMask[32];
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/* Denotes minimum required IRQL before we can process pending SW interrupts */
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KIRQL SWInterruptLookUpTable[8] =
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{
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PASSIVE_LEVEL, /* IRR 0 */
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PASSIVE_LEVEL, /* IRR 1 */
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APC_LEVEL, /* IRR 2 */
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APC_LEVEL, /* IRR 3 */
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DISPATCH_LEVEL, /* IRR 4 */
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DISPATCH_LEVEL, /* IRR 5 */
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DISPATCH_LEVEL, /* IRR 6 */
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DISPATCH_LEVEL /* IRR 7 */
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};
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#if defined(__GNUC__)
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#define HalpDelayedHardwareInterrupt(x) \
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VOID __cdecl HalpHardwareInterrupt##x(VOID); \
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VOID \
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__cdecl \
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HalpHardwareInterrupt##x(VOID) \
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{ \
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asm volatile ("int $%c0\n"::"i"(PRIMARY_VECTOR_BASE + x)); \
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}
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#elif defined(_MSC_VER)
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#define HalpDelayedHardwareInterrupt(x) \
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VOID __cdecl HalpHardwareInterrupt##x(VOID); \
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VOID \
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__cdecl \
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HalpHardwareInterrupt##x(VOID) \
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{ \
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__asm \
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{ \
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int PRIMARY_VECTOR_BASE + x \
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} \
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}
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#else
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#error Unsupported compiler
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#endif
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/* Pending/delayed hardware interrupt handlers */
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HalpDelayedHardwareInterrupt(0);
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HalpDelayedHardwareInterrupt(1);
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HalpDelayedHardwareInterrupt(2);
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HalpDelayedHardwareInterrupt(3);
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HalpDelayedHardwareInterrupt(4);
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HalpDelayedHardwareInterrupt(5);
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HalpDelayedHardwareInterrupt(6);
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HalpDelayedHardwareInterrupt(7);
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HalpDelayedHardwareInterrupt(8);
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HalpDelayedHardwareInterrupt(9);
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HalpDelayedHardwareInterrupt(10);
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HalpDelayedHardwareInterrupt(11);
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HalpDelayedHardwareInterrupt(12);
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HalpDelayedHardwareInterrupt(13);
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HalpDelayedHardwareInterrupt(14);
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HalpDelayedHardwareInterrupt(15);
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/* Handlers for pending interrupts */
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PHAL_SW_INTERRUPT_HANDLER SWInterruptHandlerTable[20] =
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{
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(PHAL_SW_INTERRUPT_HANDLER)KiUnexpectedInterrupt,
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HalpApcInterrupt,
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HalpDispatchInterrupt,
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(PHAL_SW_INTERRUPT_HANDLER)KiUnexpectedInterrupt,
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HalpHardwareInterrupt0,
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HalpHardwareInterrupt1,
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HalpHardwareInterrupt2,
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HalpHardwareInterrupt3,
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HalpHardwareInterrupt4,
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HalpHardwareInterrupt5,
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HalpHardwareInterrupt6,
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HalpHardwareInterrupt7,
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HalpHardwareInterrupt8,
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HalpHardwareInterrupt9,
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HalpHardwareInterrupt10,
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HalpHardwareInterrupt11,
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HalpHardwareInterrupt12,
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HalpHardwareInterrupt13,
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HalpHardwareInterrupt14,
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HalpHardwareInterrupt15
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};
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/* Handlers for pending software interrupts when we already have a trap frame*/
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PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY SWInterruptHandlerTable2[3] =
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{
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(PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(PVOID)KiUnexpectedInterrupt,
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HalpApcInterrupt2ndEntry,
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HalpDispatchInterrupt2ndEntry
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};
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LONG HalpEisaELCR;
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/* FUNCTIONS ******************************************************************/
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VOID
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NTAPI
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HalpInitializePICs(IN BOOLEAN EnableInterrupts)
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{
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ULONG EFlags;
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EISA_ELCR Elcr;
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ULONG i, j;
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BOOLEAN ElcrFound;
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/* Save EFlags and disable interrupts */
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EFlags = __readeflags();
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_disable();
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/* Initialize and mask the PIC */
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HalpInitializeLegacyPICs();
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/* Read EISA Edge/Level Register for master and slave */
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Elcr.Bits = (__inbyte(EISA_ELCR_SLAVE) << 8) | __inbyte(EISA_ELCR_MASTER);
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#if defined(SARCH_PC98)
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/* Force defaults when ELCR is not supported */
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if (Elcr.Bits == 0xFFFF)
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{
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Elcr.Master.Irq0Level = 0;
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Elcr.Master.Irq1Level = 0;
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Elcr.Master.Irq7Level = 0;
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Elcr.Slave.Irq8Level = 0;
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}
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ElcrFound = TRUE;
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#else
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/* IRQs 0, 1, 2, 8, and 13 are system-reserved and must be edge */
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ElcrFound = (!(Elcr.Master.Irq0Level) && !(Elcr.Master.Irq1Level) && !(Elcr.Master.Irq2Level) &&
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!(Elcr.Slave.Irq8Level) && !(Elcr.Slave.Irq13Level));
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#endif
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if (ElcrFound)
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{
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/* ELCR is as it's supposed to be, save it */
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HalpEisaELCR = Elcr.Bits;
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/* Scan for level interrupts */
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for (i = 1, j = 0; j < 16; i <<= 1, j++)
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{
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if (HalpEisaELCR & i)
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{
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/* Switch handler to level */
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SWInterruptHandlerTable[j + 4] = HalpHardwareInterruptLevel;
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/* Switch dismiss to level */
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HalpSpecialDismissTable[j] = HalpSpecialDismissLevelTable[j];
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}
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}
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}
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/* Report cascade IRQ usage */
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HalpRegisterVector(IDT_INTERNAL,
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PRIMARY_VECTOR_BASE + PIC_CASCADE_IRQ,
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PRIMARY_VECTOR_BASE + PIC_CASCADE_IRQ,
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HIGH_LEVEL);
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/* Restore interrupt state */
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if (EnableInterrupts) EFlags |= EFLAGS_INTERRUPT_MASK;
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__writeeflags(EFlags);
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}
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UCHAR
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FASTCALL
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HalpIrqToVector(UCHAR Irq)
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{
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return (PRIMARY_VECTOR_BASE + Irq);
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}
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UCHAR
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FASTCALL
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HalpVectorToIrq(UCHAR Vector)
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{
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return (Vector - PRIMARY_VECTOR_BASE);
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}
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KIRQL
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FASTCALL
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HalpVectorToIrql(UCHAR Vector)
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{
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return (PROFILE_LEVEL - (Vector - PRIMARY_VECTOR_BASE));
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}
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/* IRQL MANAGEMENT ************************************************************/
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/*
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* @implemented
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*/
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KIRQL
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NTAPI
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KeGetCurrentIrql(VOID)
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{
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/* Return the IRQL */
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return KeGetPcr()->Irql;
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}
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/*
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* @implemented
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*/
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KIRQL
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NTAPI
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KeRaiseIrqlToDpcLevel(VOID)
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{
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PKPCR Pcr = KeGetPcr();
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KIRQL CurrentIrql;
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/* Save and update IRQL */
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CurrentIrql = Pcr->Irql;
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Pcr->Irql = DISPATCH_LEVEL;
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#if DBG
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/* Validate correct raise */
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if (CurrentIrql > DISPATCH_LEVEL) KeBugCheck(IRQL_NOT_GREATER_OR_EQUAL);
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#endif
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/* Return the previous value */
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return CurrentIrql;
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}
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/*
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* @implemented
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*/
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KIRQL
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NTAPI
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KeRaiseIrqlToSynchLevel(VOID)
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{
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PKPCR Pcr = KeGetPcr();
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KIRQL CurrentIrql;
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/* Save and update IRQL */
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CurrentIrql = Pcr->Irql;
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Pcr->Irql = SYNCH_LEVEL;
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#if DBG
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/* Validate correct raise */
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if (CurrentIrql > SYNCH_LEVEL)
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{
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/* Crash system */
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KeBugCheckEx(IRQL_NOT_GREATER_OR_EQUAL,
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CurrentIrql,
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SYNCH_LEVEL,
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0,
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1);
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}
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#endif
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/* Return the previous value */
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return CurrentIrql;
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}
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/*
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* @implemented
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*/
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KIRQL
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FASTCALL
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KfRaiseIrql(IN KIRQL NewIrql)
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{
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PKPCR Pcr = KeGetPcr();
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KIRQL CurrentIrql;
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/* Read current IRQL */
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CurrentIrql = Pcr->Irql;
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#if DBG
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/* Validate correct raise */
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if (CurrentIrql > NewIrql)
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{
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/* Crash system */
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Pcr->Irql = PASSIVE_LEVEL;
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KeBugCheck(IRQL_NOT_GREATER_OR_EQUAL);
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}
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#endif
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/* Set new IRQL */
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Pcr->Irql = NewIrql;
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/* Return old IRQL */
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return CurrentIrql;
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}
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/*
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* @implemented
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*/
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VOID
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FASTCALL
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KfLowerIrql(IN KIRQL OldIrql)
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{
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ULONG EFlags;
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ULONG PendingIrql, PendingIrqlMask;
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PKPCR Pcr = KeGetPcr();
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PIC_MASK Mask;
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#if DBG
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/* Validate correct lower */
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if (OldIrql > Pcr->Irql)
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{
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/* Crash system */
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Pcr->Irql = HIGH_LEVEL;
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KeBugCheck(IRQL_NOT_LESS_OR_EQUAL);
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}
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#endif
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/* Save EFlags and disable interrupts */
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EFlags = __readeflags();
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_disable();
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/* Set old IRQL */
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Pcr->Irql = OldIrql;
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/* Check for pending software interrupts and compare with current IRQL */
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PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
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if (PendingIrqlMask)
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{
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/* Check if pending IRQL affects hardware state */
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BitScanReverse(&PendingIrql, PendingIrqlMask);
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if (PendingIrql > DISPATCH_LEVEL)
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{
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/* Set new PIC mask */
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Mask.Both = Pcr->IDR & 0xFFFF;
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__outbyte(PIC1_DATA_PORT, Mask.Master);
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__outbyte(PIC2_DATA_PORT, Mask.Slave);
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/* Clear IRR bit */
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Pcr->IRR ^= (1 << PendingIrql);
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}
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/* Now handle pending interrupt */
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SWInterruptHandlerTable[PendingIrql]();
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}
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/* Restore interrupt state */
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__writeeflags(EFlags);
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}
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/* SOFTWARE INTERRUPTS ********************************************************/
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/*
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* @implemented
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*/
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VOID
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FASTCALL
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HalRequestSoftwareInterrupt(IN KIRQL Irql)
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{
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ULONG EFlags;
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PKPCR Pcr = KeGetPcr();
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KIRQL PendingIrql;
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/* Save EFlags and disable interrupts */
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EFlags = __readeflags();
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_disable();
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/* Mask out the requested bit */
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Pcr->IRR |= (1 << Irql);
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/* Check for pending software interrupts and compare with current IRQL */
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PendingIrql = SWInterruptLookUpTable[Pcr->IRR & 3];
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if (PendingIrql > Pcr->Irql) SWInterruptHandlerTable[PendingIrql]();
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/* Restore interrupt state */
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__writeeflags(EFlags);
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}
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/*
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* @implemented
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*/
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VOID
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FASTCALL
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HalClearSoftwareInterrupt(IN KIRQL Irql)
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{
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/* Mask out the requested bit */
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KeGetPcr()->IRR &= ~(1 << Irql);
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}
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PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY
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FASTCALL
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HalpEndSoftwareInterrupt2(IN KIRQL OldIrql,
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IN PKTRAP_FRAME TrapFrame)
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{
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ULONG PendingIrql, PendingIrqlMask, PendingIrqMask;
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PKPCR Pcr = KeGetPcr();
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PIC_MASK Mask;
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UNREFERENCED_PARAMETER(TrapFrame);
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/* Set old IRQL */
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Pcr->Irql = OldIrql;
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/* Loop checking for pending interrupts */
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while (TRUE)
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{
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/* Check for pending software interrupts and compare with current IRQL */
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PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
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if (!PendingIrqlMask) return NULL;
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/* Check for in-service delayed interrupt */
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if (Pcr->IrrActive & 0xFFFFFFF0) return NULL;
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/* Check if pending IRQL affects hardware state */
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BitScanReverse(&PendingIrql, PendingIrqlMask);
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if (PendingIrql > DISPATCH_LEVEL)
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{
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/* Set new PIC mask */
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Mask.Both = Pcr->IDR & 0xFFFF;
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__outbyte(PIC1_DATA_PORT, Mask.Master);
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__outbyte(PIC2_DATA_PORT, Mask.Slave);
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/* Set active bit otherwise, and clear it from IRR */
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PendingIrqMask = (1 << PendingIrql);
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Pcr->IrrActive |= PendingIrqMask;
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Pcr->IRR ^= PendingIrqMask;
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/* Handle delayed hardware interrupt */
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SWInterruptHandlerTable[PendingIrql]();
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/* Handling complete */
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Pcr->IrrActive ^= PendingIrqMask;
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}
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else
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{
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/* No need to loop checking for hardware interrupts */
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return SWInterruptHandlerTable2[PendingIrql];
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}
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}
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return NULL;
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}
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|
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/* EDGE INTERRUPT DISMISSAL FUNCTIONS *****************************************/
|
|
|
|
FORCEINLINE
|
|
BOOLEAN
|
|
_HalpDismissIrqGeneric(IN KIRQL Irql,
|
|
IN ULONG Irq,
|
|
OUT PKIRQL OldIrql)
|
|
{
|
|
PIC_MASK Mask;
|
|
KIRQL CurrentIrql;
|
|
I8259_OCW2 Ocw2;
|
|
PKPCR Pcr = KeGetPcr();
|
|
|
|
/* First save current IRQL and compare it to the requested one */
|
|
CurrentIrql = Pcr->Irql;
|
|
|
|
/* Check if this interrupt is really allowed to happen */
|
|
if (Irql > CurrentIrql)
|
|
{
|
|
/* Set the new IRQL and return the current one */
|
|
Pcr->Irql = Irql;
|
|
*OldIrql = CurrentIrql;
|
|
|
|
/* Prepare OCW2 for EOI */
|
|
Ocw2.Bits = 0;
|
|
Ocw2.EoiMode = SpecificEoi;
|
|
|
|
/* Check which PIC needs the EOI */
|
|
if (Irq >= 8)
|
|
{
|
|
#if defined(SARCH_PC98)
|
|
I8259_OCW3 Ocw3;
|
|
I8259_ISR Isr;
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|
|
|
/* Send the EOI for the IRQ */
|
|
__outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | ((Irq - 8) & 0xFF));
|
|
|
|
/* Request the ISR */
|
|
Ocw3.Bits = 0;
|
|
Ocw3.Sbo = 1;
|
|
Ocw3.ReadRequest = ReadIsr;
|
|
__outbyte(PIC2_CONTROL_PORT, Ocw3.Bits);
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|
|
|
/* Read the ISR */
|
|
Isr.Bits = __inbyte(PIC2_CONTROL_PORT);
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|
|
|
/* Check if the interrupt serviced was the only one from the slave PIC */
|
|
if (Isr.Bits == 0)
|
|
{
|
|
/* If ISR is empty, send the EOI for cascade IRQ on the master PIC */
|
|
__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | PIC_CASCADE_IRQ);
|
|
}
|
|
#else
|
|
/* Send the EOI for the IRQ */
|
|
__outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | ((Irq - 8) & 0xFF));
|
|
|
|
/* Send the EOI for cascade IRQ on the master PIC */
|
|
__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | PIC_CASCADE_IRQ);
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
/* Send the EOI for the IRQ */
|
|
__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | (Irq & 0xFF));
|
|
}
|
|
|
|
/* Enable interrupts and return success */
|
|
_enable();
|
|
return TRUE;
|
|
}
|
|
|
|
/* Update the IRR so that we deliver this interrupt when the IRQL is proper */
|
|
Pcr->IRR |= (1 << (Irq + 4));
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|
|
|
/* Set new PIC mask to real IRQL level, since the optimization is lost now */
|
|
Mask.Both = (KiI8259MaskTable[CurrentIrql] | Pcr->IDR) & 0xFFFF;
|
|
__outbyte(PIC1_DATA_PORT, Mask.Master);
|
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__outbyte(PIC2_DATA_PORT, Mask.Slave);
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|
|
|
/* Now lie and say this was spurious */
|
|
return FALSE;
|
|
}
|
|
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpDismissIrqGeneric(IN KIRQL Irql,
|
|
IN ULONG Irq,
|
|
OUT PKIRQL OldIrql)
|
|
{
|
|
/* Run the inline code */
|
|
return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
|
|
}
|
|
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpDismissIrq15(IN KIRQL Irql,
|
|
IN ULONG Irq,
|
|
OUT PKIRQL OldIrql)
|
|
{
|
|
I8259_OCW3 Ocw3;
|
|
I8259_OCW2 Ocw2;
|
|
I8259_ISR Isr;
|
|
|
|
/* Request the ISR */
|
|
Ocw3.Bits = 0;
|
|
Ocw3.Sbo = 1; /* This encodes an OCW3 vs. an OCW2 */
|
|
Ocw3.ReadRequest = ReadIsr;
|
|
__outbyte(PIC2_CONTROL_PORT, Ocw3.Bits);
|
|
|
|
/* Read the ISR */
|
|
Isr.Bits = __inbyte(PIC2_CONTROL_PORT);
|
|
|
|
/* Is IRQ15 really active (this is IR7) */
|
|
if (Isr.Irq7 == FALSE)
|
|
{
|
|
/* It isn't, so we have to EOI cascade IRQ */
|
|
Ocw2.Bits = 0;
|
|
Ocw2.EoiMode = SpecificEoi;
|
|
__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | PIC_CASCADE_IRQ);
|
|
|
|
/* And now fail since this was spurious */
|
|
return FALSE;
|
|
}
|
|
|
|
/* Do normal interrupt dismiss */
|
|
return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
|
|
}
|
|
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpDismissIrq13(IN KIRQL Irql,
|
|
IN ULONG Irq,
|
|
OUT PKIRQL OldIrql)
|
|
{
|
|
/* Clear the FPU busy latch */
|
|
__outbyte(0xF0, 0);
|
|
|
|
/* Do normal interrupt dismiss */
|
|
return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
|
|
}
|
|
|
|
#if defined(SARCH_PC98)
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpDismissIrq08(
|
|
_In_ KIRQL Irql,
|
|
_In_ ULONG Irq,
|
|
_Out_ PKIRQL OldIrql)
|
|
{
|
|
/* Clear the FPU busy latch */
|
|
__outbyte(CPU_IO_o_FPU_BUSY_LATCH, 0);
|
|
|
|
/* Do normal interrupt dismiss */
|
|
return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
|
|
}
|
|
#endif
|
|
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpDismissIrq07(IN KIRQL Irql,
|
|
IN ULONG Irq,
|
|
OUT PKIRQL OldIrql)
|
|
{
|
|
I8259_OCW3 Ocw3;
|
|
I8259_ISR Isr;
|
|
|
|
/* Request the ISR */
|
|
Ocw3.Bits = 0;
|
|
Ocw3.Sbo = 1;
|
|
Ocw3.ReadRequest = ReadIsr;
|
|
__outbyte(PIC1_CONTROL_PORT, Ocw3.Bits);
|
|
|
|
/* Read the ISR */
|
|
Isr.Bits = __inbyte(PIC1_CONTROL_PORT);
|
|
|
|
/* Is IRQ 7 really active? If it isn't, this is spurious so fail */
|
|
if (Isr.Irq7 == FALSE) return FALSE;
|
|
|
|
/* Do normal interrupt dismiss */
|
|
return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
|
|
}
|
|
|
|
/* LEVEL INTERRUPT DISMISSAL FUNCTIONS ****************************************/
|
|
|
|
FORCEINLINE
|
|
BOOLEAN
|
|
_HalpDismissIrqLevel(IN KIRQL Irql,
|
|
IN ULONG Irq,
|
|
OUT PKIRQL OldIrql)
|
|
{
|
|
PIC_MASK Mask;
|
|
KIRQL CurrentIrql;
|
|
I8259_OCW2 Ocw2;
|
|
PKPCR Pcr = KeGetPcr();
|
|
|
|
/* Update the PIC */
|
|
Mask.Both = (KiI8259MaskTable[Irql] | Pcr->IDR) & 0xFFFF;
|
|
__outbyte(PIC1_DATA_PORT, Mask.Master);
|
|
__outbyte(PIC2_DATA_PORT, Mask.Slave);
|
|
|
|
/* Update the IRR so that we clear this interrupt when the IRQL is proper */
|
|
Pcr->IRR |= (1 << (Irq + 4));
|
|
|
|
/* Save current IRQL */
|
|
CurrentIrql = Pcr->Irql;
|
|
|
|
/* Prepare OCW2 for EOI */
|
|
Ocw2.Bits = 0;
|
|
Ocw2.EoiMode = SpecificEoi;
|
|
|
|
/* Check which PIC needs the EOI */
|
|
if (Irq >= 8)
|
|
{
|
|
#if defined(SARCH_PC98)
|
|
I8259_OCW3 Ocw3;
|
|
I8259_ISR Isr;
|
|
|
|
/* Send the EOI for the IRQ */
|
|
__outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | ((Irq - 8) & 0xFF));
|
|
|
|
/* Request the ISR */
|
|
Ocw3.Bits = 0;
|
|
Ocw3.Sbo = 1;
|
|
Ocw3.ReadRequest = ReadIsr;
|
|
__outbyte(PIC2_CONTROL_PORT, Ocw3.Bits);
|
|
|
|
/* Read the ISR */
|
|
Isr.Bits = __inbyte(PIC2_CONTROL_PORT);
|
|
|
|
/* Check if the interrupt serviced was the only one from the slave PIC */
|
|
if (Isr.Bits == 0)
|
|
{
|
|
/* If ISR is empty, send the EOI for cascade IRQ on the master PIC */
|
|
__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | PIC_CASCADE_IRQ);
|
|
}
|
|
#else
|
|
/* Send the EOI for the IRQ */
|
|
__outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | ((Irq - 8) & 0xFF));
|
|
|
|
/* Send the EOI for cascade IRQ on the master PIC */
|
|
__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | PIC_CASCADE_IRQ);
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
/* Send the EOI for the IRQ */
|
|
__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | (Irq & 0xFF));
|
|
}
|
|
|
|
/* Check if this interrupt should be allowed to happen */
|
|
if (Irql > CurrentIrql)
|
|
{
|
|
/* Set the new IRQL and return the current one */
|
|
Pcr->Irql = Irql;
|
|
*OldIrql = CurrentIrql;
|
|
|
|
/* Enable interrupts and return success */
|
|
_enable();
|
|
return TRUE;
|
|
}
|
|
|
|
/* Now lie and say this was spurious */
|
|
return FALSE;
|
|
}
|
|
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpDismissIrqLevel(IN KIRQL Irql,
|
|
IN ULONG Irq,
|
|
OUT PKIRQL OldIrql)
|
|
{
|
|
/* Run the inline code */
|
|
return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
|
|
}
|
|
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpDismissIrq15Level(IN KIRQL Irql,
|
|
IN ULONG Irq,
|
|
OUT PKIRQL OldIrql)
|
|
{
|
|
I8259_OCW3 Ocw3;
|
|
I8259_OCW2 Ocw2;
|
|
I8259_ISR Isr;
|
|
|
|
/* Request the ISR */
|
|
Ocw3.Bits = 0;
|
|
Ocw3.Sbo = 1; /* This encodes an OCW3 vs. an OCW2 */
|
|
Ocw3.ReadRequest = ReadIsr;
|
|
__outbyte(PIC2_CONTROL_PORT, Ocw3.Bits);
|
|
|
|
/* Read the ISR */
|
|
Isr.Bits = __inbyte(PIC2_CONTROL_PORT);
|
|
|
|
/* Is IRQ15 really active (this is IR7) */
|
|
if (Isr.Irq7 == FALSE)
|
|
{
|
|
/* It isn't, so we have to EOI cascade IRQ */
|
|
Ocw2.Bits = 0;
|
|
Ocw2.EoiMode = SpecificEoi;
|
|
__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | PIC_CASCADE_IRQ);
|
|
|
|
/* And now fail since this was spurious */
|
|
return FALSE;
|
|
}
|
|
|
|
/* Do normal interrupt dismiss */
|
|
return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
|
|
}
|
|
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpDismissIrq13Level(IN KIRQL Irql,
|
|
IN ULONG Irq,
|
|
OUT PKIRQL OldIrql)
|
|
{
|
|
/* Clear the FPU busy latch */
|
|
__outbyte(0xF0, 0);
|
|
|
|
/* Do normal interrupt dismiss */
|
|
return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
|
|
}
|
|
|
|
#if defined(SARCH_PC98)
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpDismissIrq08Level(
|
|
_In_ KIRQL Irql,
|
|
_In_ ULONG Irq,
|
|
_Out_ PKIRQL OldIrql)
|
|
{
|
|
/* Clear the FPU busy latch */
|
|
__outbyte(CPU_IO_o_FPU_BUSY_LATCH, 0);
|
|
|
|
/* Do normal interrupt dismiss */
|
|
return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
|
|
}
|
|
#endif
|
|
|
|
BOOLEAN
|
|
NTAPI
|
|
HalpDismissIrq07Level(IN KIRQL Irql,
|
|
IN ULONG Irq,
|
|
OUT PKIRQL OldIrql)
|
|
{
|
|
I8259_OCW3 Ocw3;
|
|
I8259_ISR Isr;
|
|
|
|
/* Request the ISR */
|
|
Ocw3.Bits = 0;
|
|
Ocw3.Sbo = 1;
|
|
Ocw3.ReadRequest = ReadIsr;
|
|
__outbyte(PIC1_CONTROL_PORT, Ocw3.Bits);
|
|
|
|
/* Read the ISR */
|
|
Isr.Bits = __inbyte(PIC1_CONTROL_PORT);
|
|
|
|
/* Is IRQ 7 really active? If it isn't, this is spurious so fail */
|
|
if (Isr.Irq7 == FALSE) return FALSE;
|
|
|
|
/* Do normal interrupt dismiss */
|
|
return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
|
|
}
|
|
|
|
PHAL_SW_INTERRUPT_HANDLER
|
|
__cdecl
|
|
HalpHardwareInterruptLevel2(VOID)
|
|
{
|
|
PKPCR Pcr = KeGetPcr();
|
|
ULONG PendingIrqlMask, PendingIrql;
|
|
|
|
/* Check for pending software interrupts and compare with current IRQL */
|
|
PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[Pcr->Irql];
|
|
if (PendingIrqlMask)
|
|
{
|
|
/* Check for in-service delayed interrupt */
|
|
if (Pcr->IrrActive & 0xFFFFFFF0) return NULL;
|
|
|
|
/* Check if pending IRQL affects hardware state */
|
|
BitScanReverse(&PendingIrql, PendingIrqlMask);
|
|
|
|
/* Clear IRR bit */
|
|
Pcr->IRR ^= (1 << PendingIrql);
|
|
|
|
/* Now handle pending interrupt */
|
|
return SWInterruptHandlerTable[PendingIrql];
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
/* SYSTEM INTERRUPTS **********************************************************/
|
|
|
|
/*
|
|
* @implemented
|
|
*/
|
|
BOOLEAN
|
|
NTAPI
|
|
HalEnableSystemInterrupt(IN ULONG Vector,
|
|
IN KIRQL Irql,
|
|
IN KINTERRUPT_MODE InterruptMode)
|
|
{
|
|
ULONG Irq;
|
|
PKPCR Pcr = KeGetPcr();
|
|
PIC_MASK PicMask;
|
|
|
|
/* Validate the IRQ */
|
|
Irq = Vector - PRIMARY_VECTOR_BASE;
|
|
if (Irq >= CLOCK2_LEVEL) return FALSE;
|
|
|
|
/* Check for level interrupt */
|
|
if (InterruptMode == LevelSensitive)
|
|
{
|
|
/* Switch handler to level */
|
|
SWInterruptHandlerTable[Irq + 4] = HalpHardwareInterruptLevel;
|
|
|
|
/* Switch dismiss to level */
|
|
HalpSpecialDismissTable[Irq] = HalpSpecialDismissLevelTable[Irq];
|
|
}
|
|
|
|
/* Disable interrupts */
|
|
_disable();
|
|
|
|
/* Update software IDR */
|
|
Pcr->IDR &= ~(1 << Irq);
|
|
|
|
/* Set new PIC mask */
|
|
PicMask.Both = (KiI8259MaskTable[Pcr->Irql] | Pcr->IDR) & 0xFFFF;
|
|
__outbyte(PIC1_DATA_PORT, PicMask.Master);
|
|
__outbyte(PIC2_DATA_PORT, PicMask.Slave);
|
|
|
|
/* Enable interrupts and exit */
|
|
_enable();
|
|
return TRUE;
|
|
}
|
|
|
|
/*
|
|
* @implemented
|
|
*/
|
|
VOID
|
|
NTAPI
|
|
HalDisableSystemInterrupt(IN ULONG Vector,
|
|
IN KIRQL Irql)
|
|
{
|
|
ULONG IrqMask;
|
|
PIC_MASK PicMask;
|
|
|
|
/* Compute new combined IRQ mask */
|
|
IrqMask = 1 << (Vector - PRIMARY_VECTOR_BASE);
|
|
|
|
/* Disable interrupts */
|
|
_disable();
|
|
|
|
/* Update software IDR */
|
|
KeGetPcr()->IDR |= IrqMask;
|
|
|
|
/* Read current interrupt mask */
|
|
PicMask.Master = __inbyte(PIC1_DATA_PORT);
|
|
PicMask.Slave = __inbyte(PIC2_DATA_PORT);
|
|
|
|
/* Add the new disabled interrupt */
|
|
PicMask.Both |= IrqMask;
|
|
|
|
/* Write new interrupt mask */
|
|
__outbyte(PIC1_DATA_PORT, PicMask.Master);
|
|
__outbyte(PIC2_DATA_PORT, PicMask.Slave);
|
|
|
|
/* Bring interrupts back */
|
|
_enable();
|
|
}
|
|
|
|
/*
|
|
* @implemented
|
|
*/
|
|
BOOLEAN
|
|
NTAPI
|
|
HalBeginSystemInterrupt(IN KIRQL Irql,
|
|
IN ULONG Vector,
|
|
OUT PKIRQL OldIrql)
|
|
{
|
|
ULONG Irq;
|
|
|
|
/* Get the IRQ and call the proper routine to handle it */
|
|
Irq = Vector - PRIMARY_VECTOR_BASE;
|
|
return HalpSpecialDismissTable[Irq](Irql, Irq, OldIrql);
|
|
}
|
|
|
|
/*
|
|
* @implemented
|
|
*/
|
|
PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY
|
|
FASTCALL
|
|
HalEndSystemInterrupt2(IN KIRQL OldIrql,
|
|
IN PKTRAP_FRAME TrapFrame)
|
|
{
|
|
ULONG PendingIrql, PendingIrqlMask, PendingIrqMask;
|
|
PKPCR Pcr = KeGetPcr();
|
|
PIC_MASK Mask;
|
|
|
|
/* Set old IRQL */
|
|
Pcr->Irql = OldIrql;
|
|
|
|
/* Check for pending software interrupts and compare with current IRQL */
|
|
PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
|
|
if (PendingIrqlMask)
|
|
{
|
|
/* Check for in-service delayed interrupt */
|
|
if (Pcr->IrrActive & 0xFFFFFFF0) return NULL;
|
|
|
|
/* Loop checking for pending interrupts */
|
|
while (TRUE)
|
|
{
|
|
/* Check if pending IRQL affects hardware state */
|
|
BitScanReverse(&PendingIrql, PendingIrqlMask);
|
|
if (PendingIrql > DISPATCH_LEVEL)
|
|
{
|
|
/* Set new PIC mask */
|
|
Mask.Both = Pcr->IDR & 0xFFFF;
|
|
__outbyte(PIC1_DATA_PORT, Mask.Master);
|
|
__outbyte(PIC2_DATA_PORT, Mask.Slave);
|
|
|
|
/* Now check if this specific interrupt is already in-service */
|
|
PendingIrqMask = (1 << PendingIrql);
|
|
if (Pcr->IrrActive & PendingIrqMask) return NULL;
|
|
|
|
/* Set active bit otherwise, and clear it from IRR */
|
|
Pcr->IrrActive |= PendingIrqMask;
|
|
Pcr->IRR ^= PendingIrqMask;
|
|
|
|
/* Handle delayed hardware interrupt */
|
|
SWInterruptHandlerTable[PendingIrql]();
|
|
|
|
/* Handling complete */
|
|
Pcr->IrrActive ^= PendingIrqMask;
|
|
|
|
/* Check if there's still interrupts pending */
|
|
PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[Pcr->Irql];
|
|
if (!PendingIrqlMask) break;
|
|
}
|
|
else
|
|
{
|
|
/* Now handle pending software interrupt */
|
|
return SWInterruptHandlerTable2[PendingIrql];
|
|
}
|
|
}
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
/* SOFTWARE INTERRUPT TRAPS ***************************************************/
|
|
|
|
FORCEINLINE
|
|
DECLSPEC_NORETURN
|
|
VOID
|
|
_HalpApcInterruptHandler(IN PKTRAP_FRAME TrapFrame)
|
|
{
|
|
KIRQL CurrentIrql;
|
|
PKPCR Pcr = KeGetPcr();
|
|
|
|
/* Save the current IRQL and update it */
|
|
CurrentIrql = Pcr->Irql;
|
|
Pcr->Irql = APC_LEVEL;
|
|
|
|
/* Remove DPC from IRR */
|
|
Pcr->IRR &= ~(1 << APC_LEVEL);
|
|
|
|
/* Enable interrupts and call the kernel's APC interrupt handler */
|
|
_enable();
|
|
KiDeliverApc(((KiUserTrap(TrapFrame)) || (TrapFrame->EFlags & EFLAGS_V86_MASK)) ?
|
|
UserMode : KernelMode,
|
|
NULL,
|
|
TrapFrame);
|
|
|
|
/* Disable interrupts and end the interrupt */
|
|
_disable();
|
|
HalpEndSoftwareInterrupt(CurrentIrql, TrapFrame);
|
|
|
|
/* Exit the interrupt */
|
|
KiEoiHelper(TrapFrame);
|
|
}
|
|
|
|
DECLSPEC_NORETURN
|
|
VOID
|
|
FASTCALL
|
|
HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame)
|
|
{
|
|
/* Do the work */
|
|
_HalpApcInterruptHandler(TrapFrame);
|
|
}
|
|
|
|
DECLSPEC_NORETURN
|
|
VOID
|
|
FASTCALL
|
|
HalpApcInterruptHandler(IN PKTRAP_FRAME TrapFrame)
|
|
{
|
|
/* Set up a fake INT Stack */
|
|
TrapFrame->EFlags = __readeflags();
|
|
TrapFrame->SegCs = KGDT_R0_CODE;
|
|
TrapFrame->Eip = TrapFrame->Eax;
|
|
|
|
/* Build the trap frame */
|
|
KiEnterInterruptTrap(TrapFrame);
|
|
|
|
/* Do the work */
|
|
_HalpApcInterruptHandler(TrapFrame);
|
|
}
|
|
|
|
FORCEINLINE
|
|
KIRQL
|
|
_HalpDispatchInterruptHandler(VOID)
|
|
{
|
|
KIRQL CurrentIrql;
|
|
PKPCR Pcr = KeGetPcr();
|
|
|
|
/* Save the current IRQL and update it */
|
|
CurrentIrql = Pcr->Irql;
|
|
Pcr->Irql = DISPATCH_LEVEL;
|
|
|
|
/* Remove DPC from IRR */
|
|
Pcr->IRR &= ~(1 << DISPATCH_LEVEL);
|
|
|
|
/* Enable interrupts and call the kernel's DPC interrupt handler */
|
|
_enable();
|
|
KiDispatchInterrupt();
|
|
_disable();
|
|
|
|
/* Return IRQL */
|
|
return CurrentIrql;
|
|
}
|
|
|
|
DECLSPEC_NORETURN
|
|
VOID
|
|
FASTCALL
|
|
HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame)
|
|
{
|
|
KIRQL CurrentIrql;
|
|
|
|
/* Do the work */
|
|
CurrentIrql = _HalpDispatchInterruptHandler();
|
|
|
|
/* End the interrupt */
|
|
HalpEndSoftwareInterrupt(CurrentIrql, TrapFrame);
|
|
|
|
/* Exit the interrupt */
|
|
KiEoiHelper(TrapFrame);
|
|
}
|
|
|
|
PHAL_SW_INTERRUPT_HANDLER
|
|
__cdecl
|
|
HalpDispatchInterrupt2(VOID)
|
|
{
|
|
ULONG PendingIrqlMask, PendingIrql;
|
|
KIRQL OldIrql;
|
|
PIC_MASK Mask;
|
|
PKPCR Pcr = KeGetPcr();
|
|
|
|
/* Do the work */
|
|
OldIrql = _HalpDispatchInterruptHandler();
|
|
|
|
/* Restore IRQL */
|
|
Pcr->Irql = OldIrql;
|
|
|
|
/* Check for pending software interrupts and compare with current IRQL */
|
|
PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
|
|
if (PendingIrqlMask)
|
|
{
|
|
/* Check if pending IRQL affects hardware state */
|
|
BitScanReverse(&PendingIrql, PendingIrqlMask);
|
|
if (PendingIrql > DISPATCH_LEVEL)
|
|
{
|
|
/* Set new PIC mask */
|
|
Mask.Both = Pcr->IDR & 0xFFFF;
|
|
__outbyte(PIC1_DATA_PORT, Mask.Master);
|
|
__outbyte(PIC2_DATA_PORT, Mask.Slave);
|
|
|
|
/* Clear IRR bit */
|
|
Pcr->IRR ^= (1 << PendingIrql);
|
|
}
|
|
|
|
/* Now handle pending interrupt */
|
|
return SWInterruptHandlerTable[PendingIrql];
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
ULONG
|
|
NTAPI
|
|
HalpGetRootInterruptVector(IN ULONG BusInterruptLevel,
|
|
IN ULONG BusInterruptVector,
|
|
OUT PKIRQL Irql,
|
|
OUT PKAFFINITY Affinity)
|
|
{
|
|
UCHAR SystemVector;
|
|
|
|
/* Validate the IRQ */
|
|
if (BusInterruptLevel > 23)
|
|
{
|
|
/* Invalid vector */
|
|
DPRINT1("IRQ %lx is too high!\n", BusInterruptLevel);
|
|
return 0;
|
|
}
|
|
|
|
/* Get the system vector */
|
|
SystemVector = HalpIrqToVector((UCHAR)BusInterruptLevel);
|
|
|
|
/* Return the IRQL and affinity */
|
|
*Irql = HalpVectorToIrql(SystemVector);
|
|
*Affinity = HalpDefaultInterruptAffinity;
|
|
ASSERT(HalpDefaultInterruptAffinity);
|
|
|
|
/* Return the vector */
|
|
return SystemVector;
|
|
}
|
|
|
|
#else /* _MINIHAL_ */
|
|
|
|
KIRQL
|
|
NTAPI
|
|
KeGetCurrentIrql(VOID)
|
|
{
|
|
return PASSIVE_LEVEL;
|
|
}
|
|
|
|
VOID
|
|
FASTCALL
|
|
KfLowerIrql(
|
|
IN KIRQL OldIrql)
|
|
{
|
|
}
|
|
|
|
KIRQL
|
|
FASTCALL
|
|
KfRaiseIrql(
|
|
IN KIRQL NewIrql)
|
|
{
|
|
return NewIrql;
|
|
}
|
|
|
|
#endif /* !_MINIHAL_ */
|