mirror of
https://github.com/reactos/reactos.git
synced 2024-11-09 08:08:38 +00:00
411 lines
8.1 KiB
C
411 lines
8.1 KiB
C
#include "ppcmmu/mmu.h"
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#include "ppcmmu/mmuutil.h"
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inline int GetMSR() {
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register int res asm ("r3");
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__asm__("mfmsr 3");
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return res;
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}
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inline int GetDEC() {
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register int res asm ("r3");
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__asm__("mfdec 3");
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return res;
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}
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__asm__("\t.globl GetPhys\n"
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"GetPhys:\t\n"
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"mflr 0\n\t"
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"stwu 0,-16(1)\n\t"
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"mfmsr 5\n\t"
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"andi. 6,5,0xffef\n\t"/* turn off MSR[DR] */
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"mtmsr 6\n\t"
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"isync\n\t"
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"sync\n\t"
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"lwz 3,0(3)\n\t" /* Get actual value at phys addr r3 */
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"mtmsr 5\n\t"
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"isync\n\t"
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"sync\n\t"
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"lwz 0,0(1)\n\t"
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"addi 1,1,16\n\t"
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"mtlr 0\n\t"
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"blr"
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);
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__asm__("\t.globl GetPhysHalf\n"
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"GetPhysHalf:\t\n"
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"mflr 0\n\t"
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"stwu 0,-16(1)\n\t"
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"mfmsr 5\n\t"
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"andi. 6,5,0xffef\n\t"/* turn off MSR[DR] */
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"mtmsr 6\n\t"
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"isync\n\t"
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"sync\n\t"
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"lhz 3,0(3)\n\t" /* Get actual value at phys addr r3 */
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"mtmsr 5\n\t"
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"isync\n\t"
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"sync\n\t"
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"lwz 0,0(1)\n\t"
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"addi 1,1,16\n\t"
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"mtlr 0\n\t"
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"blr"
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);
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__asm__("\t.globl GetPhysByte\n"
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"GetPhysByte:\t\n"
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"mflr 0\n\t"
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"stwu 0,-16(1)\n\t"
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"mfmsr 5\n\t"
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"andi. 6,5,0xffef\n\t"/* turn off MSR[DR] */
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"mtmsr 6\n\t"
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"isync\n\t"
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"sync\n\t"
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"lbz 3,0(3)\n\t" /* Get actual value at phys addr r3 */
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"mtmsr 5\n\t"
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"isync\n\t"
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"sync\n\t"
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"lwz 0,0(1)\n\t"
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"addi 1,1,16\n\t"
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"mtlr 0\n\t"
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"blr"
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);
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__asm__("\t.globl SetPhys\n"
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"SetPhys:\t\n"
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"mflr 0\n\t"
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"stwu 0,-16(1)\n\t"
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"mfmsr 5\n\t"
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"andi. 6,5,0xffef\n\t"/* turn off MSR[DR] */
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"mtmsr 6\n\t"
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"sync\n\t"
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"eieio\n\t"
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"stw 4,0(3)\n\t" /* Set actual value at phys addr r3 */
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"dcbst 0,3\n\t"
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"mtmsr 5\n\t"
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"sync\n\t"
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"eieio\n\t"
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"mr 3,4\n\t"
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"lwz 0,0(1)\n\t"
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"addi 1,1,16\n\t"
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"mtlr 0\n\t"
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"blr"
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);
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__asm__("\t.globl SetPhysHalf\n"
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"SetPhysHalf:\t\n"
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"mflr 0\n\t"
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"stwu 0,-16(1)\n\t"
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"mfmsr 5\n\t"
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"andi. 6,5,0xffef\n\t"/* turn off MSR[DR] */
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"mtmsr 6\n\t"
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"sync\n\t"
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"eieio\n\t"
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"sth 4,0(3)\n\t" /* Set actual value at phys addr r3 */
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"dcbst 0,3\n\t"
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"mtmsr 5\n\t"
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"sync\n\t"
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"eieio\n\t"
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"mr 3,4\n\t"
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"lwz 0,0(1)\n\t"
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"addi 1,1,16\n\t"
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"mtlr 0\n\t"
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"blr"
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);
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__asm__("\t.globl SetPhysByte\n"
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"SetPhysByte:\t\n"
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"mflr 0\n\t"
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"stwu 0,-16(1)\n\t"
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"mfmsr 5\n\t"
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"andi. 6,5,0xffef\n\t"/* turn off MSR[DR] */
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"mtmsr 6\n\t"
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"sync\n\t"
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"eieio\n\t"
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"stb 4,0(3)\n\t" /* Set actual value at phys addr r3 */
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"dcbst 0,3\n\t"
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"mtmsr 5\n\t"
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"sync\n\t"
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"eieio\n\t"
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"mr 3,4\n\t"
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"lwz 0,0(1)\n\t"
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"addi 1,1,16\n\t"
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"mtlr 0\n\t"
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"blr"
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);
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inline int GetSR(int n) {
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register int res = 0;
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switch( n ) {
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case 0:
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__asm__("mfsr %0,0" : "=r" (res));
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break;
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case 1:
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__asm__("mfsr %0,1" : "=r" (res));
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break;
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case 2:
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__asm__("mfsr %0,2" : "=r" (res));
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break;
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case 3:
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__asm__("mfsr %0,3" : "=r" (res));
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break;
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case 4:
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__asm__("mfsr %0,4" : "=r" (res));
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break;
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case 5:
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__asm__("mfsr %0,5" : "=r" (res));
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break;
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case 6:
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__asm__("mfsr %0,6" : "=r" (res));
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break;
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case 7:
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__asm__("mfsr %0,7" : "=r" (res));
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break;
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case 8:
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__asm__("mfsr %0,8" : "=r" (res));
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break;
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case 9:
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__asm__("mfsr %0,9" : "=r" (res));
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break;
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case 10:
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__asm__("mfsr %0,10" : "=r" (res));
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break;
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case 11:
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__asm__("mfsr %0,11" : "=r" (res));
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break;
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case 12:
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__asm__("mfsr %0,12" : "=r" (res));
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break;
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case 13:
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__asm__("mfsr %0,13" : "=r" (res));
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break;
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case 14:
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__asm__("mfsr %0,14" : "=r" (res));
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break;
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case 15:
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__asm__("mfsr %0,15" : "=r" (res));
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break;
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}
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return res;
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}
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inline void SetSR(int n, int val) {
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switch( n ) {
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case 0:
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__asm__("mtsr 0,%0" : : "r" (val));
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break;
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case 1:
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__asm__("mtsr 1,%0" : : "r" (val));
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break;
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case 2:
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__asm__("mtsr 2,%0" : : "r" (val));
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break;
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case 3:
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__asm__("mtsr 3,%0" : : "r" (val));
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break;
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case 4:
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__asm__("mtsr 4,%0" : : "r" (val));
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break;
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case 5:
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__asm__("mtsr 5,%0" : : "r" (val));
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break;
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case 6:
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__asm__("mtsr 6,%0" : : "r" (val));
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break;
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case 7:
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__asm__("mtsr 7,%0" : : "r" (val));
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break;
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case 8:
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__asm__("mtsr 8,%0" : : "r" (val));
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break;
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case 9:
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__asm__("mtsr 9,%0" : : "r" (val));
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break;
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case 10:
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__asm__("mtsr 10,%0" : : "r" (val));
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break;
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case 11:
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__asm__("mtsr 11,%0" : : "r" (val));
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break;
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case 12:
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__asm__("mtsr 12,%0" : : "r" (val));
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break;
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case 13:
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__asm__("mtsr 13,%0" : : "r" (val));
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break;
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case 14:
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__asm__("mtsr 14,%0" : : "r" (val));
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break;
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case 15:
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__asm__("mtsr 15,%0" : : "r" (val));
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break;
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}
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}
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void GetBat( int bat, int inst, int *batHi, int *batLo ) {
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register int bh asm("r3"), bl asm("r4");
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if( inst ) {
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switch( bat ) {
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case 0:
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__asm__("mfibatu 3,0");
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__asm__("mfibatl 4,0");
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break;
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case 1:
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__asm__("mfibatu 3,1");
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__asm__("mfibatl 4,1");
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break;
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case 2:
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__asm__("mfibatu 3,2");
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__asm__("mfibatl 4,2");
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break;
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case 3:
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__asm__("mfibatu 3,3");
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__asm__("mfibatl 4,3");
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break;
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}
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} else {
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switch( bat ) {
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case 0:
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__asm__("mfdbatu 3,0");
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__asm__("mfdbatl 4,0");
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break;
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case 1:
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__asm__("mfdbatu 3,1");
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__asm__("mfdbatl 4,1");
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break;
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case 2:
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__asm__("mfdbatu 3,2");
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__asm__("mfdbatl 4,2");
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break;
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case 3:
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__asm__("mfdbatu 3,3");
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__asm__("mfdbatl 4,3");
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break;
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}
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}
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*batHi = bh;
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*batLo = bl;
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}
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#define BATSET(n,t) \
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case n: __asm__("mt" #t "batu " #n ",%0\n\tmt" #t "batl " #n ",%1" \
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: : "r" (batHi), "r" (batLo)); break;
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void SetBat( int bat, int inst, int batHi, int batLo ) {
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if( inst ) {
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switch( bat ) {
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BATSET(0,i);
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BATSET(1,i);
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BATSET(2,i);
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BATSET(3,i);
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}
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} else {
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switch( bat ) {
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BATSET(0,d);
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BATSET(1,d);
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BATSET(2,d);
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BATSET(3,d);
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}
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}
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__asm__("isync\n\tsync");
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}
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inline int GetSDR1() {
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register int res asm("r3");
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__asm__("mfsdr1 3");
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return res;
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}
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inline void SetSDR1( int sdr ) {
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int i,j;
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__asm__("mtsdr1 3");
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__asm__("sync");
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__asm__("isync");
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for( i = 0; i < 256; i++ ) {
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j = i << 12;
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__asm__("tlbie %0,0" : : "r" (j));
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}
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__asm__("eieio");
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__asm__("tlbsync");
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__asm__("ptesync");
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}
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inline int BatTranslate( int batu, int batl, int virt ) {
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int mask;
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if(batu & 0x3fc)
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{
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mask = ~(0x1ffff | ((batu & 0x3fc)>>2)<<17);
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if((batu & 2) && ((batu & mask) == (virt & mask)))
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return (batl & mask) | (virt & ~mask);
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} else {
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mask = ~(0x1ffff | (batl << 17));
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if(!(batl & 0x40) || ((batu & mask) != (virt & mask)))
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return (batl & mask) | (virt & ~mask);
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}
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return -1;
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}
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inline int BatHit( int batu, int batl, int virt ) {
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return BatTranslate( batu, batl, virt ) != -1;
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}
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/* translate address */
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int PpcVirt2phys( vaddr_t virt, int inst ) {
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int msr = GetMSR();
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int txmask = inst ? 0x20 : 0x10;
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int i, bath, batl, sr, sdr1, physbase, vahi, valo;
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int npteg, hash, hashmask, ptehi, ptelo, ptegaddr;
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int vsid, pteh, ptevsid, pteapi;
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if( msr & txmask ) {
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sr = GetSR( virt >> 28 );
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vsid = sr & 0xfffffff;
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vahi = vsid >> 4;
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valo = (vsid << 28) | (virt & 0xfffffff);
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if( sr & 0x80000000 ) {
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return valo;
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}
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for( i = 0; i < 4; i++ ) {
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GetBat( i, inst, &bath, &batl );
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if( BatHit( bath, batl, virt ) ) {
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return BatTranslate( bath, batl, virt );
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}
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}
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sdr1 = GetSDR1();
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physbase = sdr1 & ~0xffff;
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hashmask = ((sdr1 & 0x1ff) << 10) | 0x3ff;
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hash = (vsid & 0x7ffff) ^ ((valo >> 12) & 0xffff);
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npteg = hashmask + 1;
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for( pteh = 0; pteh < 0x80; pteh += 64, hash ^= 0x7ffff ) {
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ptegaddr = ((hashmask & hash) * 64) + physbase;
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for( i = 0; i < 8; i++ ) {
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ptehi = GetPhys( ptegaddr + (i * 8) );
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ptelo = GetPhys( ptegaddr + (i * 8) + 4 );
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ptevsid = (ptehi >> 7) & 0xffffff;
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pteapi = ptehi & 0x3f;
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if( (ptehi & 64) != pteh ) continue;
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if( ptevsid != (vsid & 0xffffff) ) continue;
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if( pteapi != ((virt >> 22) & 0x3f) ) continue;
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return (ptelo & 0xfffff000) | (virt & 0xfff);
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}
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}
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return -1;
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} else {
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return virt;
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}
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}
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int PtegNumber(vaddr_t virt, int hfun)
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{
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int sr = GetSR( (virt >> 28) & 0xf );
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int vsid = sr & PPC_VSID_MASK;
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return ((((vsid & 0x7ffff) ^ ((virt >> 12) & 0xffff)) ^ (hfun ? -1 : 0)) & ((HTABSIZ - 1) >> 3) & 0x3ff);
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}
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