mirror of
https://github.com/reactos/reactos.git
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165 lines
5.1 KiB
C
165 lines
5.1 KiB
C
/*
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* PROJECT: ReactOS HAL
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* LICENSE: GPL - See COPYING in the top level directory
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* FILE: hal/halx86/legacy/bus/sysbus.c
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* PURPOSE:
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* PROGRAMMERS: Stefan Ginsberg (stefan.ginsberg@reactos.org)
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*/
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/* INCLUDES *******************************************************************/
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#include <hal.h>
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#define NDEBUG
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#include <debug.h>
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/* GLOBALS ********************************************************************/
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/* PRIVATE FUNCTIONS **********************************************************/
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BOOLEAN
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NTAPI
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HalpTranslateSystemBusAddress(IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PHYSICAL_ADDRESS BusAddress,
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IN OUT PULONG AddressSpace,
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OUT PPHYSICAL_ADDRESS TranslatedAddress)
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{
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PSUPPORTED_RANGE Range = NULL;
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/* Check what kind of address space this is */
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switch (*AddressSpace)
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{
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/* Memory address */
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case 0:
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/* Loop all prefetch memory */
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for (Range = &BusHandler->BusAddresses->PrefetchMemory;
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Range;
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Range = Range->Next)
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{
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/* Check if it's in a valid range */
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if ((BusAddress.QuadPart >= Range->Base) &&
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(BusAddress.QuadPart <= Range->Limit))
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{
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/* Get out */
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break;
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}
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}
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/* Check if we haven't found anything yet */
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if (!Range)
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{
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/* Loop all bus memory */
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for (Range = &BusHandler->BusAddresses->Memory;
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Range;
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Range = Range->Next)
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{
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/* Check if it's in a valid range */
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if ((BusAddress.QuadPart >= Range->Base) &&
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(BusAddress.QuadPart <= Range->Limit))
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{
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/* Get out */
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break;
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}
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}
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}
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/* Done */
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break;
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/* I/O Space */
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case 1:
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/* Loop all bus I/O memory */
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for (Range = &BusHandler->BusAddresses->IO;
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Range;
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Range = Range->Next)
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{
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/* Check if it's in a valid range */
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if ((BusAddress.QuadPart >= Range->Base) &&
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(BusAddress.QuadPart <= Range->Limit))
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{
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/* Get out */
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break;
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}
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}
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/* Done */
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break;
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}
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/* Check if we found a range */
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if (Range)
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{
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/* Do the translation and return the kind of address space this is */
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TranslatedAddress->QuadPart = BusAddress.QuadPart + Range->SystemBase;
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if ((TranslatedAddress->QuadPart != BusAddress.QuadPart) ||
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(*AddressSpace != Range->SystemAddressSpace))
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{
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/* Different than what the old HAL would do */
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DPRINT1("Translation of %I64x is %I64x %s\n",
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BusAddress.QuadPart, TranslatedAddress->QuadPart,
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Range->SystemAddressSpace ? "In I/O Space" : "In RAM");
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}
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*AddressSpace = Range->SystemAddressSpace;
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return TRUE;
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}
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/* Nothing found */
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DPRINT1("Translation of %I64x failed!\n", BusAddress.QuadPart);
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return FALSE;
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}
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ULONG
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NTAPI
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HalpGetRootInterruptVector(IN ULONG BusInterruptLevel,
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IN ULONG BusInterruptVector,
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OUT PKIRQL Irql,
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OUT PKAFFINITY Affinity)
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{
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UCHAR SystemVector;
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/* Validate the IRQ */
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if (BusInterruptLevel > 23)
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{
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/* Invalid vector */
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DPRINT1("IRQ %lx is too high!\n", BusInterruptLevel);
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return 0;
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}
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/* Get the system vector */
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SystemVector = HalpIrqToVector((UCHAR)BusInterruptLevel);
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/* Return the IRQL and affinity */
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*Irql = HalpVectorToIrql(SystemVector);
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*Affinity = HalpDefaultInterruptAffinity;
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ASSERT(HalpDefaultInterruptAffinity);
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/* Return the vector */
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return SystemVector;
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}
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ULONG
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NTAPI
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HalpGetSystemInterruptVector(IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN ULONG BusInterruptLevel,
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IN ULONG BusInterruptVector,
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OUT PKIRQL Irql,
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OUT PKAFFINITY Affinity)
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{
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ULONG Vector;
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/* Get the root vector */
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Vector = HalpGetRootInterruptVector(BusInterruptLevel,
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BusInterruptVector,
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Irql,
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Affinity);
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/* Check if the vector is owned by the HAL and fail if it is */
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if (HalpIDTUsageFlags[Vector].Flags & IDT_REGISTERED) DPRINT1("Vector %lx is ALREADY IN USE!\n", Vector);
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return (HalpIDTUsageFlags[Vector].Flags & IDT_REGISTERED) ? 0 : Vector;
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}
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/* EOF */
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