mirror of
https://github.com/reactos/reactos.git
synced 2024-07-08 05:35:06 +00:00
698 lines
22 KiB
C
698 lines
22 KiB
C
/*
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* COPYRIGHT: GPL - See COPYING in the top level directory
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* PROJECT: ReactOS Virtual DOS Machine
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* FILE: subsystems/mvdm/ntvdm/hardware/dma.c
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* PURPOSE: ISA DMA - Direct Memory Access Controller emulation -
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* i8237A compatible with 74LS612 Memory Mapper extension
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* PROGRAMMERS: Hermes Belusca-Maito (hermes.belusca@sfr.fr)
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*/
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/* INCLUDES *******************************************************************/
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#include "ntvdm.h"
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#define NDEBUG
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#include <debug.h>
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#include "emulator.h"
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#include "dma.h"
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#include "io.h"
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#include "memory.h"
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/* PRIVATE VARIABLES **********************************************************/
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/*
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* DMA Controller 0 (Channels 0..3): Slave controller
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* DMA Controller 1 (Channels 4..7): Master controller
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*/
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static DMA_CONTROLLER DmaControllers[DMA_CONTROLLERS];
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/* External page registers for each channel of the two DMA controllers */
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static DMA_PAGE_REGISTER DmaPageRegisters[DMA_CONTROLLERS * DMA_CONTROLLER_CHANNELS];
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/* PRIVATE FUNCTIONS **********************************************************/
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#define READ_ADDR(CtrlIndex, ChanIndex, Data) \
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do { \
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(Data) = \
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*((PBYTE)&DmaControllers[(CtrlIndex)].DmaChannel[(ChanIndex)].CurrAddress + \
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(DmaControllers[(CtrlIndex)].FlipFlop & 0x01)); \
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DmaControllers[(CtrlIndex)].FlipFlop ^= 1; \
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} while(0)
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#define READ_CNT(CtrlIndex, ChanIndex, Data) \
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do { \
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(Data) = \
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*((PBYTE)&DmaControllers[(CtrlIndex)].DmaChannel[(ChanIndex)].CurrElemCnt + \
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(DmaControllers[(CtrlIndex)].FlipFlop & 0x01)); \
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DmaControllers[(CtrlIndex)].FlipFlop ^= 1; \
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} while(0)
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static BYTE WINAPI DmaReadPort(USHORT Port)
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{
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BYTE ReadValue = 0xFF;
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DPRINT1("DmaReadPort(Port = 0x%04X)\n", Port);
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switch (Port)
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{
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/* Current Address Registers */
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{
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case 0x00:
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READ_ADDR(0, 0, ReadValue);
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return ReadValue;
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case 0x02:
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READ_ADDR(0, 1, ReadValue);
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return ReadValue;
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case 0x04:
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READ_ADDR(0, 2, ReadValue);
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return ReadValue;
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case 0x06:
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READ_ADDR(0, 3, ReadValue);
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return ReadValue;
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case 0xC0:
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READ_ADDR(1, 0, ReadValue);
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return ReadValue;
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case 0xC4:
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READ_ADDR(1, 1, ReadValue);
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return ReadValue;
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case 0xC8:
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READ_ADDR(1, 2, ReadValue);
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return ReadValue;
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case 0xCC:
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READ_ADDR(1, 3, ReadValue);
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return ReadValue;
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}
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/* Current Count Registers */
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{
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case 0x01:
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READ_CNT(0, 0, ReadValue);
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return ReadValue;
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case 0x03:
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READ_CNT(0, 1, ReadValue);
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return ReadValue;
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case 0x05:
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READ_CNT(0, 2, ReadValue);
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return ReadValue;
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case 0x07:
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READ_CNT(0, 3, ReadValue);
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return ReadValue;
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case 0xC2:
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READ_CNT(1, 0, ReadValue);
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return ReadValue;
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case 0xC6:
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READ_CNT(1, 1, ReadValue);
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return ReadValue;
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case 0xCA:
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READ_CNT(1, 2, ReadValue);
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return ReadValue;
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case 0xCE:
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READ_CNT(1, 3, ReadValue);
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return ReadValue;
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}
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/* Status Registers */
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{
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case 0x08:
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return DmaControllers[0].Status;
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case 0xD0:
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return DmaControllers[1].Status;
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}
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/* DMA Intermediate (Temporary) Registers */
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{
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case 0x0D:
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return DmaControllers[0].TempReg;
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case 0xDA:
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return DmaControllers[1].TempReg;
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}
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/* Multi-Channel Mask Registers */
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{
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case 0x0F:
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return DmaControllers[0].Mask;
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case 0xDE:
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return DmaControllers[1].Mask;
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}
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}
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return 0x00;
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}
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#define WRITE_ADDR(CtrlIndex, ChanIndex, Data) \
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do { \
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*((PBYTE)&DmaControllers[(CtrlIndex)].DmaChannel[(ChanIndex)].BaseAddress + \
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(DmaControllers[(CtrlIndex)].FlipFlop & 0x01)) = (Data); \
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*((PBYTE)&DmaControllers[(CtrlIndex)].DmaChannel[(ChanIndex)].CurrAddress + \
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(DmaControllers[(CtrlIndex)].FlipFlop & 0x01)) = (Data); \
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DmaControllers[(CtrlIndex)].FlipFlop ^= 1; \
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} while(0)
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#define WRITE_CNT(CtrlIndex, ChanIndex, Data) \
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do { \
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*((PBYTE)&DmaControllers[(CtrlIndex)].DmaChannel[(ChanIndex)].BaseElemCnt + \
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(DmaControllers[(CtrlIndex)].FlipFlop & 0x01)) = (Data); \
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*((PBYTE)&DmaControllers[(CtrlIndex)].DmaChannel[(ChanIndex)].CurrElemCnt + \
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(DmaControllers[(CtrlIndex)].FlipFlop & 0x01)) = (Data); \
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DmaControllers[(CtrlIndex)].FlipFlop ^= 1; \
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} while(0)
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static VOID WINAPI DmaWritePort(USHORT Port, BYTE Data)
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{
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DPRINT1("DmaWritePort(Port = 0x%04X, Data = 0x%02X)\n", Port, Data);
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switch (Port)
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{
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/* Start Address Registers */
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{
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case 0x00:
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WRITE_ADDR(0, 0, Data);
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break;
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case 0x02:
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WRITE_ADDR(0, 1, Data);
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break;
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case 0x04:
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WRITE_ADDR(0, 2, Data);
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break;
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case 0x06:
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WRITE_ADDR(0, 3, Data);
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break;
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case 0xC0:
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WRITE_ADDR(1, 0, Data);
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break;
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case 0xC4:
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WRITE_ADDR(1, 1, Data);
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break;
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case 0xC8:
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WRITE_ADDR(1, 2, Data);
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break;
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case 0xCC:
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WRITE_ADDR(1, 3, Data);
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break;
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}
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/* Base Count Registers */
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{
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case 0x01:
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WRITE_CNT(0, 0, Data);
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break;
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case 0x03:
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WRITE_CNT(0, 1, Data);
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break;
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case 0x05:
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WRITE_CNT(0, 2, Data);
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break;
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case 0x07:
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WRITE_CNT(0, 3, Data);
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break;
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case 0xC2:
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WRITE_CNT(1, 0, Data);
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break;
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case 0xC6:
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WRITE_CNT(1, 1, Data);
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break;
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case 0xCA:
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WRITE_CNT(1, 2, Data);
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break;
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case 0xCE:
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WRITE_CNT(1, 3, Data);
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break;
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}
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/* Command Registers */
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{
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case 0x08:
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DmaControllers[0].Command = Data;
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break;
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case 0xD0:
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DmaControllers[1].Command = Data;
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break;
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}
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/* Mode Registers */
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{
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case 0x0B:
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DmaControllers[0].DmaChannel[Data & 0x03].Mode = (Data & ~0x03);
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break;
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case 0xD6:
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DmaControllers[1].DmaChannel[Data & 0x03].Mode = (Data & ~0x03);
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break;
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}
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/* Request Registers */
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{
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case 0x09:
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DmaControllers[0].Request = Data;
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break;
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case 0xD2:
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DmaControllers[1].Request = Data;
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break;
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}
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/* Single Channel Mask Registers */
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{
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case 0x0A:
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if (Data & 0x04)
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DmaControllers[0].Mask |= (1 << (Data & 0x03));
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else
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DmaControllers[0].Mask &= ~(1 << (Data & 0x03));
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break;
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case 0xD4:
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if (Data & 0x04)
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DmaControllers[1].Mask |= (1 << (Data & 0x03));
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else
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DmaControllers[1].Mask &= ~(1 << (Data & 0x03));
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break;
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}
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/* Multi-Channel Mask Registers */
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{
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case 0x0F:
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DmaControllers[0].Mask = (Data & 0x0F);
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break;
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case 0xDE:
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DmaControllers[1].Mask = (Data & 0x0F);
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break;
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}
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/* Flip-Flop Reset */
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{
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case 0x0C:
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DmaControllers[0].FlipFlop = 0;
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break;
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case 0xD8:
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DmaControllers[1].FlipFlop = 0;
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break;
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}
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/* DMA Master Reset Registers */
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{
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case 0x0D:
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DmaControllers[0].Command = 0x00;
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DmaControllers[0].Status = 0x00;
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DmaControllers[0].Request = 0x00;
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DmaControllers[0].TempReg = 0x00;
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DmaControllers[0].FlipFlop = 0;
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DmaControllers[0].Mask = 0x0F;
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break;
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case 0xDA:
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DmaControllers[1].Command = 0x00;
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DmaControllers[1].Status = 0x00;
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DmaControllers[1].Request = 0x00;
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DmaControllers[1].TempReg = 0x00;
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DmaControllers[1].FlipFlop = 0;
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DmaControllers[1].Mask = 0x0F;
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break;
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}
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/* Mask Reset Registers */
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{
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case 0x0E:
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DmaControllers[0].Mask = 0x00;
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break;
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case 0xDC:
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DmaControllers[1].Mask = 0x00;
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break;
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}
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}
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}
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/* Page Address Registers */
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static BYTE WINAPI DmaPageReadPort(USHORT Port)
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{
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DPRINT1("DmaPageReadPort(Port = 0x%04X)\n", Port);
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switch (Port)
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{
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case 0x87:
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return DmaPageRegisters[0].Page;
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case 0x83:
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return DmaPageRegisters[1].Page;
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case 0x81:
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return DmaPageRegisters[2].Page;
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case 0x82:
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return DmaPageRegisters[3].Page;
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case 0x8F:
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return DmaPageRegisters[4].Page;
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case 0x8B:
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return DmaPageRegisters[5].Page;
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case 0x89:
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return DmaPageRegisters[6].Page;
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case 0x8A:
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return DmaPageRegisters[7].Page;
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}
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return 0x00;
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}
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static VOID WINAPI DmaPageWritePort(USHORT Port, BYTE Data)
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{
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DPRINT1("DmaPageWritePort(Port = 0x%04X, Data = 0x%02X)\n", Port, Data);
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switch (Port)
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{
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case 0x87:
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DmaPageRegisters[0].Page = Data;
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break;
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case 0x83:
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DmaPageRegisters[1].Page = Data;
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break;
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case 0x81:
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DmaPageRegisters[2].Page = Data;
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break;
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case 0x82:
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DmaPageRegisters[3].Page = Data;
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break;
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case 0x8F:
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DmaPageRegisters[4].Page = Data;
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break;
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case 0x8B:
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DmaPageRegisters[5].Page = Data;
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break;
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case 0x89:
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DmaPageRegisters[6].Page = Data;
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break;
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case 0x8A:
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DmaPageRegisters[7].Page = Data;
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break;
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}
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}
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/* PUBLIC FUNCTIONS ***********************************************************/
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DWORD DmaRequest(IN WORD iChannel,
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IN OUT PVOID Buffer,
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IN DWORD length)
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{
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/*
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* NOTE: This function is adapted from Wine's krnl386.exe,
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* DMA emulation by Christian Costa.
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*/
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PDMA_CONTROLLER pDcp;
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WORD Channel;
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DWORD i, Size, ret = 0;
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BYTE RegMode, OpMode, Increment, Autoinit, TrMode;
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PBYTE dmabuf = Buffer;
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ULONG CurrAddress;
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if (iChannel >= DMA_CONTROLLERS * DMA_CONTROLLER_CHANNELS)
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{
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SetLastError(ERROR_INVALID_ADDRESS);
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return 0;
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}
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pDcp = &DmaControllers[iChannel / DMA_CONTROLLER_CHANNELS];
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Channel = iChannel % DMA_CONTROLLER_CHANNELS; // == (iChannel & 0x03)
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RegMode = pDcp->DmaChannel[Channel].Mode;
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DPRINT1("DMA_Command = %x length=%d\n", RegMode, length);
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/* Exit if the controller is disabled or the channel is masked */
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if ((pDcp->Command & 0x04) || (pDcp->Mask & (1 << Channel)))
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return 0;
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OpMode = (RegMode & 0xC0) >> 6;
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Increment = !(RegMode & 0x20);
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Autoinit = RegMode & 0x10;
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TrMode = (RegMode & 0x0C) >> 2;
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/* Process operating mode */
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switch (OpMode)
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{
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case 0:
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/* Request mode */
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DPRINT1("Request Mode - Not Implemented\n");
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return 0;
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case 1:
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/* Single Mode */
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break;
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case 2:
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/* Request mode */
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DPRINT1("Block Mode - Not Implemented\n");
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return 0;
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case 3:
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/* Cascade Mode */
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DPRINT1("Cascade Mode should not be used by regular apps\n");
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return 0;
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}
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/* Perform one the 4 transfer modes */
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if (TrMode == 4)
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{
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/* Illegal */
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DPRINT1("DMA Transfer Type Illegal\n");
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return 0;
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}
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/* Transfer size : 8 bits for channels 0..3, 16 bits for channels 4..7 */
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Size = (iChannel < 4) ? sizeof(BYTE) : sizeof(WORD);
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// FIXME: Handle wrapping?
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/* Get the number of elements to transfer */
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ret = min(pDcp->DmaChannel[Channel].CurrElemCnt, length / Size);
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length = ret * Size;
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/* 16-bit mode addressing, see: http://wiki.osdev.org/ISA_DMA#16_bit_issues */
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CurrAddress = (iChannel < 4) ? (DmaPageRegisters[iChannel].Page << 16) | ((pDcp->DmaChannel[Channel].CurrAddress << 0) & 0xFFFF)
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: (DmaPageRegisters[iChannel].Page << 16) | ((pDcp->DmaChannel[Channel].CurrAddress << 1) & 0xFFFF);
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switch (TrMode)
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{
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/* Verification (no real transfer) */
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case 0:
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{
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DPRINT1("Verification DMA operation\n");
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break;
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}
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/* Write */
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case 1:
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{
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DPRINT1("Perform Write transfer of %d elements (%d bytes) at 0x%x %s with count %x\n",
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ret, length, CurrAddress, Increment ? "up" : "down", pDcp->DmaChannel[Channel].CurrElemCnt);
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if (Increment)
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{
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EmulatorWriteMemory(&EmulatorContext, CurrAddress, dmabuf, length);
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}
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else
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{
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for (i = 0; i < length; i++)
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{
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EmulatorWriteMemory(&EmulatorContext, CurrAddress - i, dmabuf + i, sizeof(BYTE));
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}
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}
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break;
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}
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/* Read */
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case 2:
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{
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DPRINT1("Perform Read transfer of %d elements (%d bytes) at 0x%x %s with count %x\n",
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ret, length, CurrAddress, Increment ? "up" : "down", pDcp->DmaChannel[Channel].CurrElemCnt);
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if (Increment)
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{
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EmulatorReadMemory(&EmulatorContext, CurrAddress, dmabuf, length);
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}
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else
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{
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for (i = 0; i < length; i++)
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{
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EmulatorReadMemory(&EmulatorContext, CurrAddress - i, dmabuf + i, sizeof(BYTE));
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}
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}
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break;
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}
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}
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/* Update DMA registers */
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pDcp->DmaChannel[Channel].CurrElemCnt -= ret;
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if (Increment)
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pDcp->DmaChannel[Channel].CurrAddress += ret;
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else
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pDcp->DmaChannel[Channel].CurrAddress -= ret;
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/* Check for end of transfer */
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if (pDcp->DmaChannel[Channel].CurrElemCnt == 0)
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{
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DPRINT1("DMA buffer empty\n");
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/* Update status register of the DMA chip corresponding to the channel */
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pDcp->Status |= 1 << Channel; /* Mark transfer as finished */
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pDcp->Status &= ~(1 << (Channel + 4)); /* Reset soft request if any */
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if (Autoinit)
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{
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/* Reload Current* registers to their initial values */
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pDcp->DmaChannel[Channel].CurrAddress = pDcp->DmaChannel[Channel].BaseAddress;
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pDcp->DmaChannel[Channel].CurrElemCnt = pDcp->DmaChannel[Channel].BaseElemCnt;
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}
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else
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{
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/* Set the mask bit for the channel */
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pDcp->Mask |= (1 << Channel);
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}
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}
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return length;
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}
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VOID DmaInitialize(VOID)
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{
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/* Register the I/O Ports */
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/* Channels 0(Reserved)..3 */
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RegisterIoPort(0x00, DmaReadPort, DmaWritePort); /* Current(R) / Start(W) Address Register 0 (Reserved) */
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RegisterIoPort(0x01, DmaReadPort, DmaWritePort); /* Current(R) / Base (W) Count Register 0 (Reserved) */
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RegisterIoPort(0x02, DmaReadPort, DmaWritePort); /* Current(R) / Start(W) Address Register 1 */
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RegisterIoPort(0x03, DmaReadPort, DmaWritePort); /* Current(R) / Base (W) Count Register 1 */
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RegisterIoPort(0x04, DmaReadPort, DmaWritePort); /* Current(R) / Start(W) Address Register 2 */
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RegisterIoPort(0x05, DmaReadPort, DmaWritePort); /* Current(R) / Base (W) Count Register 2 */
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RegisterIoPort(0x06, DmaReadPort, DmaWritePort); /* Current(R) / Start(W) Address Register 3 */
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RegisterIoPort(0x07, DmaReadPort, DmaWritePort); /* Current(R) / Base (W) Count Register 3 */
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RegisterIoPort(0x08, DmaReadPort, DmaWritePort); /* Status (Read) / Command (Write) Registers */
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RegisterIoPort(0x09, NULL, DmaWritePort); /* Request Register */
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RegisterIoPort(0x0A, NULL, DmaWritePort); /* Single Channel Mask Register */
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RegisterIoPort(0x0B, NULL, DmaWritePort); /* Mode Register */
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RegisterIoPort(0x0C, NULL, DmaWritePort); /* Flip-Flop Reset Register */
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RegisterIoPort(0x0D, DmaReadPort, DmaWritePort); /* Intermediate (Read) / Master Reset (Write) Registers */
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RegisterIoPort(0x0E, NULL, DmaWritePort); /* Mask Reset Register */
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RegisterIoPort(0x0F, DmaReadPort, DmaWritePort); /* Multi-Channel Mask Register */
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/* Channels 4(Reserved)..7 */
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RegisterIoPort(0xC0, DmaReadPort, DmaWritePort); /* Current(R) / Start(W) Address Register 4 (Reserved) */
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RegisterIoPort(0xC2, DmaReadPort, DmaWritePort); /* Current(R) / Base (W) Count Register 4 (Reserved) */
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RegisterIoPort(0xC4, DmaReadPort, DmaWritePort); /* Current(R) / Start(W) Address Register 5 */
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RegisterIoPort(0xC6, DmaReadPort, DmaWritePort); /* Current(R) / Base (W) Count Register 5 */
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RegisterIoPort(0xC8, DmaReadPort, DmaWritePort); /* Current(R) / Start(W) Address Register 6 */
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RegisterIoPort(0xCA, DmaReadPort, DmaWritePort); /* Current(R) / Base (W) Count Register 6 */
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RegisterIoPort(0xCC, DmaReadPort, DmaWritePort); /* Current(R) / Start(W) Address Register 7 */
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RegisterIoPort(0xCE, DmaReadPort, DmaWritePort); /* Current(R) / Base (W) Count Register 7 */
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RegisterIoPort(0xD0, DmaReadPort, DmaWritePort); /* Status (Read) / Command (Write) Registers */
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RegisterIoPort(0xD2, NULL, DmaWritePort); /* Request Register */
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RegisterIoPort(0xD4, NULL, DmaWritePort); /* Single Channel Mask Register */
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RegisterIoPort(0xD6, NULL, DmaWritePort); /* Mode Register */
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RegisterIoPort(0xD8, NULL, DmaWritePort); /* Flip-Flop Reset Register */
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RegisterIoPort(0xDA, DmaReadPort, DmaWritePort); /* Intermediate (Read) / Master Reset (Write) Registers */
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RegisterIoPort(0xDC, NULL, DmaWritePort); /* Mask Reset Register */
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RegisterIoPort(0xDE, DmaReadPort, DmaWritePort); /* Multi-Channel Mask Register */
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/* Channels Page Address Registers */
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RegisterIoPort(0x87, DmaPageReadPort, DmaPageWritePort); /* Channel 0 (Reserved) */
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RegisterIoPort(0x83, DmaPageReadPort, DmaPageWritePort); /* Channel 1 */
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RegisterIoPort(0x81, DmaPageReadPort, DmaPageWritePort); /* Channel 2 */
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RegisterIoPort(0x82, DmaPageReadPort, DmaPageWritePort); /* Channel 3 */
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RegisterIoPort(0x8F, DmaPageReadPort, DmaPageWritePort); /* Channel 4 (Reserved) */
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RegisterIoPort(0x8B, DmaPageReadPort, DmaPageWritePort); /* Channel 5 */
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RegisterIoPort(0x89, DmaPageReadPort, DmaPageWritePort); /* Channel 6 */
|
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RegisterIoPort(0x8A, DmaPageReadPort, DmaPageWritePort); /* Channel 7 */
|
|
}
|
|
|
|
|
|
|
|
DWORD
|
|
WINAPI
|
|
VDDRequestDMA(IN HANDLE hVdd,
|
|
IN WORD iChannel,
|
|
IN OUT PVOID Buffer,
|
|
IN DWORD length)
|
|
{
|
|
UNREFERENCED_PARAMETER(hVdd);
|
|
|
|
if (iChannel >= DMA_CONTROLLERS * DMA_CONTROLLER_CHANNELS)
|
|
{
|
|
SetLastError(ERROR_INVALID_ADDRESS);
|
|
return FALSE;
|
|
}
|
|
|
|
/*
|
|
* We assume success first. If something fails,
|
|
* DmaRequest sets an adequate last error.
|
|
*/
|
|
SetLastError(ERROR_SUCCESS);
|
|
|
|
return DmaRequest(iChannel, Buffer, length);
|
|
}
|
|
|
|
BOOL
|
|
WINAPI
|
|
VDDQueryDMA(IN HANDLE hVdd,
|
|
IN WORD iChannel,
|
|
IN PVDD_DMA_INFO pDmaInfo)
|
|
{
|
|
PDMA_CONTROLLER pDcp;
|
|
WORD Channel;
|
|
|
|
UNREFERENCED_PARAMETER(hVdd);
|
|
|
|
if (iChannel >= DMA_CONTROLLERS * DMA_CONTROLLER_CHANNELS)
|
|
{
|
|
SetLastError(ERROR_INVALID_ADDRESS);
|
|
return FALSE;
|
|
}
|
|
|
|
pDcp = &DmaControllers[iChannel / DMA_CONTROLLER_CHANNELS];
|
|
Channel = iChannel % DMA_CONTROLLER_CHANNELS;
|
|
|
|
pDmaInfo->addr = pDcp->DmaChannel[Channel].CurrAddress;
|
|
pDmaInfo->count = pDcp->DmaChannel[Channel].CurrElemCnt;
|
|
|
|
pDmaInfo->page = DmaPageRegisters[iChannel].Page;
|
|
pDmaInfo->status = pDcp->Status;
|
|
pDmaInfo->mode = pDcp->DmaChannel[Channel].Mode;
|
|
pDmaInfo->mask = pDcp->Mask;
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
BOOL
|
|
WINAPI
|
|
VDDSetDMA(IN HANDLE hVdd,
|
|
IN WORD iChannel,
|
|
IN WORD fDMA,
|
|
IN PVDD_DMA_INFO pDmaInfo)
|
|
{
|
|
PDMA_CONTROLLER pDcp;
|
|
WORD Channel;
|
|
|
|
UNREFERENCED_PARAMETER(hVdd);
|
|
|
|
if (iChannel >= DMA_CONTROLLERS * DMA_CONTROLLER_CHANNELS)
|
|
{
|
|
SetLastError(ERROR_INVALID_ADDRESS);
|
|
return FALSE;
|
|
}
|
|
|
|
pDcp = &DmaControllers[iChannel / DMA_CONTROLLER_CHANNELS];
|
|
Channel = iChannel % DMA_CONTROLLER_CHANNELS;
|
|
|
|
if (fDMA & VDD_DMA_ADDR)
|
|
pDcp->DmaChannel[Channel].CurrAddress = pDmaInfo->addr;
|
|
|
|
if (fDMA & VDD_DMA_COUNT)
|
|
pDcp->DmaChannel[Channel].CurrElemCnt = pDmaInfo->count;
|
|
|
|
if (fDMA & VDD_DMA_PAGE)
|
|
DmaPageRegisters[iChannel].Page = pDmaInfo->page;
|
|
|
|
if (fDMA & VDD_DMA_STATUS)
|
|
pDcp->Status = pDmaInfo->status;
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
/* EOF */
|