mirror of
https://github.com/reactos/reactos.git
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170 lines
6.6 KiB
C
170 lines
6.6 KiB
C
/*
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* COPYRIGHT: See COPYING in the top level directory
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* PROJECT: ReactOS RTL8139 Driver
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* FILE: rtlhw.h
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* PURPOSE: 8139 NIC definitions
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*/
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#pragma once
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#define MAXIMUM_MULTICAST_ADDRESSES 8
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#define DEFAULT_INTERRUPT_MASK (R_I_RXOK | R_I_RXERR | R_I_TXOK | \
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R_I_TXERR | R_I_RXOVRFLW | R_I_RXUNDRUN | \
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R_I_FIFOOVR | R_I_PCSTMOUT | R_I_PCIERR)
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#define TX_DESC_COUNT 4
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//Register addresses
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#define R_MAC 0x00 //MAC address uses bytes 0-5, 6 and 7 are reserved
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#define R_MCAST0 0x08 //Multicast registers
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#define R_MCAST1 0x09 //Multicast registers
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#define R_MCAST2 0x0A
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#define R_MCAST3 0x0B
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#define R_MCAST4 0x0C
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#define R_MCAST5 0x0D
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#define R_MCAST6 0x0E
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#define R_MCAST7 0x0F
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#define R_TXSTS0 0x10 //TX status, 0x10-0x13, 4 bytes
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#define R_TXSTS1 0x14
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#define R_TXSTS2 0x18
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#define R_TXSTS3 0x1C
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#define R_TXSAD0 0x20 //TX start address of descriptor 0
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#define R_TXSAD1 0x24
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#define R_TXSAD2 0x28
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#define R_TXSAD3 0x2C
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#define R_RXSA 0x30 //RX buffer start address
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#define R_ERXBC 0x34 //Early RX byte count register
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#define R_ERXSTS 0x36 //Early RX status register
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#define R_TXS_HOSTOWNS 0x00002000 //Driver still owns the buffer
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#define R_TXS_UNDERRUN 0x00004000 //TX underrun
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#define R_TXS_STATOK 0x00008000 //Successful TX
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#define R_TXS_OOW 0x20000000 //Out of window
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#define R_TXS_ABORTED 0x40000000 //TX aborted
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#define R_TXS_CARLOST 0x80000000 //Carrier lost
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#define R_CMD 0x37 //Command register
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#define R_CMD_RXEMPTY 0x01 //Receive buffer empty
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#define B_CMD_TXE 0x04 //Enable TX
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#define B_CMD_RXE 0x08 //Enable RX
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#define B_CMD_RST 0x10 //Reset bit
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#define R_CAPR 0x38 //Current address of packet read
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#define R_CBA 0x3A //Current buffer address
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#define R_IM 0x3C //Interrupt mask register
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#define R_IS 0x3E //Interrupt status register
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#define R_TC 0x40 //Transmit configuration register
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#define R_I_RXOK 0x0001 //Receive OK
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#define R_I_RXERR 0x0002 //Receive error
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#define R_I_TXOK 0x0004 //Transmit OK
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#define R_I_TXERR 0x0008 //Trasmit error
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#define R_I_RXOVRFLW 0x0010 //Receive overflow
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#define R_I_RXUNDRUN 0x0020 //Receive underrun
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#define R_I_FIFOOVR 0x0040 //FIFO overflow
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#define R_I_PCSTMOUT 0x4000 //PCS timeout
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#define R_I_PCIERR 0x8000 //PCI error
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#define R_RC 0x44 //Receive configuration register
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#define B_RC_AAP 0x01 //Accept all packets
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#define B_RC_APM 0x02 //Accept packets sent to device MAC
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#define B_RC_AM 0x04 //Accept multicast packets
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#define B_RC_AB 0x08 //Accept broadcast packets
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#define B_RC_AR 0x10 //Accept runt (smaller than 64bytes) packets
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#define R_TCTR 0x48 //Timer counter register
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#define R_MPC 0x4C //Missed packet counter
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#define R_9346CR 0x50 //93C46 command register
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#define R_CFG0 0x51 //Configuration register 0
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#define R_CFG1 0x52
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#define R_TINTR 0x54 //Timer interrupt register
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#define R_MS 0x58 //Media status register
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#define R_MS_LINKDWN 0x04 //Link is down
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#define R_MS_SPEED_10 0x08 //Media is at 10mbps
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#define R_CFG3 0x59 //Configuration register 3
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#define R_CFG4 0x5A //Configuration register 4
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#define R_MINTS 0x5C //Multiple interrupt select
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#define R_PCIID 0x5E //PCI Revision ID = 0x10
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#define R_DTSTS 0x60 //TX status of all descriptors
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#define R_BMC 0x62 //Basic mode control register
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#define R_BMSTS 0x64 //Basic mode status register
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#define R_ANA 0x66 //Auto-negotiation advertisement
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#define R_ANLP 0x68 //Auto-negotiation link partner
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#define R_ANEX 0x6A //Auto-negotiation expansion
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#define R_DCTR 0x6C //Disconnect counter
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#define R_FCSCTR 0x6E //False carrier sense counter
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#define R_NWT 0x70 //N-way test register
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#define R_RXERRCTR 0x72 //RX error counter
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#define R_CSCFG 0x74 //CS configuration register
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#define R_CSCR_LINKOK 0x00400 //Link up
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#define R_CSCR_LINKCHNG 0x00800 //Link changed
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#define R_PHYP1 0x78 //PHY parameter 1
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#define R_TWP 0x7C //Twister parameter
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#define R_PHYP2 0x80 //PHY parameter 2
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#define R_PCRC0 0x84 //Power management CRC for wakeup frame 0
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#define R_PCRC1 0x85
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#define R_PCRC2 0x86
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#define R_PCRC3 0x87
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#define R_PCRC4 0x88
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#define R_PCRC5 0x89
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#define R_PCRC6 0x8A
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#define R_PCRC7 0x8B
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#define R_WAKE0 0x8C //Power management wakeup frame 0
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#define R_WAKE1 0x94
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#define R_WAKE2 0x9C
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#define R_WAKE3 0xA4
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#define R_WAKE4 0xAC
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#define R_WAKE5 0xB4
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#define R_WAKE6 0xBC
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#define R_WAKE7 0xC4
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#define R_LSBCRC0 0xCC //LSB of the mask byte of wakeup frame 0 within offset 12 to 75
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#define R_LSBCRC1 0xCD
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#define R_LSBCRC2 0xCE
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#define R_LSBCRC3 0xCF
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#define R_LSBCRC4 0xD0
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#define R_LSBCRC5 0xD1
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#define R_LSBCRC6 0xD2
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#define R_LSBCRC7 0xD3
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#define R_CFG5 0xD8 //Configuration register 5
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//EEPROM Control Bytes
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#define EE_DATA_READ 0x01 //Chip data out
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#define EE_DATA_WRITE 0x02 //Chip data in
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#define EE_SHIFT_CLK 0x04 //Chip shift clock
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#define EE_CS 0x08 //Chip select
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#define EE_ENB 0x88 //Chip enable
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//EEPROM Commands
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#define EE_READ_CMD 0x06
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#define RSR_MAR 0x8000 //Multicast receive
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#define RSR_PAM 0x4000 //Physical address match (directed packet)
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#define RSR_BAR 0x2000 //Broadcast receive
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#define RSR_ISE 0x0020 //Invalid symbol
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#define RSR_RUNT 0x0010 //Runt packet
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#define RSR_LONG 0x0008 //Long packet
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#define RSR_CRC 0x0004 //CRC error
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#define RSR_FAE 0x0002 //Frame alignment error
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#define RSR_ROK 0x0001 //Receive OK
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/* NIC prepended structure to a received packet */
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typedef struct _PACKET_HEADER {
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USHORT Status; /* See RSR_* constants */
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USHORT PacketLength; /* Length of packet NOT including this header */
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} PACKET_HEADER, *PPACKET_HEADER;
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#define IEEE_802_ADDR_LENGTH 6
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/* Ethernet frame header */
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typedef struct _ETH_HEADER {
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UCHAR Destination[IEEE_802_ADDR_LENGTH];
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UCHAR Source[IEEE_802_ADDR_LENGTH];
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USHORT PayloadType;
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} ETH_HEADER, *PETH_HEADER;
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/* EOF */
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