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119 lines
3.8 KiB
C
119 lines
3.8 KiB
C
#include "precomp.h"
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//
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// Minimal Attribute Controller Registers initialization command stream.
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// Compatible EGA.
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//
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USHORT AT_Initialization[] =
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{
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/* Reset ATC to index mode */
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IB,
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VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */,
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/* Write the AC registers */
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METAOUT+ATCOUT,
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VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */,
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16, 0, // Values Count and Start Index
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, // Palette indices 0-5
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0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, // Palette indices 6-11
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0x0C, 0x0D, 0x0E, 0x0F, // Palette indices 12-15
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/* Reset ATC to index mode */
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IB,
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VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */,
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/* Enable screen and disable palette access */
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OB,
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VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */,
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VIDEO_ENABLE,
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/* End of Stream */
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EOD
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};
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//
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// 640x480 256-color 60Hz mode (BIOS mode 12) set command stream for VGA.
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// Adapted from win32ss/drivers/miniport/vga_new/vgadata.c
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//
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USHORT VGA_640x480[] =
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{
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/* Write the Sequencer Registers */
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OWM,
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VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT,
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VGA_NUM_SEQUENCER_PORTS, // Values Count (5)
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// HI: Value in SEQ_DATA_PORT, LO: Register index in SEQ_ADDRESS_PORT
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0x0100, // Synchronous reset on
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0x0101, // 8-Dot Mode
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0x0F02, // Memory Plane Write Enable on all planes 0-3
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0x0003, // No character set selected
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0x0604, // Disable Odd/Even host mem addressing; Enable Extended Memory
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/* Write the Miscellaneous Register */
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OB,
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VGA_BASE_IO_PORT + MISC_OUTPUT_REG_WRITE_PORT,
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0xE3, // V/H-SYNC polarity, Odd/Even High page select, RAM enable,
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// I/O Address select (1: color/graphics adapter)
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/* Enable Graphics Mode */
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OW,
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VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT,
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// HI: Value in GRAPH_DATA_PORT, LO: Register index in GRAPH_ADDRESS_PORT
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0x506, // Select A0000h-AFFFFh memory region, Disable Alphanumeric mode
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/* Synchronous reset off */
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OW,
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VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT,
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// HI: Value in SEQ_DATA_PORT, LO: Register index in SEQ_ADDRESS_PORT
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0x0300, // Synchronous reset off (LO: IND_SYNC_RESET, HI: END_SYNC_RESET_VALUE)
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/* Unlock CRTC registers 0-7 */
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OW,
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VGA_BASE_IO_PORT + CRTC_ADDRESS_PORT_COLOR,
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0x511,
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/* Write the CRTC registers */
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METAOUT+INDXOUT,
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VGA_BASE_IO_PORT + CRTC_ADDRESS_PORT_COLOR,
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VGA_NUM_CRTC_PORTS, 0, // Values Count (25) and Start Index
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0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0x0B, 0x3E, 0x00, 0x40, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0xEA, 0x8C, 0xDF, 0x28, 0x00, 0xE7, 0x04, 0xE3,
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0xFF,
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/* Reset ATC to index mode */
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IB,
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VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */,
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/* Write the AC registers */
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METAOUT+ATCOUT,
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VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */,
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VGA_NUM_ATTRIB_CONT_PORTS, 0, // Values Count (21) and Start Index
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, // Palette indices 0-5
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0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, // Palette indices 6-11
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0x0C, 0x0D, 0x0E, 0x0F, // Palette indices 12-15
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0x01, 0x00, 0x0F, 0x00, 0x00,
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/* Write the GC registers */
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METAOUT+INDXOUT,
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VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT,
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VGA_NUM_GRAPH_CONT_PORTS, 0, // Values Count (9) and Start Index
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x05, 0x0F, 0xFF,
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/* Set the PEL mask */
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OB,
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VGA_BASE_IO_PORT + DAC_PIXEL_MASK_PORT,
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0xFF,
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/* Reset ATC to index mode */
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IB,
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VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */,
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/* Enable screen and disable palette access */
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OB,
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VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */,
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VIDEO_ENABLE,
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/* End of Stream */
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EOD
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};
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