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415 lines
20 KiB
C
415 lines
20 KiB
C
/*
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* ReactOS AMD PCNet Driver
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*
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* Copyright (C) 2003 Vizzini <vizzini@plasmic.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* PURPOSE:
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* PCNet hardware configuration constants
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* REVISIONS:
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* 01-Sept-2003 vizzini - Created
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* NOTES:
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* - This file represents a clean re-implementation from the AMD
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* PCNet II chip documentation (Am79C790A, pub# 19436).
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*/
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#pragma once
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/* when in 32-bit mode, most registers require the top 16 bits be 0. */
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#define MASK16(__x__) ((__x__) & 0x0000ffff)
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#define NUMBER_OF_PORTS 0x20 /* number of i/o ports the board requires */
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/* offsets of important registers */
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#define RDP 0x10 /* same address in 16-bit and 32-bit IO mode */
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#define RAP16 0x12
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#define RESET16 0x14
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#define BDP16 0x16
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#define RAP32 0x14
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#define RESET32 0x18
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#define BDP32 0x1c
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/* NOTE: vmware doesn't support 32-bit i/o programming so we use 16-bit */
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#define RAP RAP16
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#define BDP BDP16
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/* pci id of the device */
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#define PCI_ID 0x20001022
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#define VEN_ID 0x1022
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#define DEV_ID 0x2000
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/* software style constants */
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#define SW_STYLE_0 0
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#define SW_STYLE_1 1
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#define SW_STYLE_2 2
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#define SW_STYLE_3 3
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/* control and status registers */
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#define CSR0 0x0 /* controller status register */
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#define CSR1 0x1 /* init block address 0 */
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#define CSR2 0x2 /* init block address 1 */
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#define CSR3 0x3 /* interrupt masks and deferral control */
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#define CSR4 0x4 /* test and features control */
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#define CSR5 0x5 /* extended control and interrupt */
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#define CSR6 0x6 /* rx/tx descriptor table length */
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#define CSR8 0x8 /* logical address filter 0 */
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#define CSR9 0x9 /* logical address filter 1 */
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#define CSR10 0xa /* logical address filter 2 */
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#define CSR11 0xb /* logical address filter 3 */
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#define CSR12 0xc /* physical address register 0 */
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#define CSR13 0xd /* physical address register 1 */
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#define CSR14 0xe /* physical address register 2 */
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#define CSR15 0xf /* Mode */
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#define CSR16 0x10 /* initialization block address lower */
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#define CSR17 0x11 /* initialization block address upper */
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#define CSR18 0x12 /* current receive buffer address lower */
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#define CSR19 0x13 /* current receive buffer address upper */
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#define CSR20 0x14 /* current transmit buffer address lower */
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#define CSR21 0x15 /* current transmit buffer address upper */
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#define CSR22 0x16 /* next receive buffer address lower */
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#define CSR23 0x17 /* next receive buffer address upper */
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#define CSR24 0x18 /* base address of receive descriptor ring lower */
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#define CSR25 0x19 /* base address of receive descriptor ring upper */
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#define CSR26 0x1a /* next receive descriptor address lower */
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#define CSR27 0x1b /* next receive descriptor address upper */
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#define CSR28 0x1c /* current receive descriptor address lower */
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#define CSR29 0x1d /* current receive descriptor address upper */
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#define CSR30 0x1e /* base address of transmit descriptor ring lower */
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#define CSR31 0x1f /* base address of transmit descriptor ring upper */
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#define CSR32 0x20 /* next transmit descriptor address lower */
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#define CSR33 0x21 /* next transmit descriptor address upper */
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#define CSR34 0x22 /* current transmit descriptor address lower */
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#define CSR35 0x23 /* current transmit descriptor address upper */
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#define CSR36 0x24 /* next next receive descriptor address lower */
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#define CSR37 0x25 /* next next receive descriptor address upper */
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#define CSR38 0x26 /* next next transmit descriptor address lower */
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#define CSR39 0x27 /* next next transmit descriptor address upper */
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#define CSR40 0x28 /* current receive byte count */
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#define CSR41 0x29 /* current receive status */
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#define CSR42 0x2a /* current transmit byte count */
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#define CSR43 0x2b /* current transmit status */
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#define CSR44 0x2c /* next receive byte count */
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#define CSR45 0x2d /* next receive status */
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#define CSR46 0x2e /* poll time counter */
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#define CSR47 0x2f /* polling interval */
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#define CSR58 0x3a /* software style */
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#define CSR60 0x3c /* previous transmit descriptor address lower */
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#define CSR61 0x3d /* previous transmit descriptor address upper */
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#define CSR62 0x3e /* previous transmit byte count */
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#define CSR63 0x3f /* previous transmit status */
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#define CSR64 0x40 /* next transmit buffer address lower */
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#define CSR65 0x41 /* next transmit buffer address upper */
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#define CSR66 0x42 /* next transmit byte count */
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#define CSR67 0x43 /* next transmit status */
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#define CSR72 0x48 /* receive descriptor ring counter */
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#define CSR74 0x4a /* transmit descriptor ring counter */
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#define CSR76 0x4c /* receive descriptor ring length */
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#define CSR78 0x4e /* transmit descriptor ring length */
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#define CSR80 0x50 /* dma transfer counter and fifo watermark control */
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#define CSR82 0x52 /* bus activity timer */
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#define CSR84 0x54 /* dma address register lower */
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#define CSR85 0x55 /* dma address register upper */
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#define CSR86 0x56 /* buffer byte counter */
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#define CSR88 0x58 /* chip id register lower */
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#define CSR89 0x59 /* chip id register upper */
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#define CSR94 0x5e /* transmit time domain reflectometry count */
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#define CSR100 0x64 /* bus timeout */
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#define CSR112 0x70 /* missed frame count */
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#define CSR114 0x72 /* receive collision count */
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#define CSR122 0x7a /* advanced feature control */
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#define CSR124 0x7c /* test register control */
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/* bus configuration registers */
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#define BCR2 0x2 /* miscellaneous configuration */
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#define BCR4 0x4 /* link status led */
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#define BCR5 0x5 /* led1 status */
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#define BCR6 0x6 /* led2 status */
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#define BCR7 0x7 /* led3 status */
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#define BCR9 0x9 /* full-duplex control */
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#define BCR16 0x10 /* i/o base address lower */
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#define BCR17 0x11 /* i/o base address upper */
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#define BCR18 0x12 /* burst and bus control register */
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#define BCR19 0x13 /* eeprom control and status */
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#define BCR20 0x14 /* software style */
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#define BCR21 0x15 /* interrupt control */
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#define BCR22 0x16 /* pci latency register */
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/* CSR0 bits */
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#define CSR0_INIT 0x1 /* read initialization block */
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#define CSR0_STRT 0x2 /* start the chip */
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#define CSR0_STOP 0x4 /* stop the chip */
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#define CSR0_TDMD 0x8 /* transmit demand */
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#define CSR0_TXON 0x10 /* transmit on */
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#define CSR0_RXON 0x20 /* receive on */
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#define CSR0_IENA 0x40 /* interrupt enabled */
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#define CSR0_INTR 0x80 /* interrupting */
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#define CSR0_IDON 0x100 /* initialization done */
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#define CSR0_TINT 0x200 /* transmit interrupt */
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#define CSR0_RINT 0x400 /* receive interrupt */
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#define CSR0_MERR 0x800 /* memory error */
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#define CSR0_MISS 0x1000 /* missed frame */
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#define CSR0_CERR 0x2000 /* collision error */
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#define CSR0_BABL 0x4000 /* babble */
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#define CSR0_ERR 0x8000 /* error */
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/* CSR3 bits */
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#define CSR3_BSWP 0x4 /* byte swap */
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#define CSR3_EMBA 0x8 /* enable modified backoff algorithm */
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#define CSR3_DXMT2PD 0x10 /* disable transmit two-part deferral */
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#define CSR3_LAPPEN 0x20 /* lookahead packet processing enable */
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#define CSR3_DXSUFLO 0x40 /* disable transmit stop on underflow */
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#define CSR3_IDONM 0x100 /* initialization done mask */
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#define CSR3_TINTM 0x200 /* transmit interrupt mask */
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#define CSR3_RINTM 0x400 /* receive interrupt mask */
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#define CSR3_MERRM 0x800 /* memory error interrupt mask */
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#define CSR3_MISSM 0x1000 /* missed frame interrupt mask */
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#define CSR3_BABLM 0x4000 /* babble interrupt mask */
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/* CSR4 bits */
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#define CSR4_JABM 0x1 /* jabber interrupt mask */
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#define CSR4_JAB 0x2 /* interrupt on jabber error */
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#define CSR4_TXSTRTM 0x4 /* transmit start interrupt mask */
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#define CSR4_TXSTRT 0x8 /* interrupt on transmit start */
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#define CSR4_RCVCCOM 0x10 /* receive collision counter overflow mask */
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#define CSR4_RCVCCO 0X20 /* interrupt on receive collision counter overflow */
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#define CSR4_UINT 0x40 /* user interrupt */
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#define CSR4_UINTCMD 0x80 /* user interrupt command */
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#define CSR4_MFCOM 0x100 /* missed frame counter overflow mask */
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#define CSR4_MFCO 0x200 /* interrupt on missed frame counter overflow */
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#define CSR4_ASTRP_RCV 0x400 /* auto pad strip on receive */
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#define CSR4_APAD_XMT 0x800 /* auto pad on transmit */
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#define CSR4_DPOLL 0x1000 /* disable transmit polling */
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#define CSR4_TIMER 0x2000 /* enable bus activity timer */
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#define CSR4_DMAPLUS 0x4000 /* set to 1 for pci */
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#define CSR4_EN124 0x8000 /* enable CSR124 access */
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/* CSR5 bits */
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#define CSR5_SPND 0x1 /* suspend */
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#define CSR5_MPMODE 0x2 /* magic packet mode */
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#define CSR5_MPEN 0x4 /* magic packet enable */
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#define CSR5_MPINTE 0x8 /* magic packet interrupt enable */
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#define CSR5_MPINT 0x10 /* magic packet interrupt */
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#define CSR5_MPPLBA 0x20 /* magic packet physical logical broadcast accept */
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#define CSR5_EXDINTE 0x40 /* excessive deferral interrupt enable */
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#define CSR5_EXDINT 0x80 /* excessive deferral interrupt */
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#define CSR5_SLPINTE 0x100 /* sleep interrupt enable */
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#define CSR5_SLPINT 0x200 /* sleep interrupt */
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#define CSR5_SINE 0x400 /* system interrupt enable */
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#define CSR5_SINT 0x800 /* system interrupt */
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#define CSR5_LTINTEN 0x4000 /* last transmit interrupt enable */
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#define CSR5_TOKINTD 0x8000 /* transmit ok interrupt disable */
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/* CSR15 bits */
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#define CSR15_DRX 0x1 /* disable receiver */
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#define CSR15_DTX 0x2 /* disable transmitter */
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#define CSR15_LOOP 0x4 /* loopback enable */
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#define CSR15_DXMTFCS 0x8 /* disable transmit fcs */
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#define CSR15_FCOLL 0x10 /* force collision */
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#define CSR15_DRTY 0x20 /* disable retry */
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#define CSR15_INTL 0x40 /* internal loopback */
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#define CSR15_PORTSEL0 0x80 /* port selection bit 0 */
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#define CSR15_PORTSEL1 0x100 /* port selection bit 1 */
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#define CSR15_LRT 0x200 /* low receive threshold - same as TSEL */
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#define CSR15_TSEL 0x200 /* transmit mode select - same as LRT */
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#define CSR15_MENDECL 0x400 /* mendec loopback mode */
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#define CSR15_DAPC 0x800 /* disable automatic parity correction */
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#define CSR15_DLNKTST 0x1000 /* disable link status */
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#define CSR15_DRCVPA 0x2000 /* disable receive physical address */
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#define CSR15_DRCVBC 0x4000 /* disable receive broadcast */
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#define CSR15_PROM 0x8000 /* promiscuous mode */
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/* CSR58 bits */
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#define CSR58_SSIZE32 0x100 /* 32-bit software size */
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#define CSR58_CSRPCNET 0x200 /* csr pcnet-isa configuration */
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#define CSR58_APERREN 0x400 /* advanced parity error handling enable */
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/* CSR124 bits */
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#define CSR124_RPA 0x4 /* runt packet accept */
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/* BCR2 bits */
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#define BCR2_ASEL 0x2 /* auto-select media */
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#define BCR2_AWAKE 0x4 /* select sleep mode */
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#define BCR2_EADISEL 0x8 /* eadi select */
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#define BCR2_DXCVRPOL 0x10 /* dxcvr polarity */
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#define BCR2_DXCVRCTL 0x20 /* dxcvr control */
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#define BCR2_INTLEVEL 0x80 /* interrupt level/edge */
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#define BCR2_APROMWE 0x100 /* address prom write enable */
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#define BCR2_LEDPE 0x1000 /* LED programming enable */
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#define BCR2_TMAULOOP 0x4000 /* t-mau transmit on loopback */
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/* BCR4 bits */
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#define BCR4_COLE 0x1 /* collision status enable */
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#define BCR4_JABE 0x2 /* jabber status enable */
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#define BCR4_RCVE 0x4 /* receive status enable */
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#define BCR4_RXPOLE 0x8 /* receive polarity status enable */
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#define BCR4_XMTE 0x10 /* transmit status enable */
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#define BCR4_RCVME 0x20 /* receive match status enable */
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#define BCR4_LNKSTE 0x40 /* link status enable */
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#define BCR4_PSE 0x80 /* pulse stretcher enable */
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#define BCR4_FDLSE 0x100 /* full-duplex link status enable */
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#define BCR4_MPSE 0x200 /* magic packet status enable */
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#define BCR4_E100 0x1000 /* link speed */
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#define BCR4_LEDDIS 0x2000 /* led disable */
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#define BCR4_LEDPOL 0x4000 /* led polarity */
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#define BCR4_LEDOUT 0x8000 /* led output pin value */
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/* BCR5 bits */
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#define BCR5_COLE 0x1 /* collision status enable */
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#define BCR5_JABE 0x2 /* jabber status enable */
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#define BCR5_RCVE 0x4 /* receive status enable */
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#define BCR5_RXPOLE 0x8 /* receive polarity status enable */
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#define BCR5_XMTE 0x10 /* transmit status enable */
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#define BCR5_RCVME 0x20 /* receive match status enable */
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#define BCR5_LNKSTE 0x40 /* link status enable */
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#define BCR5_PSE 0x80 /* pulse stretcher enable */
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#define BCR5_FDLSE 0x100 /* full-duplex link status enable */
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#define BCR5_MPSE 0x200 /* magic packet status enable */
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#define BCR5_E100 0x1000 /* link speed */
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#define BCR5_LEDDIS 0x2000 /* led disable */
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#define BCR5_LEDPOL 0x4000 /* led polarity */
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#define BCR5_LEDOUT 0x8000 /* led output pin value */
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/* BCR6 bits */
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#define BCR6_COLE 0x1 /* collision status enable */
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#define BCR6_JABE 0x2 /* jabber status enable */
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#define BCR6_RCVE 0x4 /* receive status enable */
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#define BCR6_RXPOLE 0x8 /* receive polarity status enable */
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#define BCR6_XMTE 0x10 /* transmit status enable */
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#define BCR6_RCVME 0x20 /* receive match status enable */
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#define BCR6_LNKSTE 0x40 /* link status enable */
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#define BCR6_PSE 0x80 /* pulse stretcher enable */
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#define BCR6_FDLSE 0x100 /* full-duplex link status enable */
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#define BCR6_MPSE 0x200 /* magic packet status enable */
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#define BCR6_E100 0x1000 /* link speed */
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#define BCR6_LEDDIS 0x2000 /* led disable */
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#define BCR6_LEDPOL 0x4000 /* led polarity */
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#define BCR6_LEDOUT 0x8000 /* led output pin value */
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/* BCR7 bits */
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#define BCR7_COLE 0x1 /* collision status enable */
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#define BCR7_JABE 0x2 /* jabber status enable */
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#define BCR7_RCVE 0x4 /* receive status enable */
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#define BCR7_RXPOLE 0x8 /* receive polarity status enable */
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#define BCR7_XMTE 0x10 /* transmit status enable */
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#define BCR7_RCVME 0x20 /* receive match status enable */
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#define BCR7_LNKSTE 0x40 /* link status enable */
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#define BCR7_PSE 0x80 /* pulse stretcher enable */
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#define BCR7_FDLSE 0x100 /* full-duplex link status enable */
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#define BCR7_MPSE 0x200 /* magic packet status enable */
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#define BCR7_E100 0x1000 /* link speed */
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#define BCR7_LEDDIS 0x2000 /* led disable */
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#define BCR7_LEDPOL 0x4000 /* led polarity */
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#define BCR7_LEDOUT 0x8000 /* led output pin value */
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/* BCR9 bits */
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#define BCR9_FDEN 0x1 /* full-duplex enable */
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#define BCR9_AUIFD 0x2 /* aui full-duplex */
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#define BCR9_FDRPAD 0x4 /* full-duplex runt packet accept disable */
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/* BCR18 bits */
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#define BCR18_BWRITE 0x20 /* burst write enable */
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#define BCR18_BREADE 0x40 /* burst read enable */
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#define BCR18_DWIO 0x80 /* dword i/o enable */
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#define BCR18_EXTREQ 0x100 /* extended request */
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#define BCR18_MEMCMD 0x200 /* memory command */
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/* BCR19 bits */
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#define BCR19_EDI 0x1 /* eeprom data in - same as EDO */
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#define BCR19_ED0 0x1 /* eeprom data out - same as EDI */
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#define BCR19_ESK 0x2 /* eeprom serial clock */
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#define BCR19_ECS 0x4 /* eeprom chip select */
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#define BCR19_EEN 0x8 /* eeprom port enable */
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#define BCR19_EEDET 0x2000 /* eeprom detect */
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#define BCR19_PREAD 0x4000 /* eeprom read */
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#define BCR19_PVALID 0x8000 /* eeprom valid */
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/* BCR20 bits */
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#define BCR20_SSIZE32 0x100 /* 32-bit software size */
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#define BCR20_CSRPCNET 0x200 /* csr pcnet-isa configuration */
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#define BCR20_APERREN 0x400 /* advanced parity error handling enable */
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/* initialization block for 32-bit software style */
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typedef struct _INITIALIZATION_BLOCK
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{
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USHORT MODE; /* card mode (csr15) */
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UCHAR RLEN; /* encoded number of receive descriptor ring entries */
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UCHAR TLEN; /* encoded number of transmit descriptor ring entries */
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UCHAR PADR[6]; /* physical address */
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USHORT RES; /* reserved */
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UCHAR LADR[8]; /* logical address */
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ULONG RDRA; /* receive descriptor ring address */
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ULONG TDRA; /* transmit descriptor ring address */
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} INITIALIZATION_BLOCK, *PINITIALIZATION_BLOCK;
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/* receive descriptor, software stle 2 (32-bit) */
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typedef struct _RECEIVE_DESCRIPTOR
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{
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ULONG RBADR; /* receive buffer address */
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USHORT BCNT; /* two's compliment buffer byte count - NOTE: always OR with 0xf000 */
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USHORT FLAGS; /* flags - always and with 0xfff0 */
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USHORT MCNT; /* message byte count ; always AND with 0x0fff */
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UCHAR RPC; /* runt packet count */
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UCHAR RCC; /* receive collision count */
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ULONG RES; /* reserved */
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} RECEIVE_DESCRIPTOR, *PRECEIVE_DESCRIPTOR;
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/* receive descriptor flags */
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#define RD_BAM 0x10 /* broadcast address match */
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#define RD_LAFM 0x20 /* logical address filter match */
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#define RD_PAM 0x40 /* physical address match */
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#define RD_BPE 0x80 /* bus parity error */
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#define RD_ENP 0x100 /* end of packet */
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#define RD_STP 0x200 /* start of packet */
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#define RD_BUFF 0x400 /* buffer error */
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#define RD_CRC 0x800 /* crc error */
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#define RD_OFLO 0x1000 /* overflow error */
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#define RD_FRAM 0x2000 /* framing error */
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#define RD_ERR 0x4000 /* an error bit is set */
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#define RD_OWN 0x8000 /* buffer ownership (0=host, 1=nic) */
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/* transmit descriptor, software style 2 */
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typedef struct _TRANSMIT_DESCRIPTOR
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{
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ULONG TBADR; /* transmit buffer address */
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USHORT BCNT; /* two's compliment buffer byte count - OR with 0xf000 */
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USHORT FLAGS; /* flags */
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USHORT TRC; /* transmit retry count (AND with 0x000f */
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USHORT FLAGS2; /* more flags */
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ULONG RES; /* reserved */
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} TRANSMIT_DESCRIPTOR, *PTRANSMIT_DESCRIPTOR;
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/* transmit descriptor flags */
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#define TD1_BPE 0x80 /* bus parity error */
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#define TD1_ENP 0x100 /* end of packet */
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#define TD1_STP 0x200 /* start of packet */
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#define TD1_DEF 0x400 /* frame transmission deferred */
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#define TD1_ONE 0x800 /* exactly one retry was needed for transmission */
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#define TD1_MORE 0x1000 /* more than 1 transmission retry required - same as LTINT */
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#define TD1_LTINT 0x1000 /* suppress transmit success interrupt - same as MORE */
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#define TD1_ADD_FCS 0x2000 /* force fcs generation - same as NO_FCS */
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#define TD1_NO_FCS 0x2000 /* prevent fcs generation - same as ADD_FCS */
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#define TD1_ERR 0x4000 /* an error bit is set */
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#define TD1_OWN 0x8000 /* buffer ownership */
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/* transmit descriptor flags2 flags */
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#define TD2_RTRY 0x400 /* retry error */
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#define TD2_LCAR 0x800 /* loss of carrier */
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#define TD2_LCOL 0x1000 /* late collision */
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#define TD2_EXDEF 0x2000 /* excessive deferral */
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#define TD2_UFLO 0x4000 /* buffer underflow */
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#define TD2_BUFF 0x8000 /* buffer error */
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