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![Vadim Galyant](/assets/img/avatar_default.png)
CORE-17359 Co-authored-by: Stanislav Motylkov <x86corez@gmail.com> Co-authored-by: Oleg Dubinskiy <oleg.dubinskij2013@yandex.ua>
125 lines
4.2 KiB
C
125 lines
4.2 KiB
C
/*
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* PROJECT: ReactOS HAL
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* LICENSE: GPL - See COPYING in the top level directory
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* FILE: hal/halx86/generic/sysinfo.c
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* PURPOSE: HAL Information Routines
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* PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org)
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* Vadim Galyant (vgal@rambler.ru)
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*/
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/* INCLUDES *******************************************************************/
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#include <hal.h>
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#define NDEBUG
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#include <debug.h>
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HAL_AMLI_BAD_IO_ADDRESS_LIST HalALMIBadIOAddressList[] =
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{
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{ 0x0000, 0x10, 1, NULL }, // DMA controller
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{ 0x0020, 0x02, 0, NULL }, // Programmable Interrupt Controller (8259A)
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{ 0x0040, 0x04, 1, NULL }, // System Timer 1
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{ 0x0048, 0x04, 1, NULL }, // System Timer 2 failsafe
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{ 0x0070, 0x02, 1, NULL }, // Real-time clock
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{ 0x0074, 0x03, 1, NULL }, // Extended CMOS
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{ 0x0081, 0x03, 1, NULL }, // DMA 1 page registers
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{ 0x0087, 0x01, 1, NULL }, // DMA 1 Ch 0 low page
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{ 0x0089, 0x01, 1, NULL }, // DMA 2 page registers
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{ 0x008A, 0x02, 1, NULL }, // DMA 2 page registers
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{ 0x008F, 0x01, 1, NULL }, // DMA 2 low page refresh
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{ 0x0090, 0x02, 1, NULL }, // Arbitration control
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{ 0x0093, 0x02, 1, NULL }, // Reserved system board setup
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{ 0x0096, 0x02, 1, NULL }, // POS channel select
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{ 0x00A0, 0x02, 0, NULL }, // Cascaded PIC
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{ 0x00C0, 0x20, 1, NULL }, // ISA DMA
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{ 0x04D0, 0x02, 0, NULL }, // PIC edge/level registers
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{ 0x0CF8, 0x08, 1, &HaliHandlePCIConfigSpaceAccess }, // PCI configuration space
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{ 0x0000, 0x00, 0, NULL } // Reserved
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};
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/* FUNCTIONS ******************************************************************/
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NTSTATUS
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NTAPI
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HaliHandlePCIConfigSpaceAccess(_In_ BOOLEAN IsRead,
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_In_ ULONG Port,
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_In_ ULONG Length,
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_Inout_ PULONG Buffer)
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{
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DPRINT1("HaliHandlePCIConfigSpaceAccess: IsRead %X, Port 0x%X, Length %u, Buffer %p\n", IsRead, Port, Length, Buffer);
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//ASSERT(FALSE);
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return STATUS_NOT_IMPLEMENTED;
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}
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NTSTATUS
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NTAPI
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HaliQuerySystemInformation(IN HAL_QUERY_INFORMATION_CLASS InformationClass,
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IN ULONG BufferSize,
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IN OUT PVOID Buffer,
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OUT PULONG ReturnedLength)
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{
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#define REPORT_THIS_CASE(X) case X: DPRINT1("Unhandled case: %s\n", #X); break
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switch (InformationClass)
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{
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REPORT_THIS_CASE(HalInstalledBusInformation);
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REPORT_THIS_CASE(HalProfileSourceInformation);
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REPORT_THIS_CASE(HalInformationClassUnused1);
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REPORT_THIS_CASE(HalPowerInformation);
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REPORT_THIS_CASE(HalProcessorSpeedInformation);
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REPORT_THIS_CASE(HalCallbackInformation);
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REPORT_THIS_CASE(HalMapRegisterInformation);
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REPORT_THIS_CASE(HalMcaLogInformation);
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case HalFrameBufferCachingInformation:
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{
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/* FIXME: TODO */
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return STATUS_NOT_IMPLEMENTED;
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}
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REPORT_THIS_CASE(HalDisplayBiosInformation);
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REPORT_THIS_CASE(HalProcessorFeatureInformation);
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REPORT_THIS_CASE(HalNumaTopologyInterface);
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REPORT_THIS_CASE(HalErrorInformation);
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REPORT_THIS_CASE(HalCmcLogInformation);
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REPORT_THIS_CASE(HalCpeLogInformation);
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REPORT_THIS_CASE(HalQueryMcaInterface);
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case HalQueryAMLIIllegalIOPortAddresses:
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{
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ULONG Size = sizeof(HalALMIBadIOAddressList);
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NTSTATUS Status = STATUS_INFO_LENGTH_MISMATCH;
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if (BufferSize >= Size)
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{
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RtlCopyMemory(Buffer, HalALMIBadIOAddressList, Size);
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Status = STATUS_SUCCESS;
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}
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*ReturnedLength = Size;
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KeFlushWriteBuffer();
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return Status;
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}
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REPORT_THIS_CASE(HalQueryMaxHotPlugMemoryAddress);
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REPORT_THIS_CASE(HalPartitionIpiInterface);
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REPORT_THIS_CASE(HalPlatformInformation);
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REPORT_THIS_CASE(HalQueryProfileSourceList);
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REPORT_THIS_CASE(HalInitLogInformation);
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REPORT_THIS_CASE(HalFrequencyInformation);
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REPORT_THIS_CASE(HalProcessorBrandString);
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REPORT_THIS_CASE(HalHypervisorInformation);
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REPORT_THIS_CASE(HalPlatformTimerInformation);
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REPORT_THIS_CASE(HalAcpiAuditInformation);
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}
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#undef REPORT_THIS_CASE
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UNIMPLEMENTED;
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return STATUS_NOT_IMPLEMENTED;
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}
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NTSTATUS
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NTAPI
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HaliSetSystemInformation(IN HAL_SET_INFORMATION_CLASS InformationClass,
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IN ULONG BufferSize,
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IN OUT PVOID Buffer)
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{
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UNIMPLEMENTED;
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return STATUS_NOT_IMPLEMENTED;
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}
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