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https://github.com/reactos/reactos.git
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346 lines
10 KiB
C
346 lines
10 KiB
C
/*
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* PROJECT: ReactOS Kernel
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* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
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* PURPOSE: Header file for APIC hal
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* COPYRIGHT: Copyright 2011 Timo Kreuzer <timo.kreuzer@reactos.org>
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* Copyright 2021 Justin Miller <justinmiller100@gmail.com>
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*/
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#pragma once
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#ifdef _M_AMD64
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#define LOCAL_APIC_BASE 0xFFFFFFFFFFFE0000ULL
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#define IOAPIC_BASE 0xFFFFFFFFFFFE1000ULL
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/* Vectors */
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#define APC_VECTOR 0x1F // IRQL 01 (APC_LEVEL) - KiApcInterrupt
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#define DISPATCH_VECTOR 0x2F // IRQL 02 (DISPATCH_LEVEL) - KiDpcInterrupt
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#define CMCI_VECTOR 0x35 // IRQL 05 (CMCI_LEVEL) - HalpInterruptCmciService
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#define APIC_CLOCK_VECTOR 0xD1 // IRQL 13 (CLOCK_LEVEL), IRQ 8 - HalpTimerClockInterrupt
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#define CLOCK_IPI_VECTOR 0xD2 // IRQL 13 (CLOCK_LEVEL) - HalpTimerClockIpiRoutine
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#define REBOOT_VECTOR 0xD7 // IRQL 15 (PROFILE_LEVEL) - HalpInterruptRebootService
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#define STUB_VECTOR 0xD8 // IRQL 15 (PROFILE_LEVEL) - HalpInterruptStubService
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#define APIC_SPURIOUS_VECTOR 0xDF // IRQL 13 (CLOCK_LEVEL) - HalpInterruptSpuriousService
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#define APIC_IPI_VECTOR 0xE1 // IRQL 14 (IPI_LEVEL) - KiIpiInterrupt
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#define APIC_ERROR_VECTOR 0xE2 // IRQL 14 (IPI_LEVEL) - HalpInterruptLocalErrorService
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#define POWERFAIL_VECTOR 0xE3 // IRQL 14 (POWER_LEVEL) : HalpInterruptDeferredRecoveryService
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#define APIC_PROFILE_VECTOR 0xFD // IRQL 15 (PROFILE_LEVEL) - HalpTimerProfileInterrupt
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#define APIC_PERF_VECTOR 0xFE // IRQL 15 (PROFILE_LEVEL) - HalpPerfInterrupt
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#define APIC_NMI_VECTOR 0xFF
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#define IrqlToTpr(Irql) (Irql << 4)
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#define IrqlToSoftVector(Irql) ((Irql << 4)|0xf)
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#define TprToIrql(Tpr) ((KIRQL)(Tpr >> 4))
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#define CLOCK2_LEVEL CLOCK_LEVEL
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#else
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#define LOCAL_APIC_BASE 0xFFFE0000
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#define IOAPIC_BASE 0xFFFE1000
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/* Vectors */
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#define APIC_SPURIOUS_VECTOR 0x1f
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#define APC_VECTOR 0x3D // IRQL 01
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#define DISPATCH_VECTOR 0x41 // IRQL 02
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#define APIC_GENERIC_VECTOR 0xC1 // IRQL 27
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#define APIC_CLOCK_VECTOR 0xD1 // IRQL 28
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#define APIC_SYNCH_VECTOR 0xD1 // IRQL 28
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#define APIC_IPI_VECTOR 0xE1 // IRQL 29
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#define APIC_ERROR_VECTOR 0xE3
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#define POWERFAIL_VECTOR 0xEF // IRQL 30
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#define APIC_PROFILE_VECTOR 0xFD // IRQL 31
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#define APIC_PERF_VECTOR 0xFE
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#define APIC_NMI_VECTOR 0xFF
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#define IrqlToTpr(Irql) (HalpIRQLtoTPR[Irql])
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#define IrqlToSoftVector(Irql) IrqlToTpr(Irql)
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#define TprToIrql(Tpr) (HalVectorToIRQL[Tpr >> 4])
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#endif
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#define APIC_MAX_IRQ 24
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#define APIC_FREE_VECTOR 0xFF
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#define APIC_RESERVED_VECTOR 0xFE
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/* The IMCR is supported by two read/writable or write-only I/O ports,
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22h and 23h, which receive address and data respectively.
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To access the IMCR, write a value of 70h to I/O port 22h, which selects the IMCR.
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Then write the data to I/O port 23h. The power-on default value is zero,
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which connects the NMI and 8259 INTR lines directly to the BSP.
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Writing a value of 01h forces the NMI and 8259 INTR signals to pass through the APIC.
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*/
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#define IMCR_ADDRESS_PORT (PUCHAR)0x0022
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#define IMCR_DATA_PORT (PUCHAR)0x0023
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#define IMCR_SELECT 0x70
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#define IMCR_PIC_DIRECT 0x00
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#define IMCR_PIC_VIA_APIC 0x01
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/* APIC Register Address Map */
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typedef enum _APIC_REGISTER
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{
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APIC_ID = 0x0020, /* Local APIC ID Register (R/W) */
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APIC_VER = 0x0030, /* Local APIC Version Register (R) */
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APIC_TPR = 0x0080, /* Task Priority Register (R/W) */
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APIC_APR = 0x0090, /* Arbitration Priority Register (R) */
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APIC_PPR = 0x00A0, /* Processor Priority Register (R) */
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APIC_EOI = 0x00B0, /* EOI Register (W) */
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APIC_RRR = 0x00C0, /* Remote Read Register () */
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APIC_LDR = 0x00D0, /* Logical Destination Register (R/W) */
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APIC_DFR = 0x00E0, /* Destination Format Register (0-27 R, 28-31 R/W) */
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APIC_SIVR = 0x00F0, /* Spurious Interrupt Vector Register (0-3 R, 4-9 R/W) */
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APIC_ISR = 0x0100, /* Interrupt Service Register 0-255 (R) */
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APIC_TMR = 0x0180, /* Trigger Mode Register 0-255 (R) */
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APIC_IRR = 0x0200, /* Interrupt Request Register 0-255 (r) */
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APIC_ESR = 0x0280, /* Error Status Register (R) */
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APIC_ICR0 = 0x0300, /* Interrupt Command Register 0-31 (R/W) */
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APIC_ICR1 = 0x0310, /* Interrupt Command Register 32-63 (R/W) */
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APIC_TMRLVTR = 0x0320, /* Timer Local Vector Table (R/W) */
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APIC_THRMLVTR = 0x0330, /* Thermal Local Vector Table */
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APIC_PCLVTR = 0x0340, /* Performance Counter Local Vector Table (R/W) */
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APIC_LINT0 = 0x0350, /* LINT0 Local Vector Table (R/W) */
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APIC_LINT1 = 0x0360, /* LINT1 Local Vector Table (R/W) */
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APIC_ERRLVTR = 0x0370, /* Error Local Vector Table (R/W) */
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APIC_TICR = 0x0380, /* Initial Count Register for Timer (R/W) */
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APIC_TCCR = 0x0390, /* Current Count Register for Timer (R) */
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APIC_TDCR = 0x03E0, /* Timer Divide Configuration Register (R/W) */
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APIC_EAFR = 0x0400, /* extended APIC Feature register (R/W) */
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APIC_EACR = 0x0410, /* Extended APIC Control Register (R/W) */
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APIC_SEOI = 0x0420, /* Specific End Of Interrupt Register (W) */
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APIC_EXT0LVTR = 0x0500, /* Extended Interrupt 0 Local Vector Table */
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APIC_EXT1LVTR = 0x0510, /* Extended Interrupt 1 Local Vector Table */
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APIC_EXT2LVTR = 0x0520, /* Extended Interrupt 2 Local Vector Table */
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APIC_EXT3LVTR = 0x0530 /* Extended Interrupt 3 Local Vector Table */
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} APIC_REGISTER;
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#define MSR_APIC_BASE 0x0000001B
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#define IOAPIC_PHYS_BASE 0xFEC00000
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#define APIC_CLOCK_INDEX 8
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#define ApicLogicalId(Cpu) ((UCHAR)(1<< Cpu))
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/* The following definitions are based on AMD documentation.
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They differ slightly in Intel documentation. */
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/* Message Type (Intel: "Delivery Mode") */
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typedef enum _APIC_MT
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{
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APIC_MT_Fixed = 0,
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APIC_MT_LowestPriority = 1,
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APIC_MT_SMI = 2,
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APIC_MT_RemoteRead = 3,
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APIC_MT_NMI = 4,
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APIC_MT_INIT = 5,
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APIC_MT_Startup = 6,
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APIC_MT_ExtInt = 7,
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} APIC_MT;
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/* Trigger Mode */
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typedef enum _APIC_TGM
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{
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APIC_TGM_Edge,
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APIC_TGM_Level
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} APIC_TGM;
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/* Destination Mode */
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typedef enum _APIC_DM
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{
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APIC_DM_Physical,
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APIC_DM_Logical
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} APIC_DM;
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/* Destination Short Hand */
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typedef enum _APIC_DSH
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{
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APIC_DSH_Destination,
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APIC_DSH_Self,
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APIC_DSH_AllIncludingSelf,
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APIC_DSH_AllExclusingSelf
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} APIC_DSH;
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/* Write Constants */
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typedef enum _APIC_DF
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{
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APIC_DF_Flat = 0xFFFFFFFF,
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APIC_DF_Cluster = 0x0FFFFFFF
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} APIC_DF;
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/* Remote Read Status */
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typedef enum _APIC_RRS
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{
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APIC_RRS_Invalid = 0,
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APIC_RRS_Pending = 1,
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APIC_RRS_Done = 2
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} APIC_RRS;
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/* Timer Constants */
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enum _TIMER_DV
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{
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TIMER_DV_DivideBy2 = 0,
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TIMER_DV_DivideBy4 = 1,
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TIMER_DV_DivideBy8 = 2,
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TIMER_DV_DivideBy16 = 3,
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TIMER_DV_DivideBy32 = 8,
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TIMER_DV_DivideBy64 = 9,
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TIMER_DV_DivideBy128 = 10,
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TIMER_DV_DivideBy1 = 11,
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} TIMER_DV;
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#include <pshpack1.h>
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typedef union _APIC_BASE_ADRESS_REGISTER
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{
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UINT64 LongLong;
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struct
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{
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UINT64 Reserved1:8;
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UINT64 BootStrapCPUCore:1;
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UINT64 Reserved2:2;
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UINT64 Enable:1;
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UINT64 BaseAddress:40;
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UINT64 ReservedMBZ:12;
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};
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} APIC_BASE_ADRESS_REGISTER;
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typedef union _APIC_SPURIOUS_INERRUPT_REGISTER
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{
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UINT32 Long;
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struct
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{
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UINT32 Vector:8;
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UINT32 SoftwareEnable:1;
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UINT32 FocusCPUCoreChecking:1;
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UINT32 ReservedMBZ:22;
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};
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} APIC_SPURIOUS_INERRUPT_REGISTER;
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typedef union _APIC_VERSION_REGISTER
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{
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UINT32 Long;
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struct
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{
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UINT32 Version:8;
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UINT32 ReservedMBZ:8;
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UINT32 MaxLVT:8;
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UINT32 ReservedMBZ1:7;
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UINT32 ExtRegSpacePresent:1;
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};
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} APIC_VERSION_REGISTER;
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typedef union _APIC_EXTENDED_CONTROL_REGISTER
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{
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UINT32 Long;
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struct
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{
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UINT32 Version:1;
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UINT32 SEOIEnable:1;
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UINT32 ExtApicIdEnable:1;
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UINT32 ReservedMBZ:29;
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};
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} APIC_EXTENDED_CONTROL_REGISTER;
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typedef union _APIC_INTERRUPT_COMMAND_REGISTER
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{
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UINT64 LongLong;
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struct
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{
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UINT32 Long0;
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UINT32 Long1;
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};
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struct
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{
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UINT64 Vector:8;
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UINT64 MessageType:3;
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UINT64 DestinationMode:1;
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UINT64 DeliveryStatus:1;
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UINT64 ReservedMBZ:1;
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UINT64 Level:1;
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UINT64 TriggerMode:1;
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UINT64 RemoteReadStatus:2; /* Intel: Reserved */
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UINT64 DestinationShortHand:2;
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UINT64 Reserved2MBZ:36;
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UINT64 Destination:8;
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};
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} APIC_INTERRUPT_COMMAND_REGISTER;
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typedef union _LVT_REGISTER
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{
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UINT32 Long;
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struct
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{
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UINT32 Vector:8;
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UINT32 MessageType:3;
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UINT32 ReservedMBZ:1;
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UINT32 DeliveryStatus:1;
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UINT32 Reserved1MBZ:1;
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UINT32 RemoteIRR:1;
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UINT32 TriggerMode:1;
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UINT32 Mask:1;
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UINT32 TimerMode:1;
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UINT32 Reserved2MBZ:13;
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};
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} LVT_REGISTER;
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/* IOAPIC offsets */
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enum
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{
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IOAPIC_IOREGSEL = 0x00,
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IOAPIC_IOWIN = 0x10
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};
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/* IOAPIC Constants */
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enum
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{
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IOAPIC_ID = 0x00,
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IOAPIC_VER = 0x01,
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IOAPIC_ARB = 0x02,
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IOAPIC_REDTBL = 0x10
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};
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typedef union _IOAPIC_REDIRECTION_REGISTER
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{
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UINT64 LongLong;
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struct
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{
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UINT32 Long0;
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UINT32 Long1;
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};
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struct
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{
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UINT64 Vector:8;
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UINT64 DeliveryMode:3;
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UINT64 DestinationMode:1;
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UINT64 DeliveryStatus:1;
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UINT64 Polarity:1;
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UINT64 RemoteIRR:1;
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UINT64 TriggerMode:1;
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UINT64 Mask:1;
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UINT64 Reserved:39;
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UINT64 Destination:8;
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};
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} IOAPIC_REDIRECTION_REGISTER;
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#include <poppack.h>
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FORCEINLINE
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ULONG
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ApicRead(APIC_REGISTER Register)
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{
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return READ_REGISTER_ULONG((PULONG)(APIC_BASE + Register));
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}
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FORCEINLINE
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VOID
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ApicWrite(APIC_REGISTER Register, ULONG Value)
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{
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WRITE_REGISTER_ULONG((PULONG)(APIC_BASE + Register), Value);
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}
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VOID
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NTAPI
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ApicInitializeTimer(ULONG Cpu);
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VOID
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NTAPI
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HalInitializeProfiling(VOID);
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VOID
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NTAPI
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HalpInitApicInfo(IN PLOADER_PARAMETER_BLOCK KeLoaderBlock);
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VOID __cdecl ApicSpuriousService(VOID);
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