mirror of
https://github.com/reactos/reactos.git
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208 lines
7.7 KiB
C
208 lines
7.7 KiB
C
/*
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*
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*/
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#pragma once
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#define APIC_DEFAULT_BASE 0xFEE00000 /* Default Local APIC Base Register Address */
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/* APIC Register Address Map */
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#define APIC_ID 0x0020 /* Local APIC ID Register (R/W) */
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#define APIC_VER 0x0030 /* Local APIC Version Register (R) */
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#define APIC_TPR 0x0080 /* Task Priority Register (R/W) */
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#define APIC_APR 0x0090 /* Arbitration Priority Register (R) */
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#define APIC_PPR 0x00A0 /* Processor Priority Register (R) */
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#define APIC_EOI 0x00B0 /* EOI Register (W) */
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#define APIC_LDR 0x00D0 /* Logical Destination Register (R/W) */
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#define APIC_DFR 0x00E0 /* Destination Format Register (0-27 R, 28-31 R/W) */
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#define APIC_SIVR 0x00F0 /* Spurious Interrupt Vector Register (0-3 R, 4-9 R/W) */
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#define APIC_ISR 0x0100 /* Interrupt Service Register 0-255 (R) */
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#define APIC_TMR 0x0180 /* Trigger Mode Register 0-255 (R) */
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#define APIC_IRR 0x0200 /* Interrupt Request Register 0-255 (r) */
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#define APIC_ESR 0x0280 /* Error Status Register (R) */
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#define APIC_ICR0 0x0300 /* Interrupt Command Register 0-31 (R/W) */
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#define APIC_ICR1 0x0310 /* Interrupt Command Register 32-63 (R/W) */
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#define APIC_LVTT 0x0320 /* Local Vector Table (Timer) (R/W) */
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#define APIC_LVTTHMR 0x0330
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#define APIC_LVTPC 0x0340 /* Performance Counter LVT (R/W) */
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#define APIC_LINT0 0x0350 /* Local Vector Table (LINT0) (R/W) */
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#define APIC_LINT1 0x0360 /* Local Vector Table (LINT1) (R/W) */
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#define APIC_LVT3 0x0370 /* Local Vector Table (Error) (R/W) */
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#define APIC_ICRT 0x0380 /* Initial Count Register for Timer (R/W) */
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#define APIC_CCRT 0x0390 /* Current Count Register for Timer (R) */
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#define APIC_TDCR 0x03E0 /* Timer Divide Configuration Register (R/W) */
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#define APIC_ID_MASK (0xF << 24)
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#define GET_APIC_ID(x) (((x) & APIC_ID_MASK) >> 24)
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#define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF)
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#define APIC_VER_MASK 0xFF00FF
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#define GET_APIC_VERSION(x) ((x) & 0xFF)
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#define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFF)
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#define APIC_TPR_PRI 0xFF
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#define APIC_TPR_INT 0xF0
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#define APIC_TPR_SUB 0xF
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#define APIC_TPR_MAX 0xFF /* Maximum priority */
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#define APIC_TPR_MIN 0x20 /* Minimum priority */
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#define APIC_LDR_MASK (0xFF << 24)
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#define APIC_SIVR_ENABLE (0x1 << 8)
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#define APIC_SIVR_FOCUS (0x1 << 9)
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#define APIC_ESR_MASK (0xFE << 0) /* Error Mask */
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#define APIC_ICR0_VECTOR (0xFF << 0) /* Vector */
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#define APIC_ICR0_DM (0x7 << 8) /* Delivery Mode */
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#define APIC_ICR0_DESTM (0x1 << 11) /* Destination Mode */
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#define APIC_ICR0_DS (0x1 << 12) /* Delivery Status */
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#define APIC_ICR0_LEVEL (0x1 << 14) /* Level */
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#define APIC_ICR0_TM (0x1 << 15) /* Trigger Mode */
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#define APIC_ICR0_DESTS (0x3 << 18) /* Destination Shorthand */
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/* Delivery Modes */
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#define APIC_DM_FIXED (0x0 << 8)
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#define APIC_DM_LOWEST (0x1 << 8)
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#define APIC_DM_SMI (0x2 << 8)
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#define APIC_DM_REMRD (0x3 << 8)
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#define APIC_DM_NMI (0x4 << 8)
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#define APIC_DM_INIT (0x5 << 8)
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#define APIC_DM_STARTUP (0x6 << 8)
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#define APIC_DM_EXTINT (0x7 << 8)
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#define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
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#define SET_APIC_DELIVERY_MODE(x,y) (((x) & ~0x700) | ((y) << 8))
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/* Destination Shorthand values */
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#define APIC_ICR0_DESTS_FIELD (0x0 << 0)
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#define APIC_ICR0_DESTS_SELF (0x1 << 18)
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#define APIC_ICR0_DESTS_ALL (0x2 << 18)
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#define APIC_ICR0_DESTS_ALL_BUT_SELF (0x3 << 18)
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#define APIC_ICR0_LEVEL_DEASSERT (0x0 << 14) /* Deassert level */
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#define APIC_ICR0_LEVEL_ASSERT (0x1 << 14) /* Assert level */
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#define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
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#define SET_APIC_DEST_FIELD(x) (((x) & 0xFF) << 24)
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#define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
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#define SET_APIC_TIMER_BASE(x) ((x) << 18)
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#define APIC_TIMER_BASE_CLKIN 0x0
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#define APIC_TIMER_BASE_TMBASE 0x1
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#define APIC_TIMER_BASE_DIV 0x2
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#define APIC_LVT_VECTOR (0xFF << 0) /* Vector */
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#define APIC_LVT_DS (0x1 << 12) /* Delivery Status */
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#define APIC_LVT_REMOTE_IRR (0x1 << 14) /* Remote IRR */
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#define APIC_LVT_LEVEL_TRIGGER (0x1 << 15) /* Lvel Triggered */
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#define APIC_LVT_MASKED (0x1 << 16) /* Mask */
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#define APIC_LVT_PERIODIC (0x1 << 17) /* Timer Mode */
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#define APIC_LVT3_DM (0x7 << 8)
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#define APIC_LVT3_IIPP (0x1 << 13)
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#define APIC_LVT3_TM (0x1 << 15)
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#define APIC_LVT3_MASKED (0x1 << 16)
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#define APIC_LVT3_OS (0x1 << 17)
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#define APIC_TDCR_TMBASE (0x1 << 2)
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#define APIC_TDCR_MASK 0x0F
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#define APIC_TDCR_2 0x00
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#define APIC_TDCR_4 0x01
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#define APIC_TDCR_8 0x02
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#define APIC_TDCR_16 0x03
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#define APIC_TDCR_32 0x08
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#define APIC_TDCR_64 0x09
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#define APIC_TDCR_128 0x0A
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#define APIC_TDCR_1 0x0B
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#define APIC_LVT_VECTOR (0xFF << 0) /* Vector */
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#define APIC_LVT_DS (0x1 << 12) /* Delivery Status */
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#define APIC_LVT_REMOTE_IRR (0x1 << 14) /* Remote IRR */
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#define APIC_LVT_LEVEL_TRIGGER (0x1 << 15) /* Lvel Triggered */
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#define APIC_LVT_MASKED (0x1 << 16) /* Mask */
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#define APIC_LVT_PERIODIC (0x1 << 17) /* Timer Mode */
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#define APIC_LVT3_DM (0x7 << 8)
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#define APIC_LVT3_IIPP (0x1 << 13)
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#define APIC_LVT3_TM (0x1 << 15)
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#define APIC_LVT3_MASKED (0x1 << 16)
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#define APIC_LVT3_OS (0x1 << 17)
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#define APIC_TDCR_TMBASE (0x1 << 2)
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#define APIC_TDCR_MASK 0x0F
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#define APIC_TDCR_2 0x00
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#define APIC_TDCR_4 0x01
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#define APIC_TDCR_8 0x02
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#define APIC_TDCR_16 0x03
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#define APIC_TDCR_32 0x08
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#define APIC_TDCR_64 0x09
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#define APIC_TDCR_128 0x0A
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#define APIC_TDCR_1 0x0B
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#define APIC_TARGET_SELF 0x100
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#define APIC_TARGET_ALL 0x200
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#define APIC_TARGET_ALL_BUT_SELF 0x300
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#define APIC_INTEGRATED(version) (version & 0xF0)
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typedef enum {
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amPIC = 0, /* IMCR and PIC compatibility mode */
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amVWIRE /* Virtual Wire compatibility mode */
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} APIC_MODE;
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#ifdef CONFIG_SMP
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#define MAX_CPU 32
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#else
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#define MAX_CPU 1
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#endif
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/*
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* Local APIC timer IRQ vector is on a different priority level,
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* to work around the 'lost local interrupt if more than 2 IRQ
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* sources per level' errata.
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*/
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#define LOCAL_TIMER_VECTOR 0xEF
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#define IPI_VECTOR 0xFB
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#define ERROR_VECTOR 0xFE
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#define SPURIOUS_VECTOR 0xFF /* Must be 0xXF */
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/* CPU flags */
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#define CPU_USABLE 0x01 /* 1 if the CPU is usable (ie. can be used) */
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#define CPU_ENABLED 0x02 /* 1 if the CPU is enabled */
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#define CPU_BSP 0x04 /* 1 if the CPU is the bootstrap processor */
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#define CPU_TSC 0x08 /* 1 if the CPU has a time stamp counter */
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typedef struct _CPU_INFO
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{
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UCHAR Flags; /* CPU flags */
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UCHAR APICId; /* Local APIC ID */
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UCHAR APICVersion; /* Local APIC version */
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// UCHAR MaxLVT; /* Number of LVT registers */
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ULONG BusSpeed; /* BUS speed */
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ULONG CoreSpeed; /* Core speed */
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UCHAR Padding[16-12]; /* Padding to 16-byte */
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} CPU_INFO, *PCPU_INFO;
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extern ULONG CPUCount; /* Total number of CPUs */
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extern ULONG BootCPU; /* Bootstrap processor */
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extern ULONG OnlineCPUs; /* Bitmask of online CPUs */
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extern CPU_INFO CPUMap[MAX_CPU]; /* Map of all CPUs in the system */
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/* Prototypes */
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__inline VOID APICWrite(ULONG Offset, ULONG Value);
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__inline ULONG APICRead(ULONG Offset);
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VOID APICSendIPI(ULONG Target, ULONG Mode);
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VOID APICSetup(VOID);
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VOID HaliInitBSP(VOID);
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VOID APICSyncArbIDs(VOID);
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__inline VOID APICSendEOI(VOID);
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VOID APICCalibrateTimer(ULONG CPU);
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VOID HaliStartApplicationProcessor(ULONG Cpu, ULONG Stack);
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static __inline ULONG ThisCPU(VOID)
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{
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return (APICRead(APIC_ID) & APIC_ID_MASK) >> 24;
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}
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/* EOF */
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