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58 lines
2.3 KiB
ArmAsm
58 lines
2.3 KiB
ArmAsm
/*
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* PROJECT: ReactOS HAL
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* LICENSE: GPL - See COPYING in the top level directory
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* FILE: hal/halarm/generic/cache.S
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* PURPOSE: Implements cache clean, invalidate routines for ARM machines
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* PROGRAMMERS: Copyright (C) 2005 ARM Ltd.
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*/
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.title "ARM HAL Cache Routines"
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.include "ntoskrnl/include/internal/arm/kxarm.h"
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.include "ntoskrnl/include/internal/arm/ksarm.h"
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NESTED_ENTRY v7_flush_dcache_all
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PROLOG_END v7_flush_dcache_all
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mrc p15, 1, r0, c0, c0, 1 // read clidr
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ands r3, r0, #0x7000000 // extract loc from clidr
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mov r3, r3, lsr #23 // left align loc bit field
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beq finished // if loc is 0, then no need to clean
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mov r10, #0 // start clean at cache level 0
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loop1:
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add r2, r10, r10, lsr #1 // work out 3x current cache level
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mov r1, r0, lsr r2 // extract cache type bits from clidr
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and r1, r1, #7 // mask of the bits for current cache only
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cmp r1, #2 // see what cache we have at this level
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blt skip // skip if no cache, or just i-cache
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mcr p15, 2, r10, c0, c0, 0 // select current cache level in cssr
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isb // isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 // read the new csidr
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and r2, r1, #7 // extract the length of the cache lines
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add r2, r2, #4 // add 4 (line length offset)
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 // find maximum number on the way size
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clz r5, r4 // find bit position of way size increment
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 // extract max number of the index size
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loop2:
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mov r9, r4 // create working copy of max way size
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loop3:
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orr r11, r10, r9, lsl r5 // factor way and cache number into r11
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orr r11, r11, r7, lsl r2 // factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 // clean & invalidate by set/way
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subs r9, r9, #1 // decrement the way
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bge loop3
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subs r7, r7, #1 // decrement the index
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bge loop2
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skip:
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add r10, r10, #2 // increment cache number
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cmp r3, r10
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bgt loop1
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finished:
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mov r10, #0 // swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 // select current cache level in cssr
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isb
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mov pc, lr
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ENTRY_END v7_flush_dcache_all
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