Modularize linear memory access by adding two new functions:
Fast486ReadLinearMemory and Fast486WriteLinearMemory.
Implement Fast486GetPageTableEntry.
svn path=/branches/ntvdm/; revision=60923
The number of bit places in a shift operation is ANDed by the width of the type
when it is in a register, so (1 << c), when c is 32, is actually 1, and not 0.
Fix the calculation of MaxValue by using SignFlag | (SignFlag - 1) instead.
svn path=/branches/ntvdm/; revision=60912
Don't enable interrupts unless it's necessary in the interrupt handler.
[FAST486]
When handling interrupt signals, make sure at least one instruction is executed,
to prevent the CPU from being completely blocked by interrupt signals.
svn path=/branches/ntvdm/; revision=60910
The behavior of the I/O port bus depends on the data width. In the case
of 16-bit/32-bit access, two/four adjacent ports will be accessed.
svn path=/branches/ntvdm/; revision=60891
Fix segment initialization. The cached descriptors must have valid values
during the switch to protected mode.
For some odd reason, GCC makes the FAST486_GDT_ENTRY structure 12 bytes
instead of 8 if there is a bit field with more than 16 bits, so split
the Base field into Base and BaseMid.
Add size checks below important structure declarations.
svn path=/branches/ntvdm/; revision=60825
Implement opcode group 0x0F, 0x01 (SGDT, SIDT, LGDT, LIDT, SMSW and LMSW).
Only INVLPG is not implemented yet.
svn path=/branches/ntvdm/; revision=60824
Fix the type of a variable.
[NTVDM]
Introduce a BOP handler table for the 256 possible BOP functions and use it.
svn path=/branches/ntvdm/; revision=60818
- Introduce a Fast486Initialize which is used to set up the CPU callbacks (and use default ones if some of the given callbacks are NULL), and to reset it the first time. Now Fast486Reset is meant to be used for only resetting the CPU to a safe state.
- Hence we are now sure that State->WhateverCallback is never NULL (and is theoretically valid), so don't do NULL-checks when calling them, but call them directly. The default cases for those checks become the default calls for the default callbacks.
- Remove the now-unneeded EmulatorIdle function.
svn path=/branches/ntvdm/; revision=60814
In real mode, the value in the IVT is a far pointer, not an IDT entry.
Fix the case when MemReadCallback is NULL.
svn path=/branches/ntvdm/; revision=60813
BOP numbers are 1 byte and map to a function (over 255). But one can pass additional "parameters" to those functions by adding extra bytes, however such functions must advance "by hand" the instruction pointer.
[NTVDM]
- Take into account our previous remark for the BIOS interrupt stubs, and comment them.
- Rework EmulatorBiosOperation (move almost all of its existing code into subfunctions in bop.c) so that one can call many other BOP functions in the future (WIP). The BOP number (still called) EMULATOR_INT_BOP (of value 0xFF) is used for internal 16 --> 32 bit switching for our 32bit bios.
- It appears that the IoRead/WriteCallback and IdleCallback must not be NULL for using fast486. I'm committing a temporary fix that I will definitely fix in a subsequent commit.
svn path=/branches/ntvdm/; revision=60812
- Remove an unneeded inclusion to the CRT header: limits.h (and use instead NDK definitions for max/min long values).
- Remove unneeded comments...
[NTVDM]
Remove an unneeded add_dependencies(...) command.
svn path=/branches/ntvdm/; revision=60767
Separate external interrupts from interrupt signals (which are
interrupts whose number is not known until they can be serviced,
just like hardware interrupts on a real CPU).
[NTVDM]
Improve the PIC emulation code (IRQ priorities, etc...).
Instead of checking for interrupts in the main loop, move the
PS/2 input parsing to a different thread.
Improve BIOS keyboard IRQ handling.
svn path=/branches/ntvdm/; revision=60761
Implement the MOV instruction for control and debug registers.
Remove definitions for non-existant registers CR1, CR4, CR5, CR6 and CR7.
The standard 80486 doesn't have a CR4 register (although some implementations
of the 80486 had large page support and CR4, it was not reliable).
As for the debug registers, DR4 is the same as DR6, and DR5 is the same as DR7.
svn path=/branches/ntvdm/; revision=60747
