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Author SHA1 Message Date
Timo Kreuzer 9ea495ba33 Create a branch for header work. 
svn path=/branches/header-work/; revision=45691
 2010-02-26 22:57:55 +00:00
Sir Richard 02c2d27111 [ARM]: Fix the ARM build, hopefully without breaking the x86 build in the process. Sorry buds! 
svn path=/trunk/; revision=45368
 2010-02-01 03:51:45 +00:00
Sir Richard 4e16ca56ce [HAL]: Rewrite IRQL handling. Alex's original code (lately translated to C) was a copy of the MicroChannel (MCA), Checked-Build HAL, an unexplained choice considering MCA is not supported or even available anymore. Windows, on machines with a PIC, uses a mechanism called Lazy IRQL, in which the PIC is only programmed "lazily", meaning that lowering and raising the IRQL does not actually change the interrupt mask. Therefore, lower priority interrupts will still come in at high IRQL. At this point, the HAL will detect this, only now mask the PICs, and lie that the lower interrupt was "spurious", while setting a pending bit. When the IRQL is lowered, the bit is detected, and a software/delayed "INT" is done with the correct IRQ vector number. More details are available in the typical resources. 
[HAL]: Implement support for Level interrupts, which are used by certain EISA cards, and more particularly, all PCI hardware. Level interrupts were not previously handled correctly, being treated as edge/latched interrupts instead.
[NTOS/HAL]: Remove VDM Alert KPCR hack (which was buggy). Now the PKTRAP_FRAME is passed as a parameter to HalpEndSoftwareInterrupt/HalEndSystemInterrupt. This also removes the HalpNestedTrap ASM hack, since the call can now be done in C.
[PERF]: On real machines, writing the PIC mask is a relatively expensive I/O operation, and IRQL lower/raise can happen hundreds of times a second. Lazy IRQL provides an important optimization.
[PERF]: Correctly handling level interrupts as level interrupts allows for faster, and more efficient, IRQ handling.

svn path=/trunk/; revision=45320
 2010-01-29 21:10:33 +00:00
Sir Richard 4fa5e49fa3 [NTOS]: Return correct IRQ 0 vector instead of IRQL, when the timer interrupt ends. 
svn path=/trunk/; revision=45315
 2010-01-29 07:27:55 +00:00
Sir Richard 7509f62a3b [PERF]: Optimize nested interrupt cases (where a pending interrupt exists at the end of a software or system interrupt) just like the old HAL did, by jumping into a second-level handler and completing the outer trap frame instead of the nested trap frame. This saves a lot of cycles in those cases, and they do happen quite often (pending DPC at the end of an interrupt, for example). 
[NTOS/HAL]: Rework respective code to handle this by using the VDM Alert field in the KPCR.

svn path=/trunk/; revision=45301
 2010-01-28 20:45:45 +00:00
Sir Richard 49ca1be9f3 [HAL]: Implement the profile and clock interrupt trap/handlers in C instead of ASM. This allows the kernel to remove the ugly hacks based on internal knowledge of how the assembly/stack of the HAL is supposed to look like. Everything is now done through a clean C interface. 
[NTOS]: Remove said hacks and have a normal C implementation of KeUpdateSystemTime. It exits the interrupt through a soft interrupt exit.
[NTOS]: Implement 4 lines of support code needed to handle interrupts during V8086 mode, which were lacking since we weren't hitting this case yet.
Note that now the KeUpdateSystemTime interface is not "compatible" with Windows anymore. This does not matter, since the only possible caller of KeUpdateSystemTime is a very specific HAL routine that needs a very specific stack layout to actually work, so the chance of anyone calling this API is absolutely zero (no, not even some experimental driver. It's absolutely impossible).

svn path=/trunk/; revision=45276
 2010-01-26 21:41:05 +00:00
Sir Richard bf8b9467dc [NTOS]: Implement KeUpdateSystemTime and KeUpdateRunTime in C instead of ASM. Based off eVb's ARM implementation, with multiple bugs fixed (incorrect update of system counters, incorrect expiration of timers, remove non-used debug features, use locks when needed). 
[NTOS]: Implement KiComputeTimerTableIndex in C instead of ASM. Based off eVb's ARM implementation, bugfixed to do correct math instead.

As a side effect, this should fix timers on ARM ;-)

svn path=/trunk/; revision=45140
 2010-01-19 06:16:47 +00:00