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NMI Support Patch 2:
[HAL]: Simplify IDT write-protection handling (always make it R/W and restore it to previous state). [HAL]: Avoid two superflous TLB flushes. svn path=/trunk/; revision=44842
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1 changed files with 5 additions and 21 deletions
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@ -254,18 +254,8 @@ HalpBiosDisplayReset(VOID)
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* the cmpxchg8b lock errata. Unprotect them here so we can set our custom
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* invalid op-code handler.
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*/
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if (KeGetCurrentPrcb()->CpuType == 5)
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{
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/* Get the PTE and check if it is has been write protected yet */
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IdtPte = GetPteAddress(((PKIPCR)KeGetPcr())->IDT);
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if (IdtPte->Write == 0)
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{
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/* Remove the protection and flush the TLB */
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IdtPte->Write = 1;
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__writecr3(__readcr3());
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RestoreWriteProtection = TRUE;
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}
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}
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IdtPte = GetPteAddress(((PKIPCR)KeGetPcr())->IDT);
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RestoreWriteProtection = IdtPte->Write;
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/* Use special invalid opcode and GPF trap handlers */
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HalpSwitchToRealModeTrapHandlers();
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@ -279,15 +269,9 @@ HalpBiosDisplayReset(VOID)
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/* Restore kernel trap handlers */
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HalpRestoreTrapHandlers();
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/* Check if we removed the write protection before */
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if (RestoreWriteProtection)
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{
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/* Get the PTE, restore the write protection and flush the TLB */
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IdtPte = GetPteAddress(((PKIPCR)KeGetPcr())->IDT);
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IdtPte->Write = 0;
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__writecr3(__readcr3());
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}
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/* Restore write permission */
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IdtPte->Write = RestoreWriteProtection;
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/* Restore TSS and IOPM */
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HalpRestoreIoPermissionsAndTask();
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