mirror of
https://github.com/reactos/reactos.git
synced 2025-08-06 09:52:56 +00:00
We can now build the ARM kernel (but not link it).
We now define _disable and _enable for ARM. We shouldn't define KeRaiseIrqlToSynchLevel for each architecture, since the prototype is portable itself. It was a mistake to guard against x86 only system calls -- the system calls should be the same on all archs, just return STATUS_NOT_IMPLEMENTED if they don't make sense. Undo the guards. We now define KeGetPcr() as portable -- it's PCR itself that is a per-arch define. We now support ARM in RtlWalkFrameChain. We now support ARM in PspCreateThread. We now define KeArchHaltProcessor for ARM by using Wait-For-Interrupt Mode. We now define KeArmInitThreadWithContext for ARM. KiRestore/SaveProcessorControlState are portable prototypes, we now define them as such. Bochs KD code should use the portable WRITE/READ_PORT_UCHAR defines, we now do so. We now support ARM in SharedUserData->ImageNumberLow/High during ExpInitializeExecutive. NtQuerySytemInformation for SystemProcessorInformation has now been fixed to use the portable KeProcesssorXxx variables instead of reading from the non-portable PRCB values. We now support NtFlushInstructionCache for ARM by flushing the I-Cache. svn path=/trunk/; revision=32197
This commit is contained in:
parent
79f55526f5
commit
fb86c24408
19 changed files with 110 additions and 47 deletions
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@ -9495,12 +9495,6 @@ DDKAPI
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KeRaiseIrqlToDpcLevel(
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KeRaiseIrqlToDpcLevel(
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VOID);
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VOID);
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NTHALAPI
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KIRQL
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DDKAPI
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KeRaiseIrqlToSynchLevel(
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VOID);
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#define KeLowerIrql(a) KfLowerIrql(a)
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#define KeLowerIrql(a) KfLowerIrql(a)
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#define KeRaiseIrql(a,b) *(b) = KfRaiseIrql(a)
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#define KeRaiseIrql(a,b) *(b) = KfRaiseIrql(a)
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@ -9587,13 +9581,14 @@ NTAPI
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KeRaiseIrqlToDpcLevel(
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KeRaiseIrqlToDpcLevel(
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VOID);
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VOID);
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#endif
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NTKERNELAPI
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NTKERNELAPI
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KIRQL
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KIRQL
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DDKAPI
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DDKAPI
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KeRaiseIrqlToSynchLevel(
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KeRaiseIrqlToSynchLevel(
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VOID);
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VOID);
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#endif
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/** Memory manager routines **/
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/** Memory manager routines **/
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@ -39,6 +39,11 @@ Author:
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#define PRCB_BUILD_DEBUG 1
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#define PRCB_BUILD_DEBUG 1
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#define PRCB_BUILD_UNIPROCESSOR 2
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#define PRCB_BUILD_UNIPROCESSOR 2
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//
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// No LDTs on ARM
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//
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#define LDT_ENTRY ULONG
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//
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//
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// HAL Variables
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// HAL Variables
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//
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//
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@ -28,9 +28,8 @@ Author:
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//
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//
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#define K0IPCR ((ULONG_PTR)(KIP0PCRADDRESS))
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#define K0IPCR ((ULONG_PTR)(KIP0PCRADDRESS))
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#define PCR ((volatile KPCR * const)K0IPCR)
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#define PCR ((volatile KPCR * const)K0IPCR)
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#if !defined(CONFIG_SMP) && !defined(NT_BUILD)
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#if defined(CONFIG_SMP) || defined(NT_BUILD)
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#define KeGetPcr() PCR
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#undef KeGetPcr()
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#else
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#define KeGetPcr() ((volatile KPCR * const)__readfsdword(0x1C))
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#define KeGetPcr() ((volatile KPCR * const)__readfsdword(0x1C))
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#endif
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#endif
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@ -457,7 +457,6 @@ NtSetIntervalProfile(
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IN KPROFILE_SOURCE ClockSource
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IN KPROFILE_SOURCE ClockSource
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);
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);
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#ifdef _M_IX86
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NTSYSCALLAPI
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NTSYSCALLAPI
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NTSTATUS
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NTSTATUS
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NTAPI
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NTAPI
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@ -467,7 +466,6 @@ NtSetLdtEntries(
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IN ULONG Selector2,
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IN ULONG Selector2,
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IN LDT_ENTRY LdtEntry2
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IN LDT_ENTRY LdtEntry2
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);
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);
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#endif
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NTSYSCALLAPI
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NTSYSCALLAPI
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NTSTATUS
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NTSTATUS
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@ -665,7 +663,6 @@ ZwSetIntervalProfile(
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IN KPROFILE_SOURCE ClockSource
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IN KPROFILE_SOURCE ClockSource
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);
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);
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#ifdef _M_IX86
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NTSYSAPI
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NTSYSAPI
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NTSTATUS
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NTSTATUS
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NTAPI
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NTAPI
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@ -675,7 +672,6 @@ ZwSetLdtEntries(
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IN ULONG Selector2,
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IN ULONG Selector2,
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IN LDT_ENTRY LdtEntry2
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IN LDT_ENTRY LdtEntry2
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);
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);
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#endif
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NTSYSAPI
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NTSYSAPI
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NTSTATUS
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NTSTATUS
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@ -112,6 +112,11 @@ Author:
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#define KINTERRUPT_DISPATCH_CODES 106
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#define KINTERRUPT_DISPATCH_CODES 106
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#endif
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#endif
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//
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// Get KPCR
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//
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#define KeGetPcr() PCR
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#ifdef NTOS_MODE_USER
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#ifdef NTOS_MODE_USER
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//
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//
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@ -148,5 +148,25 @@ static __inline__ __attribute__((always_inline)) long _InterlockedIncrement16(vo
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return _InterlockedExchangeAdd16(lpAddend, 1) + 1;
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return _InterlockedExchangeAdd16(lpAddend, 1) + 1;
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}
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}
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static __inline__ __attribute__((always_inline)) void _disable(void)
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{
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__asm__ __volatile__
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(
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"mrs r1, cpsr;"
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"orr r1, r1, #0x80;"
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"msr cpsr, r1;"
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);
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}
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static __inline__ __attribute__((always_inline)) void _enable(void)
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{
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__asm__ __volatile__
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(
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"mrs r1, cpsr;"
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"bic r1, r1, #0x80;"
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"msr cpsr, r1;"
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);
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}
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#endif
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#endif
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/* EOF */
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/* EOF */
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@ -4108,6 +4108,7 @@ static __inline__ struct _TEB * NtCurrentTeb(void)
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//
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//
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// NT-ARM is not documented
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// NT-ARM is not documented
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//
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//
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#define KIRQL ULONG // Hack!
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#include <armddk.h>
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#include <armddk.h>
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#else
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#else
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@ -103,16 +103,12 @@ struct _TEB* NtCurrentTeb(VOID)
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//
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//
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// IRQL Support on ARM is similar to MIPS/ALPHA
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// IRQL Support on ARM is similar to MIPS/ALPHA
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//
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//
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NTKERNELAPI
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KIRQL
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KIRQL
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DDKAPI
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KeSwapIrql(
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KeSwapIrql(
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IN KIRQL NewIrql
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IN KIRQL NewIrql
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);
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);
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NTKERNELAPI
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KIRQL
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KIRQL
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NTAPI
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KeRaiseIrqlToDpcLevel(
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KeRaiseIrqlToDpcLevel(
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VOID
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VOID
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);
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);
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@ -1229,6 +1229,9 @@ ExpInitializeExecutive(IN ULONG Cpu,
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#elif defined(_MIPS_)
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#elif defined(_MIPS_)
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SharedUserData->ImageNumberLow = IMAGE_FILE_MACHINE_R4000;
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SharedUserData->ImageNumberLow = IMAGE_FILE_MACHINE_R4000;
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SharedUserData->ImageNumberHigh = IMAGE_FILE_MACHINE_R4000;
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SharedUserData->ImageNumberHigh = IMAGE_FILE_MACHINE_R4000;
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#elif defined(_ARM_)
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SharedUserData->ImageNumberLow = IMAGE_FILE_MACHINE_ARM;
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SharedUserData->ImageNumberHigh = IMAGE_FILE_MACHINE_ARM;
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#else
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#else
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#error "Unsupported ReactOS Target"
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#error "Unsupported ReactOS Target"
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#endif
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#endif
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@ -531,11 +531,11 @@ QSI_DEF(SystemProcessorInformation)
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return (STATUS_INFO_LENGTH_MISMATCH);
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return (STATUS_INFO_LENGTH_MISMATCH);
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}
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}
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Prcb = KeGetCurrentPrcb();
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Prcb = KeGetCurrentPrcb();
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Spi->ProcessorArchitecture = 0; /* Intel Processor */
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Spi->ProcessorArchitecture = KeProcessorArchitecture;
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Spi->ProcessorLevel = Prcb->CpuType;
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Spi->ProcessorLevel = KeProcessorLevel;
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Spi->ProcessorRevision = Prcb->CpuStep;
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Spi->ProcessorRevision = KeProcessorRevision;
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Spi->Reserved = 0;
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Spi->Reserved = 0;
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Spi->ProcessorFeatureBits = Prcb->FeatureBits;
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Spi->ProcessorFeatureBits = KeFeatureBits;
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DPRINT("Arch %d Level %d Rev 0x%x\n", Spi->ProcessorArchitecture,
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DPRINT("Arch %d Level %d Rev 0x%x\n", Spi->ProcessorArchitecture,
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Spi->ProcessorLevel, Spi->ProcessorRevision);
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Spi->ProcessorLevel, Spi->ProcessorRevision);
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#elif defined(_M_MIPS)
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#elif defined(_M_MIPS)
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DPRINT1("NtFlushInstructionCache() is not implemented\n");
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DPRINT1("NtFlushInstructionCache() is not implemented\n");
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for (;;);
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for (;;);
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#elif defined(_M_ARM)
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__asm__ __volatile__("mov r1, #0; mcr p15, 0, r1, c7, c5, 0");
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#else
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#else
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#error Unknown architecture
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#error Unknown architecture
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#endif
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#endif
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@ -26,9 +26,7 @@
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#elif defined(_M_MIPS)
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#elif defined(_M_MIPS)
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#include "../mips/intrin_i.h"
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#include "../mips/intrin_i.h"
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#elif defined(_M_ARM)
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#elif defined(_M_ARM)
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//
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#include "../arm/intrin_i.h"
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// Not sure we'll need ARM internal intrinsics
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//
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#else
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#else
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#error "Unknown processor"
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#error "Unknown processor"
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#endif
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#endif
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18
reactos/ntoskrnl/include/internal/arm/intrin_i.h
Normal file
18
reactos/ntoskrnl/include/internal/arm/intrin_i.h
Normal file
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@ -0,0 +1,18 @@
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#ifndef _INTRIN_INTERNAL_
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#define _INTRIN_INTERNAL_
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static __inline__ __attribute__((always_inline)) void KeArchHaltProcessor(void)
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{
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//
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// Enter Wait-For-Interrupt Mode
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//
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__asm__ __volatile__
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(
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"mov r1, #0;"
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"mcr p15, 0, r1, c7, c0, 4;"
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);
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}
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#endif
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/* EOF */
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@ -1 +1,20 @@
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#ifndef __NTOSKRNL_INCLUDE_INTERNAL_ARM_KE_H
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#define __NTOSKRNL_INCLUDE_INTERNAL_ARM_KE_H
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#if __GNUC__ >=3
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#pragma GCC system_header
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#endif
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VOID
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NTAPI
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KeArmInitThreadWithContext(
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IN PKTHREAD Thread,
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IN PKSYSTEM_ROUTINE SystemRoutine,
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IN PKSTART_ROUTINE StartRoutine,
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IN PVOID StartContext,
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IN PCONTEXT Context
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);
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#define KeArchInitThreadWithContext KeArmInitThreadWithContext
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#endif
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@ -61,18 +61,6 @@ Ki386InitializeTss(
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IN PKGDTENTRY Gdt
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IN PKGDTENTRY Gdt
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);
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);
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VOID
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NTAPI
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KiRestoreProcessorControlState(
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IN PKPROCESSOR_STATE ProcessorState
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);
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VOID
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NTAPI
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KiSaveProcessorControlState(
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OUT PKPROCESSOR_STATE ProcessorState
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);
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VOID
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VOID
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FASTCALL
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FASTCALL
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KiIdleLoop(VOID);
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KiIdleLoop(VOID);
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@ -972,6 +972,18 @@ KeReleaseQueuedSpinLockFromDpcLevel(
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IN OUT PKSPIN_LOCK_QUEUE LockQueue
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IN OUT PKSPIN_LOCK_QUEUE LockQueue
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);
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);
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VOID
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NTAPI
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KiRestoreProcessorControlState(
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IN PKPROCESSOR_STATE ProcessorState
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);
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VOID
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NTAPI
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KiSaveProcessorControlState(
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OUT PKPROCESSOR_STATE ProcessorState
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);
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#include "ke_x.h"
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#include "ke_x.h"
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#endif /* __NTOSKRNL_INCLUDE_INTERNAL_KE_H */
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#endif /* __NTOSKRNL_INCLUDE_INTERNAL_KE_H */
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@ -12,7 +12,7 @@
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#include <internal/debug.h>
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#include <internal/debug.h>
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/* bochs debug output */
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/* bochs debug output */
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#define BOCHS_LOGGER_PORT (0xe9)
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#define BOCHS_LOGGER_PORT ((PVOID)0xe9)
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/* FUNCTIONS *****************************************************************/
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/* FUNCTIONS *****************************************************************/
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@ -27,9 +27,9 @@ KdpBochsDebugPrint(IN PCH Message,
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{
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{
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if (*Message == '\n')
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if (*Message == '\n')
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{
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{
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__outbyte(BOCHS_LOGGER_PORT, '\r');
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WRITE_PORT_UCHAR(BOCHS_LOGGER_PORT, '\r');
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}
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}
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__outbyte(BOCHS_LOGGER_PORT, *Message);
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WRITE_PORT_UCHAR(BOCHS_LOGGER_PORT, *Message);
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Message++;
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Message++;
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}
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}
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}
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}
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@ -44,8 +44,8 @@ KdpBochsInit(PKD_DISPATCH_TABLE DispatchTable,
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|
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if (BootPhase == 0)
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if (BootPhase == 0)
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{
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{
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Value = __inbyte(BOCHS_LOGGER_PORT);
|
Value = READ_PORT_UCHAR(BOCHS_LOGGER_PORT);
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if (Value != BOCHS_LOGGER_PORT)
|
if (Value != (ULONG)BOCHS_LOGGER_PORT)
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{
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{
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KdpDebugMode.Bochs = FALSE;
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KdpDebugMode.Bochs = FALSE;
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return;
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return;
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@ -112,7 +112,7 @@ MmInitVirtualMemory(ULONG_PTR LastKernelAddress,
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*/
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*/
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MiInitPageDirectoryMap();
|
MiInitPageDirectoryMap();
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|
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BaseAddress = (PVOID)KIP0PCRADDRESS;
|
BaseAddress = (PVOID)PCR;
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MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MmCreateMemoryArea(MmGetKernelAddressSpace(),
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MEMORY_AREA_SYSTEM,
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MEMORY_AREA_SYSTEM,
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&BaseAddress,
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&BaseAddress,
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|
|
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@ -328,7 +328,11 @@ PspCreateThread(OUT PHANDLE ThreadHandle,
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Thread->StartAddress = (PVOID)ThreadContext->Dr0;
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Thread->StartAddress = (PVOID)ThreadContext->Dr0;
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Thread->Win32StartAddress = (PVOID)ThreadContext->Gpr3;
|
Thread->Win32StartAddress = (PVOID)ThreadContext->Gpr3;
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#elif defined(_M_MIPS)
|
#elif defined(_M_MIPS)
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for (;;);
|
Thread->StartAddress = (PVOID)ThreadContext->Psr;
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|
Thread->Win32StartAddress = (PVOID)ThreadContext->IntA0;
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|
#elif defined(_M_ARM)
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|
Thread->StartAddress = (PVOID)ThreadContext->Pc;
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|
Thread->Win32StartAddress = (PVOID)ThreadContext->R0;
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#else
|
#else
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#error Unknown architecture
|
#error Unknown architecture
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#endif
|
#endif
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|
|
|
@ -284,6 +284,8 @@ RtlWalkFrameChain(OUT PVOID *Callers,
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__asm__("move $sp, %0" : "=r" (Stack) : );
|
__asm__("move $sp, %0" : "=r" (Stack) : );
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#elif defined(_M_PPC)
|
#elif defined(_M_PPC)
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__asm__("mr %0,1" : "=r" (Stack) : );
|
__asm__("mr %0,1" : "=r" (Stack) : );
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|
#elif defined(_M_ARM)
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|
__asm__("mov sp, %0" : "=r"(Stack) : );
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#else
|
#else
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#error Unknown architecture
|
#error Unknown architecture
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||||||
#endif
|
#endif
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||||||
|
|
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