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Remove trailing whitespace and fix indentation

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svn path=/trunk/; revision=16401
This commit is contained in:
Eric Kohl 2005-07-03 21:37:16 +00:00
parent d3bf39b1f2
commit fae2febad9
2 changed files with 80 additions and 83 deletions
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2
reactos/ntoskrnl/ke/i386/syscall.S
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@ -393,7 +393,7 @@ _KiServiceExit2:
popl %ebp // + 0x14
add $4, %esp // + 0x10
/* Return to user-mode */
/* Return to user-mode */
iret
.intel_syntax noprefix

33
reactos/ntoskrnl/ke/i386/tlbflush.S
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@ -1,7 +1,8 @@
/* i386-specific implemetation of Translation Buffer Flushing
/*
* i386-specific implemetation of Translation Buffer Flushing
* Written By: Alex Ionescu <alex@relsoft.net>
* Reference: IA-32 Intel® Architecture Software Developer's Manual, Volume 3: System Programming Guide,
* Chapter 10 - Memory Cache Control. Section 10.9 - Invalidating the Translation Lookaside Buffers
* Chapter 10 - Memory Cache Control. Section 10.9 - Invalidating the Translation Lookaside Buffers
*/
#include <internal/i386/ke.h>
@ -10,23 +11,19 @@
.globl _KeFlushCurrentTb@0
_KeFlushCurrentTb@0:
/* Check for global page support */
testb $0xff, (_Ke386GlobalPagesEnabled)
jz .L1
testb $0xff, (_Ke386GlobalPagesEnabled)
jz .L1
/* Modifying the PSE, PGE or PAE Flag in CR4 causes the TLB to be flushed */
movl %cr4, %eax
andl $~X86_CR4_PGE, %eax
movl %eax, %cr4
orl $X86_CR4_PGE, %eax
movl %eax, %cr4
ret
/* Modifying the PSE, PGE or PAE Flag in CR4 causes the TLB to be flushed */
movl %cr4, %eax
andl $~X86_CR4_PGE, %eax
movl %eax, %cr4
orl $X86_CR4_PGE, %eax
movl %eax, %cr4
ret
.L1:
/* the old way ... */
movl %cr3, %eax
movl %eax, %cr3
ret
movl %cr3, %eax
movl %eax, %cr3
ret