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Remove trailing whitespace and fix indentation
svn path=/trunk/; revision=16401
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parent
d3bf39b1f2
commit
fae2febad9
2 changed files with 80 additions and 83 deletions
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@ -393,7 +393,7 @@ _KiServiceExit2:
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popl %ebp // + 0x14
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popl %ebp // + 0x14
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add $4, %esp // + 0x10
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add $4, %esp // + 0x10
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/* Return to user-mode */
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/* Return to user-mode */
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iret
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iret
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.intel_syntax noprefix
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.intel_syntax noprefix
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@ -1,7 +1,8 @@
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/* i386-specific implemetation of Translation Buffer Flushing
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/*
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* i386-specific implemetation of Translation Buffer Flushing
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* Written By: Alex Ionescu <alex@relsoft.net>
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* Written By: Alex Ionescu <alex@relsoft.net>
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* Reference: IA-32 Intel® Architecture Software Developer's Manual, Volume 3: System Programming Guide,
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* Reference: IA-32 Intel® Architecture Software Developer's Manual, Volume 3: System Programming Guide,
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* Chapter 10 - Memory Cache Control. Section 10.9 - Invalidating the Translation Lookaside Buffers
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* Chapter 10 - Memory Cache Control. Section 10.9 - Invalidating the Translation Lookaside Buffers
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*/
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*/
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#include <internal/i386/ke.h>
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#include <internal/i386/ke.h>
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@ -10,23 +11,19 @@
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.globl _KeFlushCurrentTb@0
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.globl _KeFlushCurrentTb@0
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_KeFlushCurrentTb@0:
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_KeFlushCurrentTb@0:
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/* Check for global page support */
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/* Check for global page support */
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testb $0xff, (_Ke386GlobalPagesEnabled)
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testb $0xff, (_Ke386GlobalPagesEnabled)
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jz .L1
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jz .L1
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/* Modifying the PSE, PGE or PAE Flag in CR4 causes the TLB to be flushed */
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/* Modifying the PSE, PGE or PAE Flag in CR4 causes the TLB to be flushed */
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movl %cr4, %eax
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movl %cr4, %eax
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andl $~X86_CR4_PGE, %eax
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andl $~X86_CR4_PGE, %eax
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movl %eax, %cr4
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movl %eax, %cr4
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orl $X86_CR4_PGE, %eax
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orl $X86_CR4_PGE, %eax
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movl %eax, %cr4
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movl %eax, %cr4
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ret
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ret
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.L1:
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.L1:
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/* the old way ... */
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/* the old way ... */
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movl %cr3, %eax
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movl %cr3, %eax
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movl %eax, %cr3
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movl %eax, %cr3
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ret
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ret
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