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- Fixed the changing of the PGE bit in cr4.

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- Check if the cpu supports global pages.

svn path=/trunk/; revision=11317
This commit is contained in:
Hartmut Birr 2004-10-17 17:28:45 +00:00
parent 53a23c65e8
commit f7f880f8e9
2 changed files with 28 additions and 15 deletions
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18
reactos/ntoskrnl/include/internal/i386/ke.h
View file

@ -69,6 +69,15 @@
#define KTRAP_FRAME_RESERVED9 (0x8A) #define KTRAP_FRAME_RESERVED9 (0x8A)
#define KTRAP_FRAME_SIZE (0x8C) #define KTRAP_FRAME_SIZE (0x8C)
#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */
#define X86_CR4_PGE 0x00000080 /* enable global pages */
#define X86_FEATURE_PAE 0x00000040 /* physical address extension is present */
#define X86_FEATURE_PGE 0x00002000 /* Page Global Enable */
#ifndef __ASM__ #ifndef __ASM__
typedef struct _KTRAP_FRAME typedef struct _KTRAP_FRAME
@ -156,15 +165,6 @@ VOID KeFreeGdtSelector(ULONG Entry);
VOID VOID
NtEarlyInitVdm(VOID); NtEarlyInitVdm(VOID);
#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */
#define X86_CR4_PGE 0x00000080 /* enable global pages */
#define X86_FEATURE_PAE 0x00000040 /* physical address extension is present */
#define X86_FEATURE_PGE 0x00002000 /* Page Global Enable */
#if defined(__GNUC__) #if defined(__GNUC__)
#define Ke386DisableInterrupts() __asm__("cli\n\t"); #define Ke386DisableInterrupts() __asm__("cli\n\t");
#define Ke386EnableInterrupts() __asm__("sti\n\t"); #define Ke386EnableInterrupts() __asm__("sti\n\t");

25
reactos/ntoskrnl/ke/i386/tlbflush.S
View file

@ -4,16 +4,29 @@
* Chapter 10 - Memory Cache Control. Section 10.9 - Invalidating the Translation Lookaside Buffers * Chapter 10 - Memory Cache Control. Section 10.9 - Invalidating the Translation Lookaside Buffers
*/ */
#include <internal/i386/ke.h>
.globl _KeFlushCurrentTb@0 .globl _KeFlushCurrentTb@0
_KeFlushCurrentTb@0: _KeFlushCurrentTb@0:
/* Modifying the PSE, PGE or PAE Flag in CR4 causes the TLB to be flushed */ /* Check for global page support */
andl $0xFFFFFF7F, %eax testl $X86_FEATURE_PGE, (_Ke386CpuidFlags)
movl %eax, %cr4 jz .L1
orl $0x80, %eax
movl %eax, %cr4
/* Modifying the PSE, PGE or PAE Flag in CR4 causes the TLB to be flushed */
movl %cr4, %eax
andl $~X86_CR4_PGE, %eax
movl %eax, %cr4
orl $X86_CR4_PGE, %eax
movl %eax, %cr4
ret
.L1:
/* the old way ... */
movl %cr3, %eax
movl %eax, %cr3
ret ret