diff --git a/reactos/hal/hal.rbuild b/reactos/hal/hal.rbuild index 48016f53e1d..98d50f0dcf8 100644 --- a/reactos/hal/hal.rbuild +++ b/reactos/hal/hal.rbuild @@ -26,4 +26,12 @@ + + + + + + + + diff --git a/reactos/hal/hal/hal.c b/reactos/hal/hal/hal.c index 7ef9cdc5371..bd6cf5b0d04 100644 --- a/reactos/hal/hal/hal.c +++ b/reactos/hal/hal/hal.c @@ -75,6 +75,7 @@ HalSetProfileInterval(IN ULONG_PTR Interval) return Interval; } +#ifndef _M_AMD64 VOID FASTCALL ExAcquireFastMutex( @@ -101,7 +102,7 @@ ExTryToAcquireFastMutex( return TRUE; } - +#endif VOID NTAPI @@ -466,7 +467,7 @@ HalReportResourceUsage(VOID) VOID NTAPI HalRequestIpi( - ULONG Unknown) + KAFFINITY TargetSet) { UNIMPLEMENTED; } @@ -747,7 +748,7 @@ KeAcquireSpinLockRaiseToSynch( return 0; } - +#ifndef _M_AMD64 VOID FASTCALL KeAcquireInStackQueuedSpinLock( @@ -776,6 +777,7 @@ KeReleaseInStackQueuedSpinLock( { UNIMPLEMENTED; } +#endif VOID NTAPI @@ -784,6 +786,7 @@ KeFlushWriteBuffer(VOID) UNIMPLEMENTED; } +#ifndef _M_AMD64 #undef KeGetCurrentIrql KIRQL NTAPI @@ -802,6 +805,7 @@ KeLowerIrql( { UNIMPLEMENTED; } +#endif LARGE_INTEGER @@ -818,6 +822,7 @@ KeQueryPerformanceCounter( return Value; } +#ifndef _M_AMD64 #undef KeRaiseIrql VOID NTAPI @@ -847,7 +852,9 @@ KeRaiseIrqlToSynchLevel(VOID) return (KIRQL)0; } +#endif +#ifndef _M_AMD64 #undef KeReleaseSpinLock VOID NTAPI @@ -857,7 +864,7 @@ KeReleaseSpinLock( { UNIMPLEMENTED; } - +#endif VOID NTAPI @@ -891,7 +898,7 @@ KeTryToAcquireQueuedSpinLockRaiseToSynch( return FALSE; } - +#if !defined(_M_AMD64) KIRQL FASTCALL KfAcquireSpinLock( @@ -931,8 +938,9 @@ KfReleaseSpinLock( { UNIMPLEMENTED; } +#endif - +#if !defined(_M_AMD64) VOID NTAPI READ_PORT_BUFFER_UCHAR( @@ -1058,6 +1066,7 @@ WRITE_PORT_USHORT( { UNIMPLEMENTED; } +#endif KIRQL FASTCALL diff --git a/reactos/hal/hal/hal.rbuild b/reactos/hal/hal/hal.rbuild index 561415003ac..d89871d099c 100644 --- a/reactos/hal/hal/hal.rbuild +++ b/reactos/hal/hal/hal.rbuild @@ -10,8 +10,8 @@ hal.c hal.rc - - + + include @@ -20,7 +20,7 @@ hal.c hal.rc - + @@ -30,4 +30,14 @@ + + + + include + ntoskrnl + + hal.c + hal.rc + + diff --git a/reactos/hal/hal/hal_amd64.def b/reactos/hal/hal/hal_amd64.def new file mode 100644 index 00000000000..1d8fa785c0e --- /dev/null +++ b/reactos/hal/hal/hal_amd64.def @@ -0,0 +1,86 @@ +; Hardware Abstraction Layer - ReactOS Operating System + +LIBRARY hal.dll + +EXPORTS +HalAcquireDisplayOwnership +HalAdjustResourceList +HalAllProcessorsStarted +HalAllocateAdapterChannel +HalAllocateCommonBuffer +HalAllocateCrashDumpRegisters +HalAssignSlotResources +;HalBugCheckSystem +HalCalibratePerformanceCounter +HalClearSoftwareInterrupt +;HalConvertDeviceIdtToIrql +;HalDisableInterrupt +HalDisplayString +;HalEnableInterrupt +;HalEnumerateEnvironmentVariablesEx +;HalEnumerateProcessors +HalFlushCommonBuffer +HalFreeCommonBuffer +HalGetAdapter +HalGetBusData +HalGetBusDataByOffset +HalGetEnvironmentVariable +;HalGetEnvironmentVariableEx +;HalGetInterruptTargetInformation +HalGetInterruptVector +;HalGetMessageRoutingInfo +;HalGetProcessorIdByNtNumber +;HalGetVectorInput +;HalHandleMcheck +HalHandleNMI +HalInitSystem +;HalInitializeBios +;HalInitializeOnResume +HalInitializeProcessor +;HalIsHyperThreadingEnabled +HalMakeBeep +HalProcessorIdle +HalQueryDisplayParameters +;HalQueryEnvironmentVariableInfoEx +;HalQueryMaximumProcessorCount +HalQueryRealTimeClock +HalReadDmaCounter +;HalRegisterDynamicProcessor +;HalRegisterErrataCallbacks +HalReportResourceUsage +HalRequestIpi +HalRequestSoftwareInterrupt +HalReturnToFirmware +;HalSendNMI +;HalSendSoftwareInterrupt +HalSetBusData +HalSetBusDataByOffset +HalSetDisplayParameters +HalSetEnvironmentVariable +;HalSetEnvironmentVariableEx +HalSetProfileInterval +HalSetRealTimeClock +HalSetTimeIncrement +;HalStartDynamicProcessor +HalStartNextProcessor +HalStartProfileInterrupt +HalStopProfileInterrupt +HalSystemVectorDispatchEntry +HalTranslateBusAddress +IoAssignDriveLetters +IoFlushAdapterBuffers +IoFreeAdapterChannel +IoFreeMapRegisters +IoMapTransfer +IoReadPartitionTable +IoSetPartitionInformation +IoWritePartitionTable +KdComPortInUse=_KdComPortInUse DATA +KeFlushWriteBuffer +KeQueryPerformanceCounter +KeStallExecutionProcessor +;x86BiosAllocateBuffer +;x86BiosCall +;x86BiosFreeBuffer +;x86BiosReadMemory +;x86BiosWriteMemory diff --git a/reactos/hal/halamd64/directory.rbuild b/reactos/hal/halamd64/directory.rbuild new file mode 100644 index 00000000000..1e0c730ba32 --- /dev/null +++ b/reactos/hal/halamd64/directory.rbuild @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/reactos/hal/halamd64/generic/generic.rbuild b/reactos/hal/halamd64/generic/generic.rbuild new file mode 100644 index 00000000000..7c22ec5013e --- /dev/null +++ b/reactos/hal/halamd64/generic/generic.rbuild @@ -0,0 +1,16 @@ + + + + + ../include + include + + + halinit.c + irq.S + misc.c + mps.S + systimer.S + ../include/hal.h + + diff --git a/reactos/hal/halamd64/generic/hal.c b/reactos/hal/halamd64/generic/hal.c new file mode 100644 index 00000000000..82c60f243e6 --- /dev/null +++ b/reactos/hal/halamd64/generic/hal.c @@ -0,0 +1,1538 @@ +/* + * PROJECT: ReactOS HAL + * LICENSE: BSD - See COPYING.ARM in the top level directory + * FILE: hal/halarm/generic/hal.c + * PURPOSE: Hardware Abstraction Layer + * PROGRAMMERS: ReactOS Portable Systems Group + */ + +/* INCLUDES *******************************************************************/ + +#include +#define NDEBUG +#include +#include + +#undef ExAcquireFastMutex +#undef ExReleaseFastMutex +#undef ExTryToAcquireFastMutex +#undef KeAcquireSpinLock +#undef KeLowerIrql +#undef KeRaiseIrql +#undef KeReleaseSpinLock + +#define READ_REGISTER_ULONG(r) (*(volatile ULONG * const)(r)) +#define WRITE_REGISTER_ULONG(r, v) (*(volatile ULONG *)(r) = (v)) + +/* DATA **********************************************************************/ + +ULONG HalpCurrentTimeIncrement, HalpNextTimeIncrement, HalpNextIntervalCount; +ULONG _KdComPortInUse = 0; + +ULONG HalpIrqlTable[HIGH_LEVEL + 1] = +{ + 0xFFFFFFFF, // IRQL 0 PASSIVE_LEVEL + 0xFFFFFFFD, // IRQL 1 APC_LEVEL + 0xFFFFFFF9, // IRQL 2 DISPATCH_LEVEL + 0xFFFFFFD9, // IRQL 3 + 0xFFFFFF99, // IRQL 4 + 0xFFFFFF19, // IRQL 5 + 0xFFFFFE19, // IRQL 6 + 0xFFFFFC19, // IRQL 7 + 0xFFFFF819, // IRQL 8 + 0xFFFFF019, // IRQL 9 + 0xFFFFE019, // IRQL 10 + 0xFFFFC019, // IRQL 11 + 0xFFFF8019, // IRQL 12 + 0xFFFF0019, // IRQL 13 + 0xFFFE0019, // IRQL 14 + 0xFFFC0019, // IRQL 15 + 0xFFF80019, // IRQL 16 + 0xFFF00019, // IRQL 17 + 0xFFE00019, // IRQL 18 + 0xFFC00019, // IRQL 19 + 0xFF800019, // IRQL 20 + 0xFF000019, // IRQL 21 + 0xFE000019, // IRQL 22 + 0xFC000019, // IRQL 23 + 0xF0000019, // IRQL 24 + 0x80000019, // IRQL 25 + 0x19, // IRQL 26 + 0x18, // IRQL 27 PROFILE_LEVEL + 0x10, // IRQL 28 CLOCK2_LEVEL + 0x00, // IRQL 29 IPI_LEVEL + 0x00, // IRQL 30 POWER_LEVEL + 0x00, // IRQL 31 HIGH_LEVEL +}; + +UCHAR HalpMaskTable[HIGH_LEVEL + 1] = +{ + PROFILE_LEVEL, // INT 0 WATCHDOG + APC_LEVEL, // INT 1 SOFTWARE INTERRUPT + DISPATCH_LEVEL,// INT 2 COMM RX + IPI_LEVEL, // INT 3 COMM TX + CLOCK2_LEVEL, // INT 4 TIMER 0 + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 26, + 26 +}; + +/* FUNCTIONS *****************************************************************/ + +NTSTATUS +NTAPI +DriverEntry( + PDRIVER_OBJECT DriverObject, + PUNICODE_STRING RegistryPath) +{ + UNIMPLEMENTED; + + return STATUS_SUCCESS; +} + +/* +* @unimplemented +*/ +VOID +NTAPI +HalStopProfileInterrupt(IN KPROFILE_SOURCE ProfileSource) +{ + KEBUGCHECK(0); + return; +} + +/* +* @unimplemented +*/ +VOID +NTAPI +HalStartProfileInterrupt(IN KPROFILE_SOURCE ProfileSource) +{ + KEBUGCHECK(0); + return; +} + +/* +* @unimplemented +*/ +ULONG_PTR +NTAPI +HalSetProfileInterval(IN ULONG_PTR Interval) +{ + KEBUGCHECK(0); + return Interval; +} + +VOID +FASTCALL +ExAcquireFastMutex( + PFAST_MUTEX FastMutex) +{ + UNIMPLEMENTED; +} + + +VOID +FASTCALL +ExReleaseFastMutex( + PFAST_MUTEX FastMutex) +{ + UNIMPLEMENTED; +} + + +BOOLEAN FASTCALL +ExTryToAcquireFastMutex( + PFAST_MUTEX FastMutex) +{ + UNIMPLEMENTED; + + return TRUE; +} + + +NTSTATUS +NTAPI +HalAdjustResourceList( + PCM_RESOURCE_LIST Resources) +{ + UNIMPLEMENTED; + + return STATUS_SUCCESS; +} + + +/* + * @implemented + */ +BOOLEAN +NTAPI +HalAllProcessorsStarted(VOID) +{ + /* Do nothing */ + return TRUE; +} + + +NTSTATUS +NTAPI +HalAllocateAdapterChannel( + PADAPTER_OBJECT AdapterObject, + PWAIT_CONTEXT_BLOCK WaitContextBlock, + ULONG NumberOfMapRegisters, + PDRIVER_CONTROL ExecutionRoutine) +{ + UNIMPLEMENTED; + + return STATUS_SUCCESS; +} + + +PVOID +NTAPI +HalAllocateCommonBuffer( + PADAPTER_OBJECT AdapterObject, + ULONG Length, + PPHYSICAL_ADDRESS LogicalAddress, + BOOLEAN CacheEnabled) +{ + UNIMPLEMENTED; + + return NULL; +} + + +PVOID +NTAPI +HalAllocateCrashDumpRegisters( + PADAPTER_OBJECT AdapterObject, + PULONG NumberOfMapRegisters) +{ + UNIMPLEMENTED; + return NULL; +} + + +NTSTATUS +NTAPI +HalAssignSlotResources( + PUNICODE_STRING RegistryPath, + PUNICODE_STRING DriverClassName, + PDRIVER_OBJECT DriverObject, + PDEVICE_OBJECT DeviceObject, + INTERFACE_TYPE BusType, + ULONG BusNumber, + ULONG SlotNumber, + PCM_RESOURCE_LIST *AllocatedResources) +{ + UNIMPLEMENTED; + + return TRUE; +} + + +BOOLEAN +NTAPI +HalBeginSystemInterrupt (KIRQL Irql, + ULONG Vector, + PKIRQL OldIrql) +{ + UNIMPLEMENTED; + + return TRUE; +} + + +VOID +NTAPI +HalCalibratePerformanceCounter( + volatile LONG *Count, + ULONGLONG NewCount) +{ + UNIMPLEMENTED; +} + + +BOOLEAN +NTAPI +HalDisableSystemInterrupt( + ULONG Vector, + KIRQL Irql) +{ + UNIMPLEMENTED; + + return TRUE; +} + +VOID +NTAPI +HalAcquireDisplayOwnership(IN PHAL_RESET_DISPLAY_PARAMETERS ResetDisplayParameters) +{ + // + // Stub since Windows XP implemented Inbv + // + return; +} + +VOID +NTAPI +HalDisplayString(IN PCH String) +{ + // + // Call the Inbv driver + // + InbvDisplayString(String); +} + +VOID +NTAPI +HalQueryDisplayParameters(OUT PULONG DispSizeX, + OUT PULONG DispSizeY, + OUT PULONG CursorPosX, + OUT PULONG CursorPosY) +{ + // + // Stub since Windows XP implemented Inbv + // + return; +} + +VOID +NTAPI +HalSetDisplayParameters(IN ULONG CursorPosX, + IN ULONG CursorPosY) +{ + // + // Stub since Windows XP implemented Inbv + // + return; +} + +BOOLEAN +NTAPI +HalEnableSystemInterrupt( + ULONG Vector, + KIRQL Irql, + KINTERRUPT_MODE InterruptMode) +{ + UNIMPLEMENTED; + + return TRUE; +} + + +VOID +NTAPI +HalEndSystemInterrupt( + KIRQL Irql, + ULONG Unknown2) +{ + UNIMPLEMENTED; +} + + +BOOLEAN +NTAPI +HalFlushCommonBuffer( + ULONG Unknown1, + ULONG Unknown2, + ULONG Unknown3, + ULONG Unknown4, + ULONG Unknown5) +{ + UNIMPLEMENTED; + + return TRUE; +} + + +VOID +NTAPI +HalFreeCommonBuffer( + PADAPTER_OBJECT AdapterObject, + ULONG Length, + PHYSICAL_ADDRESS LogicalAddress, + PVOID VirtualAddress, + BOOLEAN CacheEnabled) +{ + UNIMPLEMENTED; +} + + +PADAPTER_OBJECT +NTAPI +HalGetAdapter( + PDEVICE_DESCRIPTION DeviceDescription, + PULONG NumberOfMapRegisters) +{ + UNIMPLEMENTED; + + return (PADAPTER_OBJECT)NULL; +} + + +ULONG +NTAPI +HalGetBusData( + BUS_DATA_TYPE BusDataType, + ULONG BusNumber, + ULONG SlotNumber, + PVOID Buffer, + ULONG Length) +{ + UNIMPLEMENTED; + + return 0; +} + + +ULONG +NTAPI +HalGetBusDataByOffset( + BUS_DATA_TYPE BusDataType, + ULONG BusNumber, + ULONG SlotNumber, + PVOID Buffer, + ULONG Offset, + ULONG Length) +{ + UNIMPLEMENTED; + + return 0; +} + + +ARC_STATUS +NTAPI +HalGetEnvironmentVariable( + PCH Name, + USHORT ValueLength, + PCH Value) +{ + UNIMPLEMENTED; + + return ENOENT; +} + + +ULONG +NTAPI +HalGetInterruptVector( + INTERFACE_TYPE InterfaceType, + ULONG BusNumber, + ULONG BusInterruptLevel, + ULONG BusInterruptVector, + PKIRQL Irql, + PKAFFINITY Affinity) +{ + UNIMPLEMENTED; + + return 0; +} + + +VOID +NTAPI +HalHandleNMI( + PVOID NmiData) +{ + UNIMPLEMENTED; +} + +VOID +NTAPI +HalpGetParameters(IN PLOADER_PARAMETER_BLOCK LoaderBlock) +{ + PCHAR CommandLine; + + /* Make sure we have a loader block and command line */ + if ((LoaderBlock) && (LoaderBlock->LoadOptions)) + { + /* Read the command line */ + CommandLine = LoaderBlock->LoadOptions; + + /* Check for initial breakpoint */ + if (strstr(CommandLine, "BREAK")) DbgBreakPoint(); + } +} + +ULONG +HalGetInterruptSource(VOID) +{ + ULONG InterruptStatus; + + // + // Get the interrupt status, and return the highest bit set + // + InterruptStatus = READ_REGISTER_ULONG(VIC_INT_STATUS); + return 31 - _clz(InterruptStatus); +} + +VOID +HalpClockInterrupt(VOID) +{ + // + // Clear the interrupt + // + ASSERT(KeGetCurrentIrql() == CLOCK2_LEVEL); + WRITE_REGISTER_ULONG(TIMER0_INT_CLEAR, 1); + + // + // FIXME: Update HAL Perf counters + // + + // + // FIXME: Check if someone changed the clockrate + // + + // + // Call the kernel + // + KeUpdateSystemTime(KeGetCurrentThread()->TrapFrame, + CLOCK2_LEVEL, + HalpCurrentTimeIncrement); + + // + // We're done + // +} + +VOID +HalpStallInterrupt(VOID) +{ + // + // Clear the interrupt + // + WRITE_REGISTER_ULONG(TIMER0_INT_CLEAR, 1); +} + +VOID +HalpInitializeInterrupts(VOID) +{ + PKPCR Pcr = (PKPCR)KeGetPcr(); + ULONG ClockInterval; + SP804_CONTROL_REGISTER ControlRegister; + + // + // Fill out the IRQL mappings + // + RtlCopyMemory(Pcr->IrqlTable, HalpIrqlTable, sizeof(Pcr->IrqlTable)); + RtlCopyMemory(Pcr->IrqlMask, HalpMaskTable, sizeof(Pcr->IrqlMask)); + + // + // Setup the clock and profile interrupt + // + Pcr->InterruptRoutine[CLOCK2_LEVEL] = HalpStallInterrupt; + + // + // Configure the interval to 10ms + // (INTERVAL (10ms) * TIMCLKfreq (1MHz)) + // --------------------------------------- == 10^4 + // (TIMCLKENXdiv (1) * PRESCALEdiv (1)) + // + ClockInterval = 0x2710; + + // + // Configure the timer + // + ControlRegister.AsUlong = 0; + ControlRegister.Wide = TRUE; + ControlRegister.Periodic = TRUE; + ControlRegister.Interrupt = TRUE; + ControlRegister.Enabled = TRUE; + + // + // Enable the timer + // + WRITE_REGISTER_ULONG(TIMER0_LOAD, ClockInterval); + WRITE_REGISTER_ULONG(TIMER0_CONTROL, ControlRegister.AsUlong); +} + +/* + * @implemented + */ +BOOLEAN +NTAPI +HalInitSystem(IN ULONG BootPhase, + IN PLOADER_PARAMETER_BLOCK LoaderBlock) +{ + PKPRCB Prcb = KeGetCurrentPrcb(); + + // + // Check the boot phase + // + if (!BootPhase) + { + // + // Get command-line parameters + // + HalpGetParameters(LoaderBlock); + +#if DBG + // + // Checked HAL requires checked kernel + // + if (!(Prcb->BuildType & PRCB_BUILD_DEBUG)) + { + // + // No match, bugcheck + // + KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 1, 0); + } +#else + // + // Release build requires release HAL + // + if (Prcb->BuildType & PRCB_BUILD_DEBUG) + { + // + // No match, bugcheck + // + KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 0, 0); + } +#endif + +#ifdef CONFIG_SMP + // + // SMP HAL requires SMP kernel + // + if (Prcb->BuildType & PRCB_BUILD_UNIPROCESSOR) + { + // + // No match, bugcheck + // + KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 0, 0); + } +#endif + + // + // Validate the PRCB + // + if (Prcb->MajorVersion != PRCB_MAJOR_VERSION) + { + // + // Validation failed, bugcheck + // + KeBugCheckEx(MISMATCHED_HAL, 1, Prcb->MajorVersion, 1, 0); + } + + // + // Setup time increments to 10ms and 1ms + // + HalpCurrentTimeIncrement = 100000; + HalpNextTimeIncrement = 100000; + HalpNextIntervalCount = 0; + KeSetTimeIncrement(100000, 10000); + + // + // Initialize interrupts + // + HalpInitializeInterrupts(); + } + else if (BootPhase == 1) + { + // + // Switch to real clock interrupt + // + PCR->InterruptRoutine[CLOCK2_LEVEL] = HalpClockInterrupt; + } + + // + // All done, return + // + return TRUE; +} + + +VOID +NTAPI +HalInitializeProcessor(IN ULONG ProcessorNumber, + IN PLOADER_PARAMETER_BLOCK LoaderBlock) +{ + // + // Nothing to do + // + return; +} + + +BOOLEAN +NTAPI +HalMakeBeep( + ULONG Frequency) +{ + UNIMPLEMENTED; + + return TRUE; +} + + +VOID +NTAPI +HalProcessorIdle(VOID) +{ + UNIMPLEMENTED; +} + + +#define RTC_DATA (PVOID)0xE00E8000 + +BOOLEAN +NTAPI +HalQueryRealTimeClock(IN PTIME_FIELDS Time) +{ + LARGE_INTEGER LargeTime; + ULONG Seconds; + + // + // Query the RTC value + // + Seconds = READ_REGISTER_ULONG(RTC_DATA); + + // + // Convert to time + // + RtlSecondsSince1970ToTime(Seconds, &LargeTime); + + // + // Convert to time-fields + // + RtlTimeToTimeFields(&LargeTime, Time); + return TRUE; +} + +ULONG +NTAPI +HalReadDmaCounter( + PADAPTER_OBJECT AdapterObject) +{ + UNIMPLEMENTED; + + return 0; +} + + +VOID +NTAPI +HalReportResourceUsage(VOID) +{ + UNIMPLEMENTED; +} + + +VOID +NTAPI +HalRequestIpi( + ULONG Unknown) +{ + UNIMPLEMENTED; +} + + +VOID +FASTCALL +HalRequestSoftwareInterrupt(IN KIRQL Request) +{ + // + // Force a software interrupt + // + WRITE_REGISTER_ULONG(VIC_SOFT_INT, 1 << Request); +} + +VOID +FASTCALL +HalClearSoftwareInterrupt(IN KIRQL Request) +{ + // + // Clear a software interrupt + // + WRITE_REGISTER_ULONG(VIC_SOFT_INT_CLEAR, 1 << Request); +} + +VOID +NTAPI +HalReturnToFirmware( + FIRMWARE_REENTRY Action) +{ + UNIMPLEMENTED; +} + + +ULONG +NTAPI +HalSetBusData( + BUS_DATA_TYPE BusDataType, + ULONG BusNumber, + ULONG SlotNumber, + PVOID Buffer, + ULONG Length) +{ + UNIMPLEMENTED; + + return 0; +} + + +ULONG +NTAPI +HalSetBusDataByOffset( + BUS_DATA_TYPE BusDataType, + ULONG BusNumber, + ULONG SlotNumber, + PVOID Buffer, + ULONG Offset, + ULONG Length) +{ + UNIMPLEMENTED; + + return 0; +} + + +ARC_STATUS +NTAPI +HalSetEnvironmentVariable( + PCH Name, + PCH Value) +{ + UNIMPLEMENTED; + + return ESUCCESS; +} + + +BOOLEAN +NTAPI +HalSetRealTimeClock( + PTIME_FIELDS Time) +{ + UNIMPLEMENTED; + + return TRUE; +} + + +ULONG +NTAPI +HalSetTimeIncrement( + ULONG Increment) +{ + UNIMPLEMENTED; + + return Increment; +} + + +BOOLEAN +NTAPI +HalStartNextProcessor(IN PLOADER_PARAMETER_BLOCK LoaderBlock, + IN PKPROCESSOR_STATE ProcessorState) +{ + UNIMPLEMENTED; + + return TRUE; +} + + +ULONG +FASTCALL +HalSystemVectorDispatchEntry( + ULONG Unknown1, + ULONG Unknown2, + ULONG Unknown3) +{ + UNIMPLEMENTED; + + return 0; +} + + +BOOLEAN +NTAPI +HalTranslateBusAddress( + INTERFACE_TYPE InterfaceType, + ULONG BusNumber, + PHYSICAL_ADDRESS BusAddress, + PULONG AddressSpace, + PPHYSICAL_ADDRESS TranslatedAddress) +{ + UNIMPLEMENTED; + + return TRUE; +} + + +VOID +NTAPI +HalpAssignDriveLetters(IN struct _LOADER_PARAMETER_BLOCK *LoaderBlock, + IN PSTRING NtDeviceName, + OUT PUCHAR NtSystemPath, + OUT PSTRING NtSystemPathString) +{ + /* Call the kernel */ + IoAssignDriveLetters(LoaderBlock, + NtDeviceName, + NtSystemPath, + NtSystemPathString); +} + +NTSTATUS +NTAPI +HalpReadPartitionTable(IN PDEVICE_OBJECT DeviceObject, + IN ULONG SectorSize, + IN BOOLEAN ReturnRecognizedPartitions, + IN OUT PDRIVE_LAYOUT_INFORMATION *PartitionBuffer) +{ + /* Call the kernel */ + return IoReadPartitionTable(DeviceObject, + SectorSize, + ReturnRecognizedPartitions, + PartitionBuffer); +} + +NTSTATUS +NTAPI +HalpWritePartitionTable(IN PDEVICE_OBJECT DeviceObject, + IN ULONG SectorSize, + IN ULONG SectorsPerTrack, + IN ULONG NumberOfHeads, + IN PDRIVE_LAYOUT_INFORMATION PartitionBuffer) +{ + /* Call the kernel */ + return IoWritePartitionTable(DeviceObject, + SectorSize, + SectorsPerTrack, + NumberOfHeads, + PartitionBuffer); +} + +NTSTATUS +NTAPI +HalpSetPartitionInformation(IN PDEVICE_OBJECT DeviceObject, + IN ULONG SectorSize, + IN ULONG PartitionNumber, + IN ULONG PartitionType) +{ + /* Call the kernel */ + return IoSetPartitionInformation(DeviceObject, + SectorSize, + PartitionNumber, + PartitionType); +} + + +BOOLEAN +NTAPI +IoFlushAdapterBuffers( + PADAPTER_OBJECT AdapterObject, + PMDL Mdl, + PVOID MapRegisterBase, + PVOID CurrentVa, + ULONG Length, + BOOLEAN WriteToDevice) +{ + UNIMPLEMENTED; + + return TRUE; +} + + +VOID +NTAPI +IoFreeAdapterChannel( + PADAPTER_OBJECT AdapterObject) +{ + UNIMPLEMENTED; +} + + +VOID +NTAPI +IoFreeMapRegisters( + PADAPTER_OBJECT AdapterObject, + PVOID MapRegisterBase, + ULONG NumberOfMapRegisters) +{ + UNIMPLEMENTED; +} + + +PHYSICAL_ADDRESS +NTAPI +IoMapTransfer( + PADAPTER_OBJECT AdapterObject, + PMDL Mdl, + PVOID MapRegisterBase, + PVOID CurrentVa, + PULONG Length, + BOOLEAN WriteToDevice) +{ + PHYSICAL_ADDRESS Address; + + UNIMPLEMENTED; + + Address.QuadPart = 0; + + return Address; +} + +VOID +NTAPI +KeFlushWriteBuffer(VOID) +{ + UNIMPLEMENTED; +} + +LARGE_INTEGER +NTAPI +KeQueryPerformanceCounter( + PLARGE_INTEGER PerformanceFreq) +{ + LARGE_INTEGER Value; + + UNIMPLEMENTED; + + Value.QuadPart = 0; + + return Value; +} + +VOID +NTAPI +KeStallExecutionProcessor(IN ULONG Microseconds) +{ + SP804_CONTROL_REGISTER ControlRegister; + + // + // Enable the timer + // + WRITE_REGISTER_ULONG(TIMER1_LOAD, Microseconds); + + // + // Configure the timer + // + ControlRegister.AsUlong = 0; + ControlRegister.OneShot = TRUE; + ControlRegister.Wide = TRUE; + ControlRegister.Periodic = TRUE; + ControlRegister.Enabled = TRUE; + WRITE_REGISTER_ULONG(TIMER1_CONTROL, ControlRegister.AsUlong); + + // + // Now we will loop until the timer reached 0 + // + while (READ_REGISTER_ULONG(TIMER1_VALUE)); +} + +VOID +FASTCALL +KfLowerIrql(IN KIRQL NewIrql) +{ + ULONG InterruptMask; + ARM_STATUS_REGISTER Flags; + PKPCR Pcr = (PKPCR)KeGetPcr(); + + // + // Validate the new IRQL + // + Flags = KeArmStatusRegisterGet(); + _disable(); + ASSERT(NewIrql <= Pcr->CurrentIrql); + + // + // IRQLs are internally 8 bits + // + NewIrql &= 0xFF; + + // + // Setup the interrupt mask for this IRQL + // + InterruptMask = KeGetPcr()->IrqlTable[NewIrql]; +// DPRINT1("[LOWER] IRQL: %d InterruptMask: %lx\n", NewIrql, InterruptMask); + + // + // Clear interrupts associated to the old IRQL + // + WRITE_REGISTER_ULONG(VIC_INT_CLEAR, 0xFFFFFFFF); + + // + // Set the new interrupt mask + // PL190 VIC support only for now + // + WRITE_REGISTER_ULONG(VIC_INT_ENABLE, InterruptMask); + + // + // Save the new IRQL + // + Pcr->CurrentIrql = NewIrql; + if (!Flags.IrqDisable) _enable(); +} + +KIRQL +FASTCALL +KfRaiseIrql(IN KIRQL NewIrql) +{ + KIRQL OldIrql; + ULONG InterruptMask; + ARM_STATUS_REGISTER Flags; + PKPCR Pcr = (PKPCR)KeGetPcr(); + + // + // Save the current IRQL + // + Flags = KeArmStatusRegisterGet(); + _disable(); + OldIrql = Pcr->CurrentIrql; + + // + // IRQLs are internally 8 bits + // + NewIrql &= 0xFF; + + // + // Setup the interrupt mask for this IRQL + // + InterruptMask = KeGetPcr()->IrqlTable[NewIrql]; + // DPRINT1("[RAISE] IRQL: %d InterruptMask: %lx\n", NewIrql, InterruptMask); + ASSERT(NewIrql >= OldIrql); + + // + // Clear interrupts associated to the old IRQL + // + WRITE_REGISTER_ULONG(VIC_INT_CLEAR, 0xFFFFFFFF); + + // + // Set the new interrupt mask + // PL190 VIC support only for now + // + WRITE_REGISTER_ULONG(VIC_INT_ENABLE, InterruptMask); + + // + // Save the new IRQL + // + Pcr->CurrentIrql = NewIrql; + if (!Flags.IrqDisable) _enable(); + return OldIrql; +} + +VOID +NTAPI +READ_PORT_BUFFER_UCHAR( + PUCHAR Port, + PUCHAR Buffer, + ULONG Count) +{ + UNIMPLEMENTED; +} + + +VOID +NTAPI +READ_PORT_BUFFER_ULONG( + PULONG Port, + PULONG Buffer, + ULONG Count) +{ + UNIMPLEMENTED; +} + + +VOID +NTAPI +READ_PORT_BUFFER_USHORT( + PUSHORT Port, + PUSHORT Buffer, + ULONG Count) +{ + UNIMPLEMENTED; +} + + +UCHAR +NTAPI +READ_PORT_UCHAR( + PUCHAR Port) +{ + UNIMPLEMENTED; + + return 0; +} + + +ULONG +NTAPI +READ_PORT_ULONG( + PULONG Port) +{ + UNIMPLEMENTED; + + return 0; +} + + +USHORT +NTAPI +READ_PORT_USHORT( + PUSHORT Port) +{ + UNIMPLEMENTED; + + return 0; +} + + +VOID +NTAPI +WRITE_PORT_BUFFER_UCHAR( + PUCHAR Port, + PUCHAR Buffer, + ULONG Count) +{ + UNIMPLEMENTED; +} + + +VOID +NTAPI +WRITE_PORT_BUFFER_USHORT( + PUSHORT Port, + PUSHORT Buffer, + ULONG Count) +{ + UNIMPLEMENTED; +} + + +VOID +NTAPI +WRITE_PORT_BUFFER_ULONG( + PULONG Port, + PULONG Buffer, + ULONG Count) +{ + UNIMPLEMENTED; +} + + +VOID +NTAPI +WRITE_PORT_UCHAR( + PUCHAR Port, + UCHAR Value) +{ + UNIMPLEMENTED; +} + +VOID +NTAPI +WRITE_PORT_ULONG( + PULONG Port, + ULONG Value) +{ + UNIMPLEMENTED; +} + +VOID +NTAPI +WRITE_PORT_USHORT( + PUSHORT Port, + USHORT Value) +{ + UNIMPLEMENTED; +} + +KIRQL +KeRaiseIrqlToDpcLevel(VOID) +{ + // + // Call the generic routine + // + return KfRaiseIrql(DISPATCH_LEVEL); +} + +KIRQL +KeRaiseIrqlToSynchLevel(VOID) +{ + // + // Call the generic routine + // + return KfRaiseIrql(DISPATCH_LEVEL); +} + +BOOLEAN HalpProcessorIdentified; +BOOLEAN HalpTestCleanSupported; + +VOID +HalpIdentifyProcessor(VOID) +{ + ARM_ID_CODE_REGISTER IdRegister; + + // + // Don't do it again + // + HalpProcessorIdentified = TRUE; + + // + // Read the ID Code + // + IdRegister = KeArmIdCodeRegisterGet(); + + // + // Architecture "6" CPUs support test-and-clean (926EJ-S and 1026EJ-S) + // + HalpTestCleanSupported = (IdRegister.Architecture == 6); +} + +VOID +HalSweepDcache(VOID) +{ + // + // We get called very early on, before HalInitSystem or any of the Hal* + // processor routines, so we need to figure out what CPU we're on. + // + if (!HalpProcessorIdentified) HalpIdentifyProcessor(); + + // + // Check if we can do it the ARMv5TE-J way + // + if (HalpTestCleanSupported) + { + // + // Test, clean, flush D-Cache + // + __asm__ __volatile__ ("1: mrc p15, 0, pc, c7, c14, 3; bne 1b"); + } + else + { + // + // We need to do it it by set/way + // + UNIMPLEMENTED; + } +} + +VOID +HalSweepIcache(VOID) +{ + // + // All ARM cores support the same Icache flush command, no need for HAL work + // + KeArmFlushIcache(); +} + +/* + * @implemented + */ +#undef KeGetCurrentIrql +KIRQL +NTAPI +KeGetCurrentIrql(VOID) +{ + /* Return IRQL */ + return PCR->CurrentIrql; +} + +/* + * @implemented + */ +VOID +NTAPI +KeLowerIrql(KIRQL NewIrql) +{ + /* Call the fastcall function */ + KfLowerIrql(NewIrql); +} + +/* + * @implemented + */ +VOID +NTAPI +KeRaiseIrql(KIRQL NewIrql, + PKIRQL OldIrql) +{ + /* Call the fastcall function */ + *OldIrql = KfRaiseIrql(NewIrql); +} + +/* + * @implemented + */ +VOID +NTAPI +KeAcquireSpinLock(PKSPIN_LOCK SpinLock, + PKIRQL OldIrql) +{ + /* Call the fastcall function */ + *OldIrql = KfAcquireSpinLock(SpinLock); +} + +/* + * @implemented + */ +KIRQL +FASTCALL +KeAcquireSpinLockRaiseToSynch(PKSPIN_LOCK SpinLock) +{ + /* Simply raise to dispatch */ + return KfRaiseIrql(DISPATCH_LEVEL); +} + +/* + * @implemented + */ +VOID +NTAPI +KeReleaseSpinLock(PKSPIN_LOCK SpinLock, + KIRQL NewIrql) +{ + /* Call the fastcall function */ + KfReleaseSpinLock(SpinLock, NewIrql); +} + +/* + * @implemented + */ +KIRQL +FASTCALL +KfAcquireSpinLock(PKSPIN_LOCK SpinLock) +{ + /* Simply raise to dispatch */ + return KfRaiseIrql(DISPATCH_LEVEL); +} + +/* + * @implemented + */ +VOID +FASTCALL +KfReleaseSpinLock(PKSPIN_LOCK SpinLock, + KIRQL OldIrql) +{ + /* Simply lower IRQL back */ + KfLowerIrql(OldIrql); +} + +/* + * @implemented + */ +KIRQL +FASTCALL +KeAcquireQueuedSpinLock(IN KSPIN_LOCK_QUEUE_NUMBER LockNumber) +{ + /* Simply raise to dispatch */ + return KfRaiseIrql(DISPATCH_LEVEL); +} + +/* + * @implemented + */ +KIRQL +FASTCALL +KeAcquireQueuedSpinLockRaiseToSynch(IN KSPIN_LOCK_QUEUE_NUMBER LockNumber) +{ + /* Simply raise to dispatch */ + return KfRaiseIrql(DISPATCH_LEVEL); +} + +/* + * @implemented + */ +VOID +FASTCALL +KeAcquireInStackQueuedSpinLock(IN PKSPIN_LOCK SpinLock, + IN PKLOCK_QUEUE_HANDLE LockHandle) +{ + /* Simply raise to dispatch */ + LockHandle->OldIrql = KfRaiseIrql(DISPATCH_LEVEL); +} + +/* + * @implemented + */ +VOID +FASTCALL +KeAcquireInStackQueuedSpinLockRaiseToSynch(IN PKSPIN_LOCK SpinLock, + IN PKLOCK_QUEUE_HANDLE LockHandle) +{ + /* Simply raise to synch */ + LockHandle->OldIrql = KfRaiseIrql(DISPATCH_LEVEL); +} + +/* + * @implemented + */ +VOID +FASTCALL +KeReleaseQueuedSpinLock(IN KSPIN_LOCK_QUEUE_NUMBER LockNumber, + IN KIRQL OldIrql) +{ + /* Simply lower IRQL back */ + KfLowerIrql(OldIrql); +} + +/* + * @implemented + */ +VOID +FASTCALL +KeReleaseInStackQueuedSpinLock(IN PKLOCK_QUEUE_HANDLE LockHandle) +{ + /* Simply lower IRQL back */ + KfLowerIrql(LockHandle->OldIrql); +} + +/* + * @implemented + */ +BOOLEAN +FASTCALL +KeTryToAcquireQueuedSpinLockRaiseToSynch(IN KSPIN_LOCK_QUEUE_NUMBER LockNumber, + IN PKIRQL OldIrql) +{ + /* Simply raise to dispatch */ + *OldIrql = KfRaiseIrql(DISPATCH_LEVEL); + + /* Always return true on UP Machines */ + return TRUE; +} + +/* + * @implemented + */ +LOGICAL +FASTCALL +KeTryToAcquireQueuedSpinLock(IN KSPIN_LOCK_QUEUE_NUMBER LockNumber, + OUT PKIRQL OldIrql) +{ + /* Simply raise to dispatch */ + *OldIrql = KfRaiseIrql(DISPATCH_LEVEL); + + /* Always return true on UP Machines */ + return TRUE; +} + +/* EOF */ diff --git a/reactos/hal/halamd64/generic/halinit.c b/reactos/hal/halamd64/generic/halinit.c new file mode 100644 index 00000000000..d3d834bf19a --- /dev/null +++ b/reactos/hal/halamd64/generic/halinit.c @@ -0,0 +1,170 @@ +/* + * PROJECT: ReactOS HAL + * LICENSE: GPL - See COPYING in the top level directory + * FILE: hal/halx86/generic/halinit.c + * PURPOSE: HAL Entrypoint and Initialization + * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org) + */ + +/* INCLUDES ******************************************************************/ + +#include +#define NDEBUG +#include + +/* GLOBALS *******************************************************************/ + +BOOLEAN HalpPciLockSettings; + +/* PRIVATE FUNCTIONS *********************************************************/ + +VOID +NTAPI +HalpGetParameters(IN PLOADER_PARAMETER_BLOCK LoaderBlock) +{ + PCHAR CommandLine; + + /* Make sure we have a loader block and command line */ + if ((LoaderBlock) && (LoaderBlock->LoadOptions)) + { + /* Read the command line */ + CommandLine = LoaderBlock->LoadOptions; + + /* Check if PCI is locked */ + if (strstr(CommandLine, "PCILOCK")) HalpPciLockSettings = TRUE; + + /* Check for initial breakpoint */ + if (strstr(CommandLine, "BREAK")) DbgBreakPoint(); + } +} + +/* FUNCTIONS *****************************************************************/ + +NTSTATUS +NTAPI +DriverEntry( + PDRIVER_OBJECT DriverObject, + PUNICODE_STRING RegistryPath) +{ + UNIMPLEMENTED; + + return STATUS_SUCCESS; +} + +/* + * @implemented + */ +BOOLEAN +NTAPI +HalInitSystem(IN ULONG BootPhase, + IN PLOADER_PARAMETER_BLOCK LoaderBlock) +{ + PKPRCB Prcb = KeGetCurrentPrcb(); + + /* Check the boot phase */ + if (!BootPhase) + { + /* Phase 0... save bus type */ + HalpBusType = LoaderBlock->u.I386.MachineType & 0xFF; + + /* Get command-line parameters */ + HalpGetParameters(LoaderBlock); + + /* Checked HAL requires checked kernel */ +#if DBG + if (!(Prcb->BuildType & PRCB_BUILD_DEBUG)) + { + /* No match, bugcheck */ + KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 1, 0); + } +#else + /* Release build requires release HAL */ + if (Prcb->BuildType & PRCB_BUILD_DEBUG) + { + /* No match, bugcheck */ + KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 0, 0); + } +#endif + +#ifdef CONFIG_SMP + /* SMP HAL requires SMP kernel */ + if (Prcb->BuildType & PRCB_BUILD_UNIPROCESSOR) + { + /* No match, bugcheck */ + KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 0, 0); + } +#endif + + /* Validate the PRCB */ + if (Prcb->MajorVersion != PRCB_MAJOR_VERSION) + { + /* Validation failed, bugcheck */ + KeBugCheckEx(MISMATCHED_HAL, 1, Prcb->MajorVersion, 1, 0); + } +DPRINT1("HalInitSystem 2\n"); + /* Initialize the PICs */ + HalpInitPICs(); +DPRINT1("HalInitSystem 3\n"); + /* Force initial PIC state */ + KfRaiseIrql(KeGetCurrentIrql()); +DPRINT1("HalInitSystem 4\n"); + /* Initialize the clock */ + HalpInitializeClock(); +DPRINT1("HalInitSystem 5\n"); + /* Setup busy waiting */ + //HalpCalibrateStallExecution(); + + /* Fill out the dispatch tables */ + HalQuerySystemInformation = HaliQuerySystemInformation; + HalSetSystemInformation = HaliSetSystemInformation; + HalInitPnpDriver = NULL; // FIXME: TODO +// HalGetDmaAdapter = HalpGetDmaAdapter; + HalGetInterruptTranslator = NULL; // FIXME: TODO +// HalResetDisplay = HalpBiosDisplayReset; +DPRINT1("HalInitSystem 6\n"); + /* Initialize the hardware lock (CMOS) */ + KeInitializeSpinLock(&HalpSystemHardwareLock); + + /* Do some HAL-specific initialization */ + HalpInitPhase0(LoaderBlock); + } + else if (BootPhase == 1) + { + /* Initialize the default HAL stubs for bus handling functions */ + HalpInitNonBusHandler(); + + /* Enable the clock interrupt */ + PKIDTENTRY64 IdtEntry = &((PKIPCR)KeGetPcr())->IdtBase[0x30]; + IdtEntry->OffsetLow = (((ULONG_PTR)HalpClockInterrupt) & 0xFFFF); + IdtEntry->OffsetMiddle = (((ULONG_PTR)HalpClockInterrupt >> 16) & 0xFFFF); + IdtEntry->OffsetHigh = ((ULONG_PTR)HalpClockInterrupt >> 32); +// HalEnableSystemInterrupt(0x30, CLOCK_LEVEL, Latched); + + /* Initialize DMA. NT does this in Phase 0 */ + HalpInitDma(); + + /* Do some HAL-specific initialization */ + HalpInitPhase1(); + } + + /* All done, return */ + return TRUE; +} + +/* + * @unimplemented + */ +VOID +NTAPI +HalReportResourceUsage(VOID) +{ + /* Initialize PCI bus. */ + HalpInitializePciBus(); + + /* FIXME: This is done in ReactOS MP HAL only*/ + //HaliReconfigurePciInterrupts(); + + /* FIXME: Report HAL Usage to kernel */ +} + +/* EOF */ diff --git a/reactos/hal/halamd64/generic/irq.S b/reactos/hal/halamd64/generic/irq.S new file mode 100644 index 00000000000..1d5bb59861f --- /dev/null +++ b/reactos/hal/halamd64/generic/irq.S @@ -0,0 +1,91 @@ +/* + * FILE: hal/halx86/generic/irq.S + * COPYRIGHT: See COPYING in the top level directory + * PURPOSE: Software, System and Hardware IRQ Management + * PROGRAMMER: Alex Ionescu (alex@relsoft.net) + */ + +/* INCLUDES ******************************************************************/ + +#include +#include +.intel_syntax noprefix + +.macro UNIMPLEMENTED func + jmp 2f +1: + .ascii "Sorry, asm function " + .ascii func + .ascii " is unimplemented!\n\0" +2: + movabs rcx, offset 1b + call _DbgPrint + ret +.endm + + + +/* GLOBALS *******************************************************************/ + + + +/* FUNCTIONS *****************************************************************/ + +.globl _HalpInitPICs +.func _HalpInitPICs +_HalpInitPICs: + UNIMPLEMENTED "HalpInitPICs" +.endfunc + +.global _HalEnableInterrupt +.func _HalEnableInterrupt +_HalEnableInterrupt: + UNIMPLEMENTED "HalEnableInterrupt" +.endfunc + +.global _HalDisableInterrupt +.func _HalDisableInterrupt +_HalDisableInterrupt: + UNIMPLEMENTED "HalDisableInterrupt" +.endfunc + +.global _HalRequestSoftwareInterrupt +.func _HalRequestSoftwareInterrupt +_HalRequestSoftwareInterrupt: + UNIMPLEMENTED "HalRequestSoftwareInterrupt" +.endfunc + +.global _HalSendSoftwareInterrupt +.func _HalSendSoftwareInterrupt +_HalSendSoftwareInterrupt: + UNIMPLEMENTED "HalSendSoftwareInterrupt" +.endfunc + +.global _HalEndSystemInterrupt +.func _HalEndSystemInterrupt +_HalEndSystemInterrupt: + UNIMPLEMENTED "HalEndSystemInterrupt" +.endfunc + + +.globl _HalClearSoftwareInterrupt +.func _HalClearSoftwareInterrupt +_HalClearSoftwareInterrupt: + UNIMPLEMENTED "HalClearSoftwareInterrupt" + + /* Get IRR mask */ + mov eax, 1 + shl eax, cl + not eax + + /* Set IRR */ +// and gs:[KPCR_IRR], eax + ret +.endfunc + +.globl _HalBeginSystemInterrupt +.func _HalBeginSystemInterrupt +_HalBeginSystemInterrupt: + UNIMPLEMENTED "HalBeginSystemInterrupt" +.endfunc + diff --git a/reactos/hal/halamd64/generic/misc.c b/reactos/hal/halamd64/generic/misc.c new file mode 100644 index 00000000000..7eb1d9170f9 --- /dev/null +++ b/reactos/hal/halamd64/generic/misc.c @@ -0,0 +1,105 @@ +/* + * PROJECT: ReactOS HAL + * LICENSE: GPL - See COPYING in the top level directory + * FILE: hal/halx86/generic/misc.c + * PURPOSE: Miscellanous Routines + * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org) + * Eric Kohl (ekohl@abo.rhein-zeitung.de) + */ + +/* INCLUDES ******************************************************************/ + +#include +#define NDEBUG +#include + +/* PRIVATE FUNCTIONS *********************************************************/ + +VOID +NTAPI +HalpCheckPowerButton(VOID) +{ + /* Nothing to do on non-ACPI */ + return; +} + +PVOID +NTAPI +HalpMapPhysicalMemory64(IN PHYSICAL_ADDRESS PhysicalAddress, + IN ULONG NumberPage) +{ + /* Use kernel memory manager I/O map facilities */ + return MmMapIoSpace(PhysicalAddress, + NumberPage << PAGE_SHIFT, + MmNonCached); +} + +VOID +NTAPI +HalpUnmapVirtualAddress(IN PVOID VirtualAddress, + IN ULONG NumberPages) +{ + /* Use kernel memory manager I/O map facilities */ + MmUnmapIoSpace(VirtualAddress, NumberPages << PAGE_SHIFT); +} + +/* FUNCTIONS *****************************************************************/ + +/* + * @implemented + */ +VOID +NTAPI +HalHandleNMI(IN PVOID NmiInfo) +{ + UCHAR ucStatus; + + /* Get the NMI Flag */ + ucStatus = READ_PORT_UCHAR((PUCHAR)0x61); + + /* Display NMI failure string */ + HalDisplayString ("\n*** Hardware Malfunction\n\n"); + HalDisplayString ("Call your hardware vendor for support\n\n"); + + /* Check for parity error */ + if (ucStatus & 0x80) + { + /* Display message */ + HalDisplayString ("NMI: Parity Check / Memory Parity Error\n"); + } + + /* Check for I/O failure */ + if (ucStatus & 0x40) + { + /* Display message */ + HalDisplayString ("NMI: Channel Check / IOCHK\n"); + } + + /* Halt the system */ + HalDisplayString("\n*** The system has halted ***\n"); + //KeEnterKernelDebugger(); +} + +/* + * @implemented + */ +BOOLEAN +FASTCALL +HalSystemVectorDispatchEntry(IN ULONG Vector, + OUT PKINTERRUPT_ROUTINE **FlatDispatch, + OUT PKINTERRUPT_ROUTINE *NoConnection) +{ + /* Not implemented on x86 */ + return FALSE; +} + +/* + * @implemented + */ +VOID +NTAPI +KeFlushWriteBuffer(VOID) +{ + /* Not implemented on x86 */ + return; +} diff --git a/reactos/hal/halamd64/generic/mps.S b/reactos/hal/halamd64/generic/mps.S new file mode 100644 index 00000000000..219d651498c --- /dev/null +++ b/reactos/hal/halamd64/generic/mps.S @@ -0,0 +1,95 @@ +/* + * COPYRIGHT: See COPYING in the top level directory + * PROJECT: ReactOS kernel + * FILE: ntoskrnl/hal/amd64/generic/mps.S + * PURPOSE: Intel MultiProcessor specification support + * PROGRAMMER: Casper S. Hornstrup (chorns@users.sourceforge.net) + */ + +/* INCLUDES ******************************************************************/ + +#include + +/* FUNCTIONS *****************************************************************/ + +#define BEFORE \ + cld; \ + pushq %rax; \ + pushq %rbx; \ + pushq %rcx; \ + pushq %rdx; \ + pushq %rsi; \ + pushq %rdi; \ + pushq %fs; \ + pushq %gs; \ + +#define AFTER \ + popq %gs; \ + popq %fs; \ + popq %rdi; \ + popq %rsi; \ + popq %rdx; \ + popq %rcx; \ + popq %rbx; \ + popq %rax; \ + +#ifdef CONFIG_SMP +.global _MpsIpiInterrupt +_MpsIpiInterrupt: + /* Save registers */ + BEFORE + + /* Call the C handler */ + call _MpsIpiHandler + + /* Return to the caller */ + AFTER + iret +#endif + +.globl _MpsErrorInterrupt +_MpsErrorInterrupt: + /* Save registers */ + BEFORE + + /* Call the C handler */ + call _MpsErrorHandler + + /* Return to the caller */ + AFTER + iret + + +.globl _MpsSpuriousInterrupt +_MpsSpuriousInterrupt: + /* Save registers */ + BEFORE + + /* Call the C handler */ + call _MpsSpuriousHandler + + /* Return to the caller */ + AFTER + iret + +.global _MpsTimerInterrupt +_MpsTimerInterrupt: + /* Save registers */ + BEFORE + + movl $0xef,%ebx + movl $0xceafbeef,%eax + pushq %rax + pushq %rsp + pushq %rbx + call _MpsTimerHandler + popq %rax + popq %rax + popq %rax + + /* Return to the caller */ + AFTER + iret + + +/* EOF */ diff --git a/reactos/hal/halamd64/generic/systimer.S b/reactos/hal/halamd64/generic/systimer.S new file mode 100644 index 00000000000..298cea2619f --- /dev/null +++ b/reactos/hal/halamd64/generic/systimer.S @@ -0,0 +1,258 @@ +/* + * FILE: hal/halx86/generic/timer.S + * COPYRIGHT: See COPYING in the top level directory + * PURPOSE: System Timer Interrupt and Management + * PROGRAMMER: Alex Ionescu (alex@relsoft.net) + */ + +/* INCLUDES ******************************************************************/ + +#include +#include +.intel_syntax noprefix + +/* GLOBALS *******************************************************************/ + +_HalpLastPerfCounterLow: .long 0 +_HalpLastPerfCounterHigh: .long 0 +_HalpPerfCounterLow: .long 0 +_HalpPerfCounterHigh: .long 0 + +_UnhandledMsg: + .asciz "\n\x7\x7!!! Unhandled or Unexpected Code at line: %lx!!!\n" + +/* FUNCTIONS *****************************************************************/ + +.globl _KeStallExecutionProcessor +.func KeStallExecutionProcessor +_KeStallExecutionProcessor: + + /* Get the number of microseconds required */ + jecxz Done + + /* Multiply by the stall factor */ + mov eax, gs:[KPCR_STALL_SCALE_FACTOR] + mul ecx + + /* Align to 16 bytes */ + .align 16 + + /* Jump to subtraction loop */ + jmp SubtractLoop + + /* Align to 16 bytes */ + .align 16 + + /* Subtract one count */ +SubtractLoop: + sub eax, 1 + jnz SubtractLoop + +Done: + /* Return */ + ret 4 +.endfunc + +.global _KeQueryPerformanceCounter +.func KeQueryPerformanceCounter +_KeQueryPerformanceCounter: + + /* Check if we were called too early */ + cmp dword ptr _HalpCurrentRollOver, 0 + je NoCount + + /* Save volatiles */ + push rbx + push rsi + +LoopPreInt: + + /* Disable interrupts */ + pushf + cli + +LoopPostInt: + + /* Get the current value */ + mov ebx, _HalpPerfCounterLow + mov esi, _HalpPerfCounterHigh + + /* Read 8254 timer */ + mov al, 0 + out 0x43, al + jmp $+2 + in al, 0x40 + jmp $+2 + movzx ecx, al + in al, 0x40 + mov ch, al + + /* Enable interrupts and do a short wait */ + popf + nop + jmp $+2 + + /* Disable them again */ + pushf + cli + + /* Get the counter value again */ + mov eax, _HalpPerfCounterLow + mov edx, _HalpPerfCounterHigh + + /* Check if someone updated the counter */ + cmp eax, ebx + jnz LoopPostInt + cmp edx, esi + jnz LoopPostInt + + /* Check if the current 8254 value causes rollover */ + neg ecx + add ecx, _HalpCurrentRollOver + jnb DoRollOver + +SetSum: + + /* Calculate the sum */ + add eax, ecx + adc edx, 0 + + /* Check if we're above or below the last high value */ + cmp edx, _HalpLastPerfCounterHigh + jb short BelowHigh + jnz short BelowLow + + /* Check if we're above or below the last low value */ + cmp eax, _HalpLastPerfCounterLow + jb BelowHigh + +BelowLow: + + /* Update the last value and bring back interrupts */ + mov _HalpLastPerfCounterLow, eax + mov _HalpLastPerfCounterHigh, edx + popf + + /* Check if caller wants frequency */ + cmp dword ptr [esp+12], 0 + jz ReturnNoFreq + + /* Save hard-coded frequency */ + mov ecx, dword ptr [esp+12] + mov dword ptr [ecx], 1193182 + mov dword ptr [ecx+4], 0 + +ReturnNoFreq: + + /* Restore volatiles */ + pop rsi + pop rbx + ret 4 + +NoCount: + + /* Return empty, called too soon */ + mov eax, 0 + mov edx, 0 + ret 4 + +DoRollOver: + + /* We might have an incoming interrupt, save EFLAGS and reset rollover */ + mov esi, [esp] + mov ecx, _HalpCurrentRollOver + popf + + /* Check if interrupts were enabled and try again */ + test esi, EFLAGS_INTERRUPT_MASK + jnz LoopPreInt + + /* They're not, continue where we left */ + pushf + jmp SetSum + +BelowHigh: + + /* Get the last counter values */ + mov ebx, _HalpLastPerfCounterLow + mov esi, _HalpLastPerfCounterHigh + + /* Check if the previous value was 0 and go back if yes */ + mov ecx, ebx + or ecx, esi + jz BelowLow + + /* Make sure that the count is still valid */ + sub ebx, eax + sbb esi, edx + jnz InvalidCount + cmp ebx, _HalpCurrentRollOver + jg InvalidCount + + /* Fixup the count with the last known value */ + sub eax, ebx + sbb edx, esi + + /* We might have an incoming interrupt, save EFLAGS */ + mov ecx, [esp] + popf + + /* Check if interrupts were enabled and try again */ + test ecx, EFLAGS_INTERRUPT_MASK + jnz LoopPreInt + + /* They're not, continue where we left */ + pushf + jmp BelowLow + +InvalidCount: + popf + xor eax, eax + mov _HalpLastPerfCounterLow, eax + mov _HalpLastPerfCounterHigh, eax + jmp LoopPreInt +.endfunc + +.globl _HalpClockInterrupt +.func HalpClockInterrupt +//TRAP_FIXUPS hci_a, hci_t, DoFixupV86, DoFixupAbios +_HalpClockInterrupt: + + /* Enter trap */ +// INT_PROLOG hci_a, hci_t, DoPushFakeErrorCode + + /* Push vector and make stack for IRQL */ + push 0x30 + sub esp, 4 + + /* Begin the interrupt */ + push rsp + push 0x30 + push CLOCK_LEVEL +// call _HalBeginSystemInterrupt + + /* Check if it's spurious */ + or al, al + jz Spurious + + /* Update the performance counter */ + xor ebx, ebx + mov eax, _HalpCurrentRollOver + add _HalpPerfCounterLow, eax + adc _HalpPerfCounterHigh, ebx + + /* Get the time increment and check if someone changed the clock rate */ + mov eax, _HalpCurrentTimeIncrement + cmp _HalpClockSetMSRate, ebx + jz _KeUpdateSystemTime + + /* FIXME: Someone did! */ + int 3 + +Spurious: + + /* Exit the interrupt */ + add esp, 8 +// jmp _Kei386EoiHelper +.endfunc + diff --git a/reactos/hal/halamd64/hal_generic.c b/reactos/hal/halamd64/hal_generic.c new file mode 100644 index 00000000000..a5aa4488c65 --- /dev/null +++ b/reactos/hal/halamd64/hal_generic.c @@ -0,0 +1,34 @@ +/* + * PROJECT: ReactOS HAL + * LICENSE: GPL - See COPYING in the top level directory + * FILE: hal/halamd64/ + * PURPOSE: I/O HAL Routines for Disk Access + * PROGRAMMERS: Timo Kreuzer (timo.kreuzer@reactos.org) + */ + +/* INCLUDES ******************************************************************/ + +#include +#define NDEBUG +#include + +/* FUNCTIONS *****************************************************************/ + + + + +NTSTATUS +NTAPI +HalpSetPartitionInformation(IN PDEVICE_OBJECT DeviceObject, + IN ULONG SectorSize, + IN ULONG PartitionNumber, + IN ULONG PartitionType) +{ + /* Call the kernel */ + return IoSetPartitionInformation(DeviceObject, + SectorSize, + PartitionNumber, + PartitionType); +} + + diff --git a/reactos/hal/halamd64/hal_generic.rbuild b/reactos/hal/halamd64/hal_generic.rbuild new file mode 100644 index 00000000000..1e0fdc00088 --- /dev/null +++ b/reactos/hal/halamd64/hal_generic.rbuild @@ -0,0 +1,11 @@ + + + + + include + include + + + hal_generic.c + + diff --git a/reactos/hal/halamd64/include/bus.h b/reactos/hal/halamd64/include/bus.h new file mode 100644 index 00000000000..9f58d4055e0 --- /dev/null +++ b/reactos/hal/halamd64/include/bus.h @@ -0,0 +1,296 @@ +#ifndef __INTERNAL_HAL_BUS_H +#define __INTERNAL_HAL_BUS_H + +// +// Helper Macros +// +#define PASTE2(x,y) x ## y +#define POINTER_TO_(x) PASTE2(P,x) +#define READ_FROM(x) PASTE2(READ_PORT_, x) +#define WRITE_TO(x) PASTE2(WRITE_PORT_, x) + +// +// Declares a PCI Register Read/Write Routine +// +#define TYPE_DEFINE(x, y) \ + ULONG \ + NTAPI \ + x( \ + IN PPCIPBUSDATA BusData, \ + IN y PciCfg, \ + IN PUCHAR Buffer, \ + IN ULONG Offset \ + ) +#define TYPE1_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS); +#define TYPE2_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS); + +// +// Defines a PCI Register Read/Write Type 1 Routine Prologue and Epilogue +// +#define TYPE1_START(x, y) \ + TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS) \ +{ \ + ULONG i = Offset % sizeof(ULONG); \ + PciCfg->u.bits.RegisterNumber = Offset / sizeof(ULONG); \ + WRITE_PORT_ULONG(BusData->Config.Type1.Address, PciCfg->u.AsULONG); +#define TYPE1_END(y) \ + return sizeof(y); } +#define TYPE2_END TYPE1_END + +// +// PCI Register Read Type 1 Routine +// +#define TYPE1_READ(x, y) \ + TYPE1_START(x, y) \ + *((POINTER_TO_(y))Buffer) = \ + READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i)); \ + TYPE1_END(y) + +// +// PCI Register Write Type 1 Routine +// +#define TYPE1_WRITE(x, y) \ + TYPE1_START(x, y) \ + WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i), \ + *((POINTER_TO_(y))Buffer)); \ + TYPE1_END(y) + +// +// Defines a PCI Register Read/Write Type 2 Routine Prologue and Epilogue +// +#define TYPE2_START(x, y) \ + TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS) \ +{ \ + PciCfg->u.bits.RegisterNumber = (USHORT)Offset; + +// +// PCI Register Read Type 2 Routine +// +#define TYPE2_READ(x, y) \ + TYPE2_START(x, y) \ + *((POINTER_TO_(y))Buffer) = \ + READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT); \ + TYPE2_END(y) + +// +// PCI Register Write Type 2 Routine +// +#define TYPE2_WRITE(x, y) \ + TYPE2_START(x, y) \ + WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT, \ + *((POINTER_TO_(y))Buffer)); \ + TYPE2_END(y) + +typedef struct _PCIPBUSDATA +{ + PCIBUSDATA CommonData; + union + { + struct + { + PULONG Address; + ULONG Data; + } Type1; + struct + { + PUCHAR CSE; + PUCHAR Forward; + ULONG Base; + } Type2; + } Config; + ULONG MaxDevice; +} PCIPBUSDATA, *PPCIPBUSDATA; + +typedef ULONG +(NTAPI *FncConfigIO)( + IN PPCIPBUSDATA BusData, + IN PVOID State, + IN PUCHAR Buffer, + IN ULONG Offset +); + +typedef VOID +(NTAPI *FncSync)( + IN PBUS_HANDLER BusHandler, + IN PCI_SLOT_NUMBER Slot, + IN PKIRQL Irql, + IN PVOID State +); + +typedef VOID +(NTAPI *FncReleaseSync)( + IN PBUS_HANDLER BusHandler, + IN KIRQL Irql +); + +typedef struct _PCI_CONFIG_HANDLER +{ + FncSync Synchronize; + FncReleaseSync ReleaseSynchronzation; + FncConfigIO ConfigRead[3]; + FncConfigIO ConfigWrite[3]; +} PCI_CONFIG_HANDLER, *PPCI_CONFIG_HANDLER; + +typedef struct _PCI_REGISTRY_INFO_INTERNAL +{ + UCHAR MajorRevision; + UCHAR MinorRevision; + UCHAR NoBuses; + UCHAR HardwareMechanism; + ULONG ElementCount; + PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY]; +} PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL; + +/* FUNCTIONS *****************************************************************/ + +VOID +NTAPI +HalpPCISynchronizeType1( + IN PBUS_HANDLER BusHandler, + IN PCI_SLOT_NUMBER Slot, + IN PKIRQL Irql, + IN PPCI_TYPE1_CFG_BITS PciCfg +); + +VOID +NTAPI +HalpPCIReleaseSynchronzationType1( + IN PBUS_HANDLER BusHandler, + IN KIRQL Irql +); + +VOID +NTAPI +HalpPCISynchronizeType2( + IN PBUS_HANDLER BusHandler, + IN PCI_SLOT_NUMBER Slot, + IN PKIRQL Irql, + IN PPCI_TYPE2_ADDRESS_BITS PciCfg +); + +VOID +NTAPI +HalpPCIReleaseSynchronizationType2( + IN PBUS_HANDLER BusHandler, + IN KIRQL Irql +); + +TYPE1_DEFINE(HalpPCIReadUcharType1); +TYPE1_DEFINE(HalpPCIReadUshortType1); +TYPE1_DEFINE(HalpPCIReadUlongType1); +TYPE2_DEFINE(HalpPCIReadUcharType2); +TYPE2_DEFINE(HalpPCIReadUshortType2); +TYPE2_DEFINE(HalpPCIReadUlongType2); +TYPE1_DEFINE(HalpPCIWriteUcharType1); +TYPE1_DEFINE(HalpPCIWriteUshortType1); +TYPE1_DEFINE(HalpPCIWriteUlongType1); +TYPE2_DEFINE(HalpPCIWriteUcharType2); +TYPE2_DEFINE(HalpPCIWriteUshortType2); +TYPE2_DEFINE(HalpPCIWriteUlongType2); + +BOOLEAN +NTAPI +HalpValidPCISlot( + IN PBUS_HANDLER BusHandler, + IN PCI_SLOT_NUMBER Slot +); + +VOID +NTAPI +HalpReadPCIConfig( + IN PBUS_HANDLER BusHandler, + IN PCI_SLOT_NUMBER Slot, + IN PVOID Buffer, + IN ULONG Offset, + IN ULONG Length +); + +VOID +NTAPI +HalpWritePCIConfig( + IN PBUS_HANDLER BusHandler, + IN PCI_SLOT_NUMBER Slot, + IN PVOID Buffer, + IN ULONG Offset, + IN ULONG Length +); + +ULONG +NTAPI +HalpGetSystemInterruptVector( + ULONG BusNumber, + ULONG BusInterruptLevel, + ULONG BusInterruptVector, + PKIRQL Irql, + PKAFFINITY Affinity +); + +ULONG +NTAPI +HalpGetCmosData( + IN ULONG BusNumber, + IN ULONG SlotNumber, + IN PVOID Buffer, + IN ULONG Length +); + +ULONG +NTAPI +HalpSetCmosData( + IN ULONG BusNumber, + IN ULONG SlotNumber, + IN PVOID Buffer, + IN ULONG Length +); + +ULONG +NTAPI +HalpGetPCIData( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootBusHandler, + IN PCI_SLOT_NUMBER SlotNumber, + IN PUCHAR Buffer, + IN ULONG Offset, + IN ULONG Length +); + +ULONG +NTAPI +HalpSetPCIData( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootBusHandler, + IN PCI_SLOT_NUMBER SlotNumber, + IN PUCHAR Buffer, + IN ULONG Offset, + IN ULONG Length +); + +NTSTATUS +NTAPI +HalpAssignPCISlotResources( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootHandler, + IN PUNICODE_STRING RegistryPath, + IN PUNICODE_STRING DriverClassName OPTIONAL, + IN PDRIVER_OBJECT DriverObject, + IN PDEVICE_OBJECT DeviceObject OPTIONAL, + IN ULONG Slot, + IN OUT PCM_RESOURCE_LIST *pAllocatedResources +); + +VOID +NTAPI +HalpInitializePciBus( + VOID +); + +extern ULONG HalpBusType; +extern BOOLEAN HalpPCIConfigInitialized; +extern BUS_HANDLER HalpFakePciBusHandler; +extern ULONG HalpMinPciBus, HalpMaxPciBus; + +#endif /* __INTERNAL_HAL_BUS_H */ + +/* EOF */ + + diff --git a/reactos/hal/halamd64/include/hal.h b/reactos/hal/halamd64/include/hal.h new file mode 100644 index 00000000000..c793782d06a --- /dev/null +++ b/reactos/hal/halamd64/include/hal.h @@ -0,0 +1,52 @@ +/* + * COPYRIGHT: See COPYING in the top level directory + * PROJECT: ReactOS Hardware Abstraction Layer + * FILE: hal/halx86/include/hal.h + * PURPOSE: HAL Header + * PROGRAMMER: Alex Ionescu (alex@relsoft.net) + */ + +/* INCLUDES ******************************************************************/ + +/* C Headers */ +#include + +/* WDK HAL Compilation hack */ +#ifdef _MSC_VER +#include +#include +#undef _NTHAL_ +#undef DECLSPEC_IMPORT +#define DECLSPEC_IMPORT +#define __declspec(dllimport) +#endif + +/* IFS/DDK/NDK Headers */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Internal kernel headers */ +#include "internal/pci.h" +#include "internal/i386/intrin_i.h" + +/* Internal HAL Headers */ +//#include "apic.h" +#include "bus.h" +//#include "halirq.h" +//#include "haldma.h" +#include "halp.h" +//#include "mps.h" +//#include "ioapic.h" + +/* Helper Header */ +#include + +/* EOF */ diff --git a/reactos/hal/halamd64/include/halp.h b/reactos/hal/halamd64/include/halp.h new file mode 100644 index 00000000000..bac9ef1e7c9 --- /dev/null +++ b/reactos/hal/halamd64/include/halp.h @@ -0,0 +1,172 @@ +/* + * + */ + +#ifndef __INTERNAL_HAL_HAL_H +#define __INTERNAL_HAL_HAL_H + +#define HAL_APC_REQUEST 0 +#define HAL_DPC_REQUEST 1 + +/* CMOS Registers and Ports */ +#define CMOS_CONTROL_PORT (PUCHAR)0x70 +#define CMOS_DATA_PORT (PUCHAR)0x71 +#define RTC_REGISTER_A 0x0A +#define RTC_REGISTER_B 0x0B +#define RTC_REG_A_UIP 0x80 +#define RTC_REGISTER_CENTURY 0x32 + +/* Timer Registers and Ports */ +#define TIMER_CONTROL_PORT 0x43 +#define TIMER_DATA_PORT0 0x40 +#define TIMER_SC0 0 +#define TIMER_BOTH 0x30 +#define TIMER_MD2 0x4 + +/* Conversion functions */ +#define BCD_INT(bcd) \ + (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F)) +#define INT_BCD(int) \ + (UCHAR)(((int / 10) << 4) + (int % 10)) + +/* adapter.c */ +PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses); + +/* bus.c */ +VOID NTAPI HalpInitNonBusHandler (VOID); + +/* irql.c */ +VOID NTAPI HalpInitPICs(VOID); + +/* udelay.c */ +VOID NTAPI HalpInitializeClock(VOID); + +/* pci.c */ +VOID HalpInitPciBus (VOID); + +/* dma.c */ +VOID HalpInitDma (VOID); + +/* Non-generic initialization */ +VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock); +VOID HalpInitPhase1(VOID); +VOID NTAPI HalpClockInterrupt(VOID); + +// +// KD Support +// +VOID +NTAPI +HalpCheckPowerButton( + VOID +); + +VOID +NTAPI +HalpRegisterKdSupportFunctions( + VOID +); + +NTSTATUS +NTAPI +HalpSetupPciDeviceForDebugging( + IN PVOID LoaderBlock, + IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice +); + +NTSTATUS +NTAPI +HalpReleasePciDeviceForDebugging( + IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice +); + +// +// Memory routines +// +PVOID +NTAPI +HalpMapPhysicalMemory64( + IN PHYSICAL_ADDRESS PhysicalAddress, + IN ULONG NumberPage +); + +VOID +NTAPI +HalpUnmapVirtualAddress( + IN PVOID VirtualAddress, + IN ULONG NumberPages +); + +/* sysinfo.c */ +NTSTATUS +NTAPI +HaliQuerySystemInformation( + IN HAL_QUERY_INFORMATION_CLASS InformationClass, + IN ULONG BufferSize, + IN OUT PVOID Buffer, + OUT PULONG ReturnedLength +); + +NTSTATUS +NTAPI +HaliSetSystemInformation( + IN HAL_SET_INFORMATION_CLASS InformationClass, + IN ULONG BufferSize, + IN OUT PVOID Buffer +); + +// +// BIOS Routines +// +BOOLEAN +NTAPI +HalpBiosDisplayReset( + VOID +); + +ULONG +NTAPI +HalpBorrowTss( + VOID +); + +ULONG +NTAPI +HalpReturnTss( + ULONG SavedTss +); + +VOID +NTAPI +HalpBiosCall( + VOID +); + +VOID +NTAPI +HalpTrap0D( + VOID +); + +VOID +NTAPI +HalpTrap06( + VOID +); + +PDMA_ADAPTER +NTAPI +HalpGetDmaAdapter( + IN PVOID Context, + IN PDEVICE_DESCRIPTION DeviceDescription, + OUT PULONG NumberOfMapRegisters); + +VOID HaliInitBSP(VOID); +VOID HaliStartApplicationProcessor(ULONG Cpu, ULONG Stack); + +extern PVOID HalpRealModeStart; +extern PVOID HalpRealModeEnd; + +extern KSPIN_LOCK HalpSystemHardwareLock; + +#endif /* __INTERNAL_HAL_HAL_H */ diff --git a/reactos/hal/halamd64/up/halinit_up.c b/reactos/hal/halamd64/up/halinit_up.c new file mode 100644 index 00000000000..cbb18bc665e --- /dev/null +++ b/reactos/hal/halamd64/up/halinit_up.c @@ -0,0 +1,32 @@ +/* $Id: halinit_up.c 24964 2006-11-29 08:28:20Z ion $ + * + * COPYRIGHT: See COPYING in the top level directory + * PROJECT: ReactOS kernel + * FILE: ntoskrnl/hal/x86/halinit.c + * PURPOSE: Initalize the x86 hal + * PROGRAMMER: David Welch (welch@cwcom.net) + * UPDATE HISTORY: + * 11/06/98: Created + */ + +/* INCLUDES *****************************************************************/ + +#include +#define NDEBUG +#include + +/* FUNCTIONS ***************************************************************/ + +VOID +HalpInitPhase0(IN PLOADER_PARAMETER_BLOCK LoaderBlock) +{ + +} + +VOID +HalpInitPhase1(VOID) +{ + +} + +/* EOF */ diff --git a/reactos/hal/halamd64/up/halup.rbuild b/reactos/hal/halamd64/up/halup.rbuild new file mode 100644 index 00000000000..08f72745185 --- /dev/null +++ b/reactos/hal/halamd64/up/halup.rbuild @@ -0,0 +1,16 @@ + + + + + + ../include + include + + + hal_generic_amd64 + hal_generic + ntoskrnl + halinit_up.c + halup.rc + processor.c + diff --git a/reactos/hal/halamd64/up/halup.rc b/reactos/hal/halamd64/up/halup.rc new file mode 100644 index 00000000000..951c3581d56 --- /dev/null +++ b/reactos/hal/halamd64/up/halup.rc @@ -0,0 +1,5 @@ +#define REACTOS_VERSION_DLL +#define REACTOS_STR_FILE_DESCRIPTION "AMD64 Uniprocessor Hardware Abstraction Layer\0" +#define REACTOS_STR_INTERNAL_NAME "halup\0" +#define REACTOS_STR_ORIGINAL_FILENAME "halup.dll\0" +#include diff --git a/reactos/hal/halamd64/up/processor.c b/reactos/hal/halamd64/up/processor.c new file mode 100644 index 00000000000..669c82b5910 --- /dev/null +++ b/reactos/hal/halamd64/up/processor.c @@ -0,0 +1,87 @@ +/* + * PROJECT: ReactOS HAL + * LICENSE: GPL - See COPYING in the top level directory + * FILE: hal/halamd64/up/processor.c + * PURPOSE: HAL Processor Routines + * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org) + */ + +/* INCLUDES ******************************************************************/ + +#include +#define NDEBUG +#include + +LONG HalpActiveProcessors; +KAFFINITY HalpDefaultInterruptAffinity; + +/* FUNCTIONS *****************************************************************/ + +/* + * @implemented + */ +VOID +NTAPI +HalInitializeProcessor(IN ULONG ProcessorNumber, + IN PLOADER_PARAMETER_BLOCK LoaderBlock) +{ + /* Set default IDR and stall count */ +// KeGetPcr()->IDR = 0xFFFFFFFB; + KeGetPcr()->StallScaleFactor = INITIAL_STALL_COUNT; + + /* Update the interrupt affinity and processor mask */ + InterlockedBitTestAndSet(&HalpActiveProcessors, ProcessorNumber); + InterlockedBitTestAndSet((PLONG)&HalpDefaultInterruptAffinity, + ProcessorNumber); + + /* Register routines for KDCOM */ + HalpRegisterKdSupportFunctions(); +} + +/* + * @implemented + */ +BOOLEAN +NTAPI +HalAllProcessorsStarted(VOID) +{ + /* Do nothing */ + return TRUE; +} + +/* + * @implemented + */ +BOOLEAN +NTAPI +HalStartNextProcessor(IN PLOADER_PARAMETER_BLOCK LoaderBlock, + IN PKPROCESSOR_STATE ProcessorState) +{ + /* Ready to start */ + return FALSE; +} + +/* + * @implemented + */ +VOID +NTAPI +HalProcessorIdle(VOID) +{ + /* Enable interrupts and halt the processor */ + _enable(); + Ke386HaltProcessor(); +} + +/* + * @implemented + */ +VOID +NTAPI +HalRequestIpi(KAFFINITY TargetSet) +{ + /* Not implemented on NT */ + __debugbreak(); +} + +/* EOF */ diff --git a/reactos/hal/halx86/generic/timer.c b/reactos/hal/halx86/generic/timer.c index f9876f60070..e7ef223f506 100644 --- a/reactos/hal/halx86/generic/timer.c +++ b/reactos/hal/halx86/generic/timer.c @@ -48,7 +48,7 @@ HalpInitializeClock(VOID) PKPRCB Prcb = KeGetCurrentPrcb(); ULONG Increment; USHORT RollOver; - ULONG Flags; + ULONG_PTR Flags; /* Check the CPU Type */ if (Prcb->CpuType <= 4) @@ -92,7 +92,7 @@ NTAPI HalCalibratePerformanceCounter(IN volatile PLONG Count, IN ULONGLONG NewCount) { - ULONG Flags; + ULONG_PTR Flags; /* Disable interrupts */ Flags = __readeflags(); diff --git a/reactos/hal/halx86/hal_generic_amd64.rbuild b/reactos/hal/halx86/hal_generic_amd64.rbuild new file mode 100644 index 00000000000..c343b64e268 --- /dev/null +++ b/reactos/hal/halx86/hal_generic_amd64.rbuild @@ -0,0 +1,29 @@ + + + + + include + include + + + + beep.c + bus.c + cmos.c + dma.c + drive.c + display.c + pci.c + profil.c + reboot.c + sysinfo.c + timer.c + + + apic.c + + + hal.h + + + diff --git a/reactos/hal/halx86/include/apic.h b/reactos/hal/halx86/include/apic.h index 453b32fee4d..1625e9d0ece 100644 --- a/reactos/hal/halx86/include/apic.h +++ b/reactos/hal/halx86/include/apic.h @@ -5,7 +5,11 @@ #ifndef __INTERNAL_HAL_APIC_H #define __INTERNAL_HAL_APIC_H +#ifdef _M_AMD64 +#define APIC_DEFAULT_BASE 0xfffffffffee00000ULL; +#else #define APIC_DEFAULT_BASE 0xFEE00000 /* Default Local APIC Base Register Address */ +#endif /* APIC Register Address Map */ #define APIC_ID 0x0020 /* Local APIC ID Register (R/W) */ @@ -115,30 +119,6 @@ #define APIC_TDCR_128 0x0A #define APIC_TDCR_1 0x0B -#define APIC_LVT_VECTOR (0xFF << 0) /* Vector */ -#define APIC_LVT_DS (0x1 << 12) /* Delivery Status */ -#define APIC_LVT_REMOTE_IRR (0x1 << 14) /* Remote IRR */ -#define APIC_LVT_LEVEL_TRIGGER (0x1 << 15) /* Lvel Triggered */ -#define APIC_LVT_MASKED (0x1 << 16) /* Mask */ -#define APIC_LVT_PERIODIC (0x1 << 17) /* Timer Mode */ - -#define APIC_LVT3_DM (0x7 << 8) -#define APIC_LVT3_IIPP (0x1 << 13) -#define APIC_LVT3_TM (0x1 << 15) -#define APIC_LVT3_MASKED (0x1 << 16) -#define APIC_LVT3_OS (0x1 << 17) - -#define APIC_TDCR_TMBASE (0x1 << 2) -#define APIC_TDCR_MASK 0x0F -#define APIC_TDCR_2 0x00 -#define APIC_TDCR_4 0x01 -#define APIC_TDCR_8 0x02 -#define APIC_TDCR_16 0x03 -#define APIC_TDCR_32 0x08 -#define APIC_TDCR_64 0x09 -#define APIC_TDCR_128 0x0A -#define APIC_TDCR_1 0x0B - #define APIC_TARGET_SELF 0x100 #define APIC_TARGET_ALL 0x200 #define APIC_TARGET_ALL_BUT_SELF 0x300 @@ -206,7 +186,7 @@ static __inline ULONG _APICRead(ULONG Offset) { PULONG p; - p = (PULONG)((ULONG)APICBase + Offset); + p = (PULONG)((ULONG_PTR)APICBase + Offset); return *p; } @@ -216,7 +196,7 @@ static __inline VOID APICWrite(ULONG Offset, { PULONG p; - p = (PULONG)((ULONG)APICBase + Offset); + p = (PULONG)((ULONG_PTR)APICBase + Offset); *p = Value; } @@ -230,7 +210,7 @@ static __inline VOID APICWrite(ULONG Offset, lastregw[CPU] = Offset; lastvalw[CPU] = Value; - p = (PULONG)((ULONG)APICBase + Offset); + p = (PULONG)((ULONG_PTR)APICBase + Offset); *p = Value; } @@ -241,7 +221,7 @@ static __inline ULONG APICRead(ULONG Offset) { PULONG p; - p = (PULONG)((ULONG)APICBase + Offset); + p = (PULONG)((ULONG_PTR)APICBase + Offset); return *p; } #else @@ -253,7 +233,7 @@ static __inline ULONG APICRead(ULONG Offset) lastregr[CPU] = Offset; lastvalr[CPU] = 0; - p = (PULONG)((ULONG)APICBase + Offset); + p = (PULONG)((ULONG_PTR)APICBase + Offset); lastvalr[CPU] = *p; return lastvalr[CPU]; diff --git a/reactos/hal/halx86/include/bus.h b/reactos/hal/halx86/include/bus.h index 262efeea1b9..9f58d4055e0 100644 --- a/reactos/hal/halx86/include/bus.h +++ b/reactos/hal/halx86/include/bus.h @@ -43,7 +43,7 @@ #define TYPE1_READ(x, y) \ TYPE1_START(x, y) \ *((POINTER_TO_(y))Buffer) = \ - READ_FROM(y)((POINTER_TO_(y))(BusData->Config.Type1.Data + i)); \ + READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i)); \ TYPE1_END(y) // @@ -51,7 +51,7 @@ // #define TYPE1_WRITE(x, y) \ TYPE1_START(x, y) \ - WRITE_TO(y)((POINTER_TO_(y))(BusData->Config.Type1.Data + i), \ + WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i), \ *((POINTER_TO_(y))Buffer)); \ TYPE1_END(y) @@ -69,7 +69,7 @@ #define TYPE2_READ(x, y) \ TYPE2_START(x, y) \ *((POINTER_TO_(y))Buffer) = \ - READ_FROM(y)((POINTER_TO_(y))(ULONG)PciCfg->u.AsUSHORT); \ + READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT); \ TYPE2_END(y) // @@ -77,7 +77,7 @@ // #define TYPE2_WRITE(x, y) \ TYPE2_START(x, y) \ - WRITE_TO(y)((POINTER_TO_(y))(ULONG)PciCfg->u.AsUSHORT, \ + WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT, \ *((POINTER_TO_(y))Buffer)); \ TYPE2_END(y) diff --git a/reactos/hal/halx86/include/hal.h b/reactos/hal/halx86/include/hal.h index b6b01e39f1f..facbbcf3caa 100644 --- a/reactos/hal/halx86/include/hal.h +++ b/reactos/hal/halx86/include/hal.h @@ -34,7 +34,11 @@ /* Internal kernel headers */ #include "internal/pci.h" +#ifdef _M_AMD64 +#include "internal/amd64/intrin_i.h" +#else #include "internal/i386/intrin_i.h" +#endif /* Internal HAL Headers */ #include "apic.h" diff --git a/reactos/hal/halx86/include/halp.h b/reactos/hal/halx86/include/halp.h index d5a9240e4d6..578d8832409 100644 --- a/reactos/hal/halx86/include/halp.h +++ b/reactos/hal/halx86/include/halp.h @@ -154,6 +154,17 @@ HalpTrap06( VOID ); +#ifdef _M_AMD64 +#define KfLowerIrql KeLowerIrql +#ifndef CONFIG_SMP +/* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */ +#define KiAcquireSpinLock(SpinLock) +#define KiReleaseSpinLock(SpinLock) +#define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL); +#define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql); +#endif // !CONFIG_SMP +#endif // _M_AMD64 + extern PVOID HalpRealModeStart; extern PVOID HalpRealModeEnd; diff --git a/reactos/hal/halx86/mp/apic.c b/reactos/hal/halx86/mp/apic.c index 8214c5b58cb..3c955d856d4 100644 --- a/reactos/hal/halx86/mp/apic.c +++ b/reactos/hal/halx86/mp/apic.c @@ -709,6 +709,9 @@ VOID MpsIRQTrapFrameToTrapFrame(PKIRQ_TRAPFRAME IrqTrapFrame, PKTRAP_FRAME TrapFrame) { +#ifdef _M_AMD64 + UNIMPLEMENTED; +#else TrapFrame->SegGs = (USHORT)IrqTrapFrame->Gs; TrapFrame->SegFs = (USHORT)IrqTrapFrame->Fs; TrapFrame->SegEs = (USHORT)IrqTrapFrame->Es; @@ -724,6 +727,7 @@ MpsIRQTrapFrameToTrapFrame(PKIRQ_TRAPFRAME IrqTrapFrame, TrapFrame->Eip = IrqTrapFrame->Eip; TrapFrame->SegCs = IrqTrapFrame->Cs; TrapFrame->EFlags = IrqTrapFrame->Eflags; +#endif } VOID @@ -798,7 +802,7 @@ APICCalibrateTimer(ULONG CPU) APICSetupLVTT(1000000000); - TSCPresent = ((PKIPCR)KeGetPcr())->PrcbData.FeatureBits & KF_RDTSC ? TRUE : FALSE; + TSCPresent = KeGetCurrentPrcb()->FeatureBits & KF_RDTSC ? TRUE : FALSE; /* * The timer chip counts down to zero. Let's wait @@ -827,7 +831,7 @@ APICCalibrateTimer(ULONG CPU) DPRINT("CPU clock speed is %ld.%04ld MHz.\n", CPUMap[CPU].CoreSpeed/1000000, CPUMap[CPU].CoreSpeed%1000000); - ((PKIPCR)KeGetPcr())->PrcbData.MHz = CPUMap[CPU].CoreSpeed/1000000; + KeGetCurrentPrcb()->MHz = CPUMap[CPU].CoreSpeed/1000000; } CPUMap[CPU].BusSpeed = (HZ * (long)(tt1 - tt2) * APIC_DIVISOR); @@ -843,8 +847,25 @@ APICCalibrateTimer(ULONG CPU) } VOID -SetInterruptGate(ULONG index, ULONG address) +SetInterruptGate(ULONG index, ULONG_PTR address) { +#ifdef _M_AMD64 + KIDTENTRY64 *idt; + + idt = &KeGetPcr()->IdtBase[index]; + + idt->OffsetLow = address & 0xffff; + idt->Selector = KGDT_64_R0_CODE; + idt->IstIndex = 0; + idt->Reserved0 = 0; + idt->Type = 0x0e; + idt->Dpl = 0; + idt->Present = 1; + idt->OffsetMiddle = (address >> 16) & 0xffff; + idt->OffsetHigh = address >> 32; + idt->Reserved1 = 0; + idt->Alignment = 0; +#else KIDTENTRY *idt; KIDT_ACCESS Access; @@ -860,6 +881,7 @@ SetInterruptGate(ULONG index, ULONG address) idt->Selector = KGDT_R0_CODE; idt->Access = Access.Value; idt->ExtendedOffset = (USHORT)(address >> 16); +#endif } VOID HaliInitBSP(VOID) @@ -880,11 +902,11 @@ VOID HaliInitBSP(VOID) BSPInitialized = TRUE; /* Setup interrupt handlers */ - SetInterruptGate(LOCAL_TIMER_VECTOR, (ULONG)MpsTimerInterrupt); - SetInterruptGate(ERROR_VECTOR, (ULONG)MpsErrorInterrupt); - SetInterruptGate(SPURIOUS_VECTOR, (ULONG)MpsSpuriousInterrupt); + SetInterruptGate(LOCAL_TIMER_VECTOR, (ULONG_PTR)MpsTimerInterrupt); + SetInterruptGate(ERROR_VECTOR, (ULONG_PTR)MpsErrorInterrupt); + SetInterruptGate(SPURIOUS_VECTOR, (ULONG_PTR)MpsSpuriousInterrupt); #ifdef CONFIG_SMP - SetInterruptGate(IPI_VECTOR, (ULONG)MpsIpiInterrupt); + SetInterruptGate(IPI_VECTOR, (ULONG_PTR)MpsIpiInterrupt); #endif DPRINT("APIC is mapped at 0x%X\n", APICBase); @@ -913,18 +935,18 @@ VOID HaliInitBSP(VOID) CommonBase = (PULONG)COMMON_AREA; /* Copy bootstrap code to common area */ - memcpy((PVOID)((ULONG)CommonBase + PAGE_SIZE), + memcpy((PVOID)((ULONG_PTR)CommonBase + PAGE_SIZE), &APstart, - (ULONG)&APend - (ULONG)&APstart + 1); + (ULONG_PTR)&APend - (ULONG_PTR)&APstart + 1); /* Set shutdown code */ CMOS_WRITE(0xF, 0xA); /* Set warm reset vector */ - ps = (PUSHORT)((ULONG)BIOSBase + 0x467); + ps = (PUSHORT)((ULONG_PTR)BIOSBase + 0x467); *ps = (COMMON_AREA + PAGE_SIZE) & 0xF; - ps = (PUSHORT)((ULONG)BIOSBase + 0x469); + ps = (PUSHORT)((ULONG_PTR)BIOSBase + 0x469); *ps = (COMMON_AREA + PAGE_SIZE) >> 4; #endif