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- Fix receive to work on VMware emulated adapters. We need to set busmaster bit on PCI command register in order to get packets. Otherwise we just get "missing frame" error and the ring buffer remains empty.
- Indicate receive completition. - Implement basic packet transmitting. - Don't read slot number from registry and report itself as NDIS 5.0 miniport. - Fix nasty bugs in halt code path (incorrect assignment and wrong parameters to NdisMFreeSharedMemory calls). svn path=/trunk/; revision=11270
This commit is contained in:
Filip Navara
parent
2dea5c279b
commit
f321359e16
6 changed files with 269 additions and 241 deletions
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@ -3,10 +3,10 @@ TARGET_TYPE = driver
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TARGET_NAME = pcnet
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#
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# - must define NDIS40 to get the right characteristics struct
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# - must define NDIS50 to get the right characteristics struct
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# - must define anonymous unions to make physical addresses work right
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#
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TARGET_CFLAGS = -I. -DDBG=1 -Wall -Werror -DNDIS40 -DANONYMOUSUNIONS
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TARGET_CFLAGS = -I. -DDBG=0 -Wall -Werror -DNDIS50 -DANONYMOUSUNIONS
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TARGET_OBJECTS = pcnet.o requests.o
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TARGET_DDKLIBS = ndis.a
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@ -1,6 +1,7 @@
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/*
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* ReactOS AMD PCNet Driver
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* Copyright (C) 1998, 1999, 2000, 2001 ReactOS Team
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*
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* Copyright (C) 2003 Vizzini <vizzini@plasmic.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -16,14 +17,14 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* PROJECT: ReactOS AMD PCNet Driver
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* FILE: pcnet/pci.h
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* PURPOSE: PCI configuration constants
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* PROGRAMMER: Vizzini (vizzini@plasmic.com)
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* PURPOSE:
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* PCI configuration constants
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* REVISIONS:
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* 1-Sept-2003 vizzini - Created
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* 01-Sept-2003 vizzini - Created
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*/
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#ifndef _PCI_
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#define _PCI_
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/* PCI Config Space Offset Definitions */
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#define PCI_PCIID 0x0 /* pci id - query 32 bits */
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@ -67,3 +68,4 @@
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#define PCI_SERR 0x2000 /* signalled error */
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#define PCI_PERR 0x4000 /* parity error */
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#endif /* _PCI_ */
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@ -1,6 +1,8 @@
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/*
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* ReactOS AMD PCNet Driver
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* Copyright (C) 1998, 1999, 2000, 2001 ReactOS Team
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*
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* Copyright (C) 2003 Vizzini <vizzini@plasmic.com>
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* Copyright (C) 2004 Filip Navara <navaraf@reactos.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -16,20 +18,21 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* PROJECT: ReactOS AMD PCNet Driver
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* FILE: drivers/net/dd/pcnet/pcnet.c
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* PURPOSE: PCNet Device Driver
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* PROGRAMMER: Vizzini (vizzini@plasmic.com)
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* REVISIONS:
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* 9-Sept-2003 vizzini - Created
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* 09-Sep-2003 vizzini - Created
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* 10-Oct-2004 navaraf - Fix receive to work on VMware adapters (
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* need to set busmaster bit on PCI).
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* - Indicate receive completition.
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* - Implement packet transmitting.
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* - Don't read slot number from registry and
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* report itself as NDIS 5.0 miniport.
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* 11-Oct-2004 navaraf - Fix nasty bugs in halt code path.
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*
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* NOTES:
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* - this is hard-coded to NDIS4
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* - this assumes a little-endian machine
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* - this is hard-coded to NDIS5
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* - this assumes a 32-bit machine
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* - this doesn't handle multiple PCNET NICs yet
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* - this driver includes both NdisRaw and NdisImmediate calls
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* for NDIS testing purposes. Pick your poison below.
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*/
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#include <ndis.h>
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#include "pci.h"
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#include "pcnethw.h"
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@ -49,10 +52,12 @@ MiniportHandleInterrupt(
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{
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PADAPTER Adapter = (PADAPTER)MiniportAdapterContext;
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USHORT Data;
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BOOLEAN ErrorHandled = FALSE;
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#if DBG
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BOOLEAN ReceiveHandled = FALSE;
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BOOLEAN ErrorHandled = FALSE;
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BOOLEAN IdonHandled = FALSE;
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USHORT Temp;
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BOOLEAN TransmitHandled = FALSE;
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#endif
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PCNET_DbgPrint(("Called\n"));
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@ -63,6 +68,9 @@ MiniportHandleInterrupt(
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while(Data & CSR0_INTR)
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{
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/* Clear interrupt flags early to avoid race conditions. */
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NdisRawWritePortUshort(Adapter->PortOffset + RDP, Data);
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if(Data & CSR0_ERR)
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{
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#if DBG
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@ -75,10 +83,7 @@ MiniportHandleInterrupt(
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ErrorHandled = TRUE;
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#endif
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PCNET_DbgPrint(("clearing an error\n"));
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NdisRawWritePortUshort(Adapter->PortOffset + RDP, CSR0_MERR|CSR0_BABL|CSR0_CERR|CSR0_MISS);
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NdisRawReadPortUshort(Adapter->PortOffset + RDP, &Temp);
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PCNET_DbgPrint(("CSR0 is now 0x%x\n", Temp));
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PCNET_DbgPrint(("error: %x\n", Data & (CSR0_MERR|CSR0_BABL|CSR0_CERR|CSR0_MISS)));
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}
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else if(Data & CSR0_IDON)
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{
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@ -92,10 +97,7 @@ MiniportHandleInterrupt(
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IdonHandled = TRUE;
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#endif
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PCNET_DbgPrint(("clearing IDON\n"));
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NdisRawWritePortUshort(Adapter->PortOffset + RDP, CSR0_IDON);
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NdisRawReadPortUshort(Adapter->PortOffset + RDP, &Temp);
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PCNET_DbgPrint(("CSR0 is now 0x%x\n", Temp));
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PCNET_DbgPrint(("IDON\n"));
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}
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else if(Data & CSR0_RINT)
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{
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@ -109,10 +111,7 @@ MiniportHandleInterrupt(
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ReceiveHandled = TRUE;
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#endif
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PCNET_DbgPrint(("receive interrupt - clearing\n"));
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NdisRawWritePortUshort(Adapter->PortOffset + RDP, CSR0_RINT);
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NdisRawReadPortUshort(Adapter->PortOffset + RDP, &Temp);
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PCNET_DbgPrint(("CSR0 is now 0x%x\n", Temp));
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PCNET_DbgPrint(("receive interrupt\n"));
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while(1)
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{
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@ -144,19 +143,60 @@ MiniportHandleInterrupt(
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PCNET_DbgPrint(("Indicating a %d-byte packet (index %d)\n", ByteCount, Adapter->CurrentReceiveDescriptorIndex));
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NdisMEthIndicateReceive(Adapter->MiniportAdapterHandle, 0, Buffer, 14, Buffer+14, ByteCount-14, ByteCount-14);
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NdisMEthIndicateReceiveComplete(Adapter->MiniportAdapterHandle);
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memset(Descriptor, 0, sizeof(RECEIVE_DESCRIPTOR));
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RtlZeroMemory(Descriptor, sizeof(RECEIVE_DESCRIPTOR));
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Descriptor->RBADR =
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(ULONG)(Adapter->ReceiveBufferPtrPhys + Adapter->CurrentReceiveDescriptorIndex * BUFFER_SIZE);
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Descriptor->BCNT = (-BUFFER_SIZE) | 0xf000;
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Descriptor->FLAGS &= RD_OWN;
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Descriptor->FLAGS |= RD_OWN;
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Adapter->CurrentReceiveDescriptorIndex++;
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if(Adapter->CurrentReceiveDescriptorIndex == NUMBER_OF_BUFFERS)
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Adapter->CurrentReceiveDescriptorIndex = 0;
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Adapter->CurrentReceiveDescriptorIndex %= NUMBER_OF_BUFFERS;
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}
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}
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else if(Data & CSR0_TINT)
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{
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PTRANSMIT_DESCRIPTOR Descriptor;
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#if DBG
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if(TransmitHandled)
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{
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PCNET_DbgPrint(("TRANSMIT HANDLED TWO TIMES\n"));
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ASSERT(0);
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}
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TransmitHandled = TRUE;
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#endif
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PCNET_DbgPrint(("transmit interrupt\n"));
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while (Adapter->CurrentTransmitStartIndex !=
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Adapter->CurrentTransmitEndIndex)
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{
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Descriptor = Adapter->TransmitDescriptorRingVirt + Adapter->CurrentTransmitStartIndex;
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PCNET_DbgPrint(("buffer %d flags %x flags2 %x\n",
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Adapter->CurrentTransmitStartIndex,
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Descriptor->FLAGS, Descriptor->FLAGS2));
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if (Descriptor->FLAGS & TD1_OWN)
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{
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PCNET_DbgPrint(("non-TXed buffer\n"));
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break;
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}
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if (Descriptor->FLAGS & TD1_ERR)
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{
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PCNET_DbgPrint(("major error: %x\n", Descriptor->FLAGS2));
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break;
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}
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Adapter->CurrentTransmitStartIndex++;
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Adapter->CurrentTransmitStartIndex %= NUMBER_OF_BUFFERS;
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}
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NdisMSendResourcesAvailable(Adapter->MiniportAdapterHandle);
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}
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else
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{
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PCNET_DbgPrint(("UNHANDLED INTERRUPT\n"));
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@ -191,7 +231,7 @@ MiQueryCard(
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NDIS_STATUS Status;
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/* Detect the card in the configured slot */
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Status = NdisReadPciSlotInformation(Adapter->MiniportAdapterHandle, Adapter->SlotNumber, PCI_PCIID, &buf32, 4);
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Status = NdisReadPciSlotInformation(Adapter->MiniportAdapterHandle, 0, PCI_PCIID, &buf32, 4);
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if(Status != 4)
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{
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Status = NDIS_STATUS_FAILURE;
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@ -203,36 +243,18 @@ MiQueryCard(
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if(buf32 != PCI_ID)
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{
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Status = NDIS_STATUS_ADAPTER_NOT_FOUND;
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PCNET_DbgPrint(("card in slot 0x%x isn't us: 0x%x\n", Adapter->SlotNumber, buf32));
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PCNET_DbgPrint(("card in slot isn't our: 0x%x\n", 0, buf32));
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BREAKPOINT;
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return Status;
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}
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Status = NdisReadPciSlotInformation(Adapter->MiniportAdapterHandle, Adapter->SlotNumber,
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PCI_COMMAND, &buf32, 4);
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if(Status != 4)
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{
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PCNET_DbgPrint(("NdisReadPciSlotInformation failed\n"));
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BREAKPOINT;
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return NDIS_STATUS_FAILURE;
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}
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PCNET_DbgPrint(("config/status register: 0x%x\n", buf32));
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if(buf32 & 0x1)
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{
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PCNET_DbgPrint(("io space access is enabled.\n"));
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}
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else
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{
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PCNET_DbgPrint(("io space is NOT enabled!\n"));
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BREAKPOINT;
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return NDIS_STATUS_FAILURE;
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}
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/* set busmaster and io space enable bits */
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buf32 = PCI_BMEN | PCI_IOEN;
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NdisWritePciSlotInformation(Adapter->MiniportAdapterHandle, 0, PCI_COMMAND, &buf32, 4);
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/* get IO base physical address */
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buf32 = 0;
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Status = NdisReadPciSlotInformation(Adapter->MiniportAdapterHandle, Adapter->SlotNumber, PCI_IOBAR, &buf32, 4);
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Status = NdisReadPciSlotInformation(Adapter->MiniportAdapterHandle, 0, PCI_IOBAR, &buf32, 4);
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if(Status != 4)
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{
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Status = NDIS_STATUS_FAILURE;
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@ -253,7 +275,7 @@ MiQueryCard(
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Adapter->IoBaseAddress = buf32;
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/* get interrupt vector */
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Status = NdisReadPciSlotInformation(Adapter->MiniportAdapterHandle, Adapter->SlotNumber, PCI_ILR, &buf8, 1);
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Status = NdisReadPciSlotInformation(Adapter->MiniportAdapterHandle, 0, PCI_ILR, &buf8, 1);
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if(Status != 1)
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{
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Status = NDIS_STATUS_FAILURE;
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@ -268,48 +290,6 @@ MiQueryCard(
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return NDIS_STATUS_SUCCESS;
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}
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NDIS_STATUS
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MiGetConfig(
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PADAPTER Adapter,
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NDIS_HANDLE WrapperConfigurationContext)
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/*
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* FUNCTION: Get configuration parameters from the registry
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* ARGUMENTS:
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* Adapter: pointer to the Adapter struct for this NIC
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* WrapperConfigurationContext: Context passed into MiniportInitialize
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* RETURNS:
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* NDIS_STATUS_SUCCESS on success
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* NDIS_STATUS_{something} on failure (return val from other Ndis calls)
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*/
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{
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PNDIS_CONFIGURATION_PARAMETER Parameter;
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NDIS_HANDLE ConfigurationHandle = 0;
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UNICODE_STRING Keyword;
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NDIS_STATUS Status;
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NdisOpenConfiguration(&Status, &ConfigurationHandle, WrapperConfigurationContext);
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if(Status != NDIS_STATUS_SUCCESS)
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{
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PCNET_DbgPrint(("Unable to open configuration: 0x%x\n", Status));
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BREAKPOINT;
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return Status;
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}
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RtlInitUnicodeString(&Keyword, L"SlotNumber");
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NdisReadConfiguration(&Status, &Parameter, ConfigurationHandle, &Keyword, NdisParameterInteger);
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if(Status != NDIS_STATUS_SUCCESS)
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{
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PCNET_DbgPrint(("Unable to read slot number: 0x%x\n", Status));
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BREAKPOINT;
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}
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else
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Adapter->SlotNumber = Parameter->ParameterData.IntegerData;
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NdisCloseConfiguration(ConfigurationHandle);
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return NDIS_STATUS_SUCCESS;
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}
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NDIS_STATUS
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MiAllocateSharedMemory(
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PADAPTER Adapter)
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@ -346,7 +326,6 @@ MiAllocateSharedMemory(
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}
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Adapter->InitializationBlockPhys = (PINITIALIZATION_BLOCK)NdisGetPhysicalAddressLow(PhysicalAddress);
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memset(Adapter->InitializationBlockVirt, 0, sizeof(INITIALIZATION_BLOCK));
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/* allocate the transport descriptor ring */
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Adapter->TransmitDescriptorRingLength = sizeof(TRANSMIT_DESCRIPTOR) * NUMBER_OF_BUFFERS;
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@ -367,7 +346,7 @@ MiAllocateSharedMemory(
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}
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Adapter->TransmitDescriptorRingPhys = (PTRANSMIT_DESCRIPTOR)NdisGetPhysicalAddressLow(PhysicalAddress);
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memset(Adapter->TransmitDescriptorRingVirt, 0, sizeof(TRANSMIT_DESCRIPTOR) * NUMBER_OF_BUFFERS);
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RtlZeroMemory(Adapter->TransmitDescriptorRingVirt, sizeof(TRANSMIT_DESCRIPTOR) * NUMBER_OF_BUFFERS);
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/* allocate the receive descriptor ring */
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Adapter->ReceiveDescriptorRingLength = sizeof(RECEIVE_DESCRIPTOR) * NUMBER_OF_BUFFERS;
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@ -388,7 +367,7 @@ MiAllocateSharedMemory(
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}
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Adapter->ReceiveDescriptorRingPhys = (PRECEIVE_DESCRIPTOR)NdisGetPhysicalAddressLow(PhysicalAddress);
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memset(Adapter->ReceiveDescriptorRingVirt, 0, sizeof(RECEIVE_DESCRIPTOR) * NUMBER_OF_BUFFERS);
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RtlZeroMemory(Adapter->ReceiveDescriptorRingVirt, sizeof(RECEIVE_DESCRIPTOR) * NUMBER_OF_BUFFERS);
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/* allocate transmit buffers */
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Adapter->TransmitBufferLength = BUFFER_SIZE * NUMBER_OF_BUFFERS;
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@ -409,7 +388,7 @@ MiAllocateSharedMemory(
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}
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Adapter->TransmitBufferPtrPhys = (PCHAR)NdisGetPhysicalAddressLow(PhysicalAddress);
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memset(Adapter->TransmitBufferPtrVirt, 0, BUFFER_SIZE * NUMBER_OF_BUFFERS);
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RtlZeroMemory(Adapter->TransmitBufferPtrVirt, BUFFER_SIZE * NUMBER_OF_BUFFERS);
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/* allocate receive buffers */
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Adapter->ReceiveBufferLength = BUFFER_SIZE * NUMBER_OF_BUFFERS;
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@ -430,7 +409,7 @@ MiAllocateSharedMemory(
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}
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Adapter->ReceiveBufferPtrPhys = (PCHAR)NdisGetPhysicalAddressLow(PhysicalAddress);
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memset(Adapter->ReceiveBufferPtrVirt, 0, BUFFER_SIZE * NUMBER_OF_BUFFERS);
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RtlZeroMemory(Adapter->ReceiveBufferPtrVirt, BUFFER_SIZE * NUMBER_OF_BUFFERS);
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/* initialize tx descriptors */
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TransmitDescriptor = Adapter->TransmitDescriptorRingVirt;
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@ -448,8 +427,8 @@ MiAllocateSharedMemory(
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for(i = 0; i < NUMBER_OF_BUFFERS; i++)
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{
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(ReceiveDescriptor+i)->RBADR = (ULONG)Adapter->ReceiveBufferPtrPhys + i * BUFFER_SIZE;
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(ReceiveDescriptor+i)->BCNT = 0xf0000 | -BUFFER_SIZE; /* 2's compliment + set top 4 bits */
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(ReceiveDescriptor+i)->FLAGS |= RD_OWN;
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(ReceiveDescriptor+i)->BCNT = 0xf000 | -BUFFER_SIZE; /* 2's compliment + set top 4 bits */
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(ReceiveDescriptor+i)->FLAGS = RD_OWN;
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}
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PCNET_DbgPrint(("receive ring initialized\n"));
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@ -468,9 +447,18 @@ MiPrepareInitializationBlock(
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{
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ULONG i = 0;
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RtlZeroMemory(Adapter->InitializationBlockVirt, sizeof(INITIALIZATION_BLOCK));
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/* read burned-in address from card */
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for(i = 0; i < 6; i++)
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NdisRawReadPortUchar(Adapter->PortOffset + i, Adapter->InitializationBlockVirt->PADR + i);
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PCNET_DbgPrint(("MAC address: %02x-%02x-%02x-%02x-%02x-%02x\n",
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Adapter->InitializationBlockVirt->PADR[0],
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Adapter->InitializationBlockVirt->PADR[1],
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Adapter->InitializationBlockVirt->PADR[2],
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Adapter->InitializationBlockVirt->PADR[3],
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Adapter->InitializationBlockVirt->PADR[4],
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Adapter->InitializationBlockVirt->PADR[5]));
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/* set up receive ring */
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PCNET_DbgPrint(("Receive ring physical address: 0x%x\n", Adapter->ReceiveDescriptorRingPhys));
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@ -500,35 +488,35 @@ MiFreeSharedMemory(
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{
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PhysicalAddress.u.LowPart = (ULONG)Adapter->InitializationBlockPhys;
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NdisMFreeSharedMemory(Adapter->MiniportAdapterHandle, Adapter->InitializationBlockLength,
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FALSE, (PVOID *)&Adapter->InitializationBlockVirt, PhysicalAddress);
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FALSE, Adapter->InitializationBlockVirt, PhysicalAddress);
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}
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if(Adapter->TransmitDescriptorRingVirt)
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{
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PhysicalAddress.u.LowPart = (ULONG)Adapter->TransmitDescriptorRingPhys;
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NdisMFreeSharedMemory(Adapter->MiniportAdapterHandle, Adapter->TransmitDescriptorRingLength,
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FALSE, (PVOID *)&Adapter->TransmitDescriptorRingVirt, PhysicalAddress);
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FALSE, Adapter->TransmitDescriptorRingVirt, PhysicalAddress);
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}
|
||||
|
||||
if(Adapter->ReceiveDescriptorRingVirt)
|
||||
{
|
||||
PhysicalAddress.u.LowPart = (ULONG)Adapter->ReceiveDescriptorRingPhys;
|
||||
NdisMFreeSharedMemory(Adapter->MiniportAdapterHandle, Adapter->ReceiveDescriptorRingLength,
|
||||
FALSE, (PVOID *)&Adapter->ReceiveDescriptorRingVirt, PhysicalAddress);
|
||||
FALSE, Adapter->ReceiveDescriptorRingVirt, PhysicalAddress);
|
||||
}
|
||||
|
||||
if(Adapter->TransmitBufferPtrVirt)
|
||||
{
|
||||
PhysicalAddress.u.LowPart = (ULONG)Adapter->TransmitBufferPtrPhys;
|
||||
NdisMFreeSharedMemory(Adapter->MiniportAdapterHandle, Adapter->TransmitBufferLength,
|
||||
FALSE, (PVOID *)&Adapter->TransmitBufferPtrVirt, PhysicalAddress);
|
||||
FALSE, Adapter->TransmitBufferPtrVirt, PhysicalAddress);
|
||||
}
|
||||
|
||||
if(Adapter->ReceiveBufferPtrVirt)
|
||||
{
|
||||
PhysicalAddress.u.LowPart = (ULONG)Adapter->ReceiveBufferPtrPhys;
|
||||
NdisMFreeSharedMemory(Adapter->MiniportAdapterHandle, Adapter->ReceiveBufferLength,
|
||||
FALSE, (PVOID *)&Adapter->ReceiveBufferPtrVirt, PhysicalAddress);
|
||||
FALSE, Adapter->ReceiveBufferPtrVirt, PhysicalAddress);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -544,7 +532,7 @@ MiniportHalt(
|
|||
* - Called by NDIS at PASSIVE_LEVEL
|
||||
*/
|
||||
{
|
||||
PADAPTER Adapter = (PADAPTER)Adapter;
|
||||
PADAPTER Adapter = (PADAPTER)MiniportAdapterContext;
|
||||
|
||||
PCNET_DbgPrint(("Called\n"));
|
||||
ASSERT(Adapter);
|
||||
|
|
@ -765,7 +753,7 @@ MiniportInitialize(
|
|||
return Status;
|
||||
}
|
||||
|
||||
memset(Adapter,0,sizeof(ADAPTER));
|
||||
RtlZeroMemory(Adapter, sizeof(ADAPTER));
|
||||
|
||||
Adapter->MiniportAdapterHandle = MiniportAdapterHandle;
|
||||
|
||||
|
|
@ -774,16 +762,6 @@ MiniportInitialize(
|
|||
|
||||
do
|
||||
{
|
||||
/* get registry config */
|
||||
Status = MiGetConfig(Adapter, WrapperConfigurationContext);
|
||||
if(Status != NDIS_STATUS_SUCCESS)
|
||||
{
|
||||
PCNET_DbgPrint(("MiGetConfig failed\n"));
|
||||
Status = NDIS_STATUS_ADAPTER_NOT_FOUND;
|
||||
BREAKPOINT;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Card-specific detection and setup */
|
||||
Status = MiQueryCard(Adapter);
|
||||
if(Status != NDIS_STATUS_SUCCESS)
|
||||
|
|
@ -815,7 +793,7 @@ MiniportInitialize(
|
|||
}
|
||||
|
||||
/* set up the interrupt */
|
||||
memset(&Adapter->InterruptObject, 0, sizeof(NDIS_MINIPORT_INTERRUPT));
|
||||
RtlZeroMemory(&Adapter->InterruptObject, sizeof(NDIS_MINIPORT_INTERRUPT));
|
||||
Status = NdisMRegisterInterrupt(&Adapter->InterruptObject, Adapter->MiniportAdapterHandle, Adapter->InterruptVector,
|
||||
Adapter->InterruptVector, FALSE, TRUE, NdisInterruptLevelSensitive);
|
||||
if(Status != NDIS_STATUS_SUCCESS)
|
||||
|
|
@ -967,12 +945,75 @@ MiniportSend(
|
|||
* Packet: The NDIS_PACKET to be sent
|
||||
* Flags: Flags associated with Packet
|
||||
* RETURNS:
|
||||
* NDIS_STATUS_SUCCESS on all requests
|
||||
* NDIS_STATUS_SUCCESS on processed requests
|
||||
* NDIS_STATUS_RESOURCES if there's no place in buffer ring
|
||||
* NOTES:
|
||||
* - Called by NDIS at DISPATCH_LEVEL
|
||||
*/
|
||||
{
|
||||
PADAPTER Adapter = (PADAPTER)MiniportAdapterContext;
|
||||
PTRANSMIT_DESCRIPTOR Desc;
|
||||
PNDIS_BUFFER NdisBuffer;
|
||||
PVOID SourceBuffer;
|
||||
UINT TotalPacketLength, SourceLength, Position = 0;
|
||||
|
||||
PCNET_DbgPrint(("Called\n"));
|
||||
|
||||
/* Check if we have free entry in our circular buffer. */
|
||||
if ((Adapter->CurrentTransmitEndIndex + 1 ==
|
||||
Adapter->CurrentTransmitStartIndex) ||
|
||||
(Adapter->CurrentTransmitEndIndex == NUMBER_OF_BUFFERS - 1 &&
|
||||
Adapter->CurrentTransmitStartIndex == 0))
|
||||
{
|
||||
PCNET_DbgPrint(("No free space in circular buffer\n"));
|
||||
return NDIS_STATUS_RESOURCES;
|
||||
}
|
||||
|
||||
Desc = Adapter->TransmitDescriptorRingVirt + Adapter->CurrentTransmitEndIndex;
|
||||
|
||||
NdisQueryPacket(Packet, NULL, NULL, &NdisBuffer, &TotalPacketLength);
|
||||
ASSERT(TotalPacketLength <= BUFFER_SIZE);
|
||||
|
||||
PCNET_DbgPrint(("TotalPacketLength: %x\n", TotalPacketLength));
|
||||
|
||||
while (NdisBuffer)
|
||||
{
|
||||
NdisQueryBuffer(NdisBuffer, &SourceBuffer, &SourceLength);
|
||||
|
||||
PCNET_DbgPrint(("Buffer: %x Length: %x\n", SourceBuffer, SourceLength));
|
||||
|
||||
RtlCopyMemory(Adapter->TransmitBufferPtrVirt +
|
||||
Adapter->CurrentTransmitEndIndex * BUFFER_SIZE + Position,
|
||||
SourceBuffer, SourceLength);
|
||||
|
||||
Position += SourceLength;
|
||||
|
||||
NdisGetNextBuffer(NdisBuffer, &NdisBuffer);
|
||||
}
|
||||
|
||||
#if DBG
|
||||
{
|
||||
PUCHAR Ptr = Adapter->TransmitBufferPtrVirt +
|
||||
Adapter->CurrentTransmitEndIndex * BUFFER_SIZE;
|
||||
for (Position = 0; Position < TotalPacketLength; Position++)
|
||||
{
|
||||
if (Position % 16 == 0)
|
||||
DbgPrint("\n");
|
||||
DbgPrint("%x ", *Ptr++);
|
||||
}
|
||||
}
|
||||
DbgPrint("\n");
|
||||
#endif
|
||||
|
||||
Adapter->CurrentTransmitEndIndex++;
|
||||
Adapter->CurrentTransmitEndIndex %= NUMBER_OF_BUFFERS;
|
||||
|
||||
Desc->FLAGS = TD1_OWN | TD1_STP | TD1_ENP;
|
||||
Desc->BCNT = 0xf000 | -TotalPacketLength;
|
||||
|
||||
NdisRawWritePortUshort(Adapter->PortOffset + RAP, CSR0);
|
||||
NdisRawWritePortUshort(Adapter->PortOffset + RDP, CSR0_IENA | CSR0_TDMD);
|
||||
|
||||
return NDIS_STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
|
|
@ -998,8 +1039,9 @@ DriverEntry(
|
|||
NDIS_MINIPORT_CHARACTERISTICS Characteristics;
|
||||
NDIS_STATUS Status;
|
||||
|
||||
memset(&Characteristics, 0, sizeof(Characteristics));
|
||||
Characteristics.MajorNdisVersion = 4;
|
||||
RtlZeroMemory(&Characteristics, sizeof(Characteristics));
|
||||
Characteristics.MajorNdisVersion = 5;
|
||||
Characteristics.MinorNdisVersion = 0;
|
||||
Characteristics.HaltHandler = MiniportHalt;
|
||||
Characteristics.HandleInterruptHandler = MiniportHandleInterrupt;
|
||||
Characteristics.InitializeHandler = MiniportInitialize;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* ReactOS AMD PCNet Driver
|
||||
* Copyright (C) 1998, 1999, 2000, 2001 ReactOS Team
|
||||
*
|
||||
* Copyright (C) 2003 Vizzini <vizzini@plasmic.com>
|
||||
* Copyright (C) 2004 Filip Navara <navaraf@reactos.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -16,15 +18,9 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
* PROJECT: ReactOS AMD PCNet Driver
|
||||
* FILE: pcnet/pcnet.h
|
||||
* PURPOSE: PCNet Device Driver
|
||||
* PROGRAMMER: Vizzini (vizzini@plasmic.com)
|
||||
* REVISIONS:
|
||||
* 1-Sept-2003 vizzini - Created
|
||||
* 01-Sep-2003 vizzini - Created
|
||||
* NOTES:
|
||||
* - this is hard-coded to NDIS4
|
||||
* - this assumes a little-endian machine
|
||||
* - this assumes a 32-bit machine, where sizeof(PVOID) = 32 and sizeof(USHORT) = 16
|
||||
* - this assumes 32-bit physical addresses
|
||||
*/
|
||||
|
|
@ -37,8 +33,6 @@ typedef struct _ADAPTER
|
|||
{
|
||||
NDIS_HANDLE MiniportAdapterHandle;
|
||||
ULONG Flags;
|
||||
ULONG BusNumber;
|
||||
ULONG SlotNumber;
|
||||
ULONG InterruptVector;
|
||||
ULONG IoBaseAddress;
|
||||
PVOID PortOffset;
|
||||
|
|
@ -47,6 +41,10 @@ typedef struct _ADAPTER
|
|||
ULONG CurrentPacketFilter;
|
||||
ULONG CurrentLookaheadSize;
|
||||
|
||||
/* circular indexes to transmit descriptors */
|
||||
ULONG CurrentTransmitStartIndex;
|
||||
ULONG CurrentTransmitEndIndex;
|
||||
|
||||
/* initialization block */
|
||||
ULONG InitializationBlockLength;
|
||||
PINITIALIZATION_BLOCK InitializationBlockVirt;
|
||||
|
|
@ -71,7 +69,6 @@ typedef struct _ADAPTER
|
|||
ULONG ReceiveBufferLength;
|
||||
PCHAR ReceiveBufferPtrVirt;
|
||||
PCHAR ReceiveBufferPtrPhys;
|
||||
|
||||
} ADAPTER, *PADAPTER;
|
||||
|
||||
/* forward declarations */
|
||||
|
|
@ -123,15 +120,5 @@ MiniportSetInformation(
|
|||
/* memory pool tag */
|
||||
#define PCNET_TAG 0xbaadf00d
|
||||
|
||||
/* stack validation */
|
||||
#define STACKENTER __asm__("movl %%esp, %0\n" : "=m" (esp));
|
||||
|
||||
#define STACKLEAVE {\
|
||||
unsigned long esptemp = esp; \
|
||||
__asm__ ("movl %%esp, %0\n": "=m" (esp)); \
|
||||
if(esp != esptemp) \
|
||||
__asm__ ("int $3\n"); \
|
||||
}
|
||||
|
||||
#endif // _PCNET_H_
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/*
|
||||
* ReactOS AMD PCNet Driver
|
||||
* Copyright (C) 1998, 1999, 2000, 2001 ReactOS Team
|
||||
*
|
||||
* Copyright (C) 2003 Vizzini <vizzini@plasmic.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -16,17 +17,18 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
* PROJECT: ReactOS AMD PCNet Driver
|
||||
* FILE: drivers/net/dd/pcnet/pcnethw.h
|
||||
* PURPOSE: PCNet hardware configuration constants
|
||||
* PROGRAMMER: Vizzini (vizzini@plasmic.com)
|
||||
* PURPOSE:
|
||||
* PCNet hardware configuration constants
|
||||
* REVISIONS:
|
||||
* 1-Sept-2003 vizzini - Created
|
||||
* 01-Sept-2003 vizzini - Created
|
||||
* NOTES:
|
||||
* - This file represents a clean re-implementation from the AMD
|
||||
* PCNet II chip documentation (Am79C790A, pub# 19436).
|
||||
*/
|
||||
|
||||
#ifndef _PCNETHW_
|
||||
#define _PCNETHW_
|
||||
|
||||
/* when in 32-bit mode, most registers require the top 16 bits be 0. */
|
||||
#define MASK16(__x__) ((__x__) & 0x0000ffff)
|
||||
|
||||
|
|
@ -408,4 +410,4 @@ typedef struct _TRANSMIT_DESCRIPTOR
|
|||
#define TD2_UFLO 0x4000 /* buffer underflow */
|
||||
#define TD2_BUFF 0x8000 /* buffer error */
|
||||
|
||||
|
||||
#endif /* _PCNETHW_ */
|
||||
|
|
|
|||
|
|
@ -1,6 +1,9 @@
|
|||
/*
|
||||
* ReactOS AMD PCNet Driver
|
||||
* Copyright (C) 1998, 1999, 2000, 2001 ReactOS Team
|
||||
*
|
||||
* Copyright (C) 2000 Casper Hornstroup <chorns@users.sourceforge.net>
|
||||
* Copyright (C) 2003 Vizzini <vizzini@plasmic.com>
|
||||
* Copyright (C) 2004 Filip Navara <navaraf@reactos.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -16,16 +19,14 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
* PROJECT: ReactOS AMD PCNet Driver
|
||||
* FILE: drivers/net/dd/pcnet/pcnet.c
|
||||
* PURPOSE: PCNet Device Driver
|
||||
* PROGRAMMERS: Vizzini (vizzini@plasmic.com),
|
||||
* PROGRAMMERS:
|
||||
* Vizzini (vizzini@plasmic.com),
|
||||
* borrowed very heavily from the ReactOS ne2000 driver by
|
||||
* Casper S. Hornstrup (chorns@users.sourceforge.net)
|
||||
* REVISIONS:
|
||||
* 14-Sept-2003 vizzini - Created
|
||||
* NOTES:
|
||||
*/
|
||||
|
||||
#include <ndis.h>
|
||||
#include "pcnethw.h"
|
||||
#include "pcnet.h"
|
||||
|
|
@ -124,12 +125,13 @@ MiniportQueryInformation(
|
|||
case OID_GEN_MEDIA_SUPPORTED:
|
||||
case OID_GEN_MEDIA_IN_USE:
|
||||
{
|
||||
NDIS_MEDIUM Medium = NdisMedium802_3;
|
||||
static const NDIS_MEDIUM Medium = NdisMedium802_3;
|
||||
CopyFrom = (PVOID)&Medium;
|
||||
CopySize = sizeof(NDIS_MEDIUM);
|
||||
break;
|
||||
}
|
||||
|
||||
case OID_GEN_CURRENT_LOOKAHEAD:
|
||||
case OID_GEN_MAXIMUM_LOOKAHEAD:
|
||||
{
|
||||
GenericULONG = 1500;
|
||||
|
|
@ -202,13 +204,6 @@ MiniportQueryInformation(
|
|||
break;
|
||||
}
|
||||
|
||||
case OID_GEN_CURRENT_LOOKAHEAD:
|
||||
{
|
||||
/* XXX make me a constant */
|
||||
GenericULONG = 1500;
|
||||
break;
|
||||
}
|
||||
|
||||
case OID_GEN_DRIVER_VERSION:
|
||||
{
|
||||
GenericULONG = 1;
|
||||
|
|
@ -294,7 +289,7 @@ MiniportQueryInformation(
|
|||
{
|
||||
*BytesNeeded = (CopySize - InformationBufferLength);
|
||||
*BytesWritten = 0;
|
||||
Status = NDIS_STATUS_INVALID_LENGTH;
|
||||
Status = NDIS_STATUS_BUFFER_TOO_SHORT;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue