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[NTOS:KE] Improve readability of CPU flag checks and fix error checking wrong register for HT support

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This commit is contained in:
Ivan Labutin 2017-11-10 19:44:30 +03:00 committed by Timo Kreuzer
parent 5857733996
commit ede3f4d449
2 changed files with 47 additions and 24 deletions
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25
ntoskrnl/include/internal/amd64/ke.h
View file

@ -22,19 +22,42 @@
#define X86_CR4_OSFXSR 0x00000200 /* enable FXSAVE/FXRSTOR instructions */
#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable #XF exception */
/* EDX flags */
#define X86_FEATURE_FPU 0x00000001 /* x87 FPU is present */
#define X86_FEATURE_VME 0x00000002 /* Virtual 8086 Extensions are present */
#define X86_FEATURE_DBG 0x00000004 /* Debugging extensions are present */
#define X86_FEATURE_PSE 0x00000008 /* Page Size Extension is present */
#define X86_FEATURE_TSC 0x00000010 /* time stamp counters are present */
#define X86_FEATURE_PAE 0x00000040 /* physical address extension is present */
#define X86_FEATURE_CX8 0x00000100 /* CMPXCHG8B instruction present */
#define X86_FEATURE_SYSCALL 0x00000800 /* SYSCALL/SYSRET support present */
#define X86_FEATURE_MTTR 0x00001000 /* Memory type range registers are present */
#define X86_FEATURE_PGE 0x00002000 /* Page Global Enable */
#define X86_FEATURE_NX 0x00100000 /* NX support present */
#define X86_FEATURE_CMOV 0x00008000 /* "Conditional move" instruction supported */
#define X86_FEATURE_PAT 0x00010000 /* Page Attribute Table is supported */
#define X86_FEATURE_DS 0x00200000 /* Debug Store is present */
#define X86_FEATURE_MMX 0x00800000 /* MMX extension present */
#define X86_FEATURE_FXSR 0x01000000 /* FXSAVE/FXRSTOR instructions present */
#define X86_FEATURE_SSE 0x02000000 /* SSE extension present */
#define X86_FEATURE_SSE2 0x04000000 /* SSE2 extension present */
#define X86_FEATURE_HT 0x10000000 /* Hyper-Threading present */
/* ECX flags */
#define X86_FEATURE_SSE3 0x00000001 /* SSE3 is supported */
#define X86_FEATURE_MONITOR 0x00000008 /* SSE3 Monitor instructions supported */
#define X86_FEATURE_VMX 0x00000020 /* Virtual Machine eXtensions are available */
#define X86_FEATURE_SSSE3 0x00000200 /* Supplemental SSE3 are available */
#define X86_FEATURE_FMA3 0x00001000 /* Fused multiple-add supported */
#define X86_FEATURE_CX16 0x00002000 /* CMPXCHG16B instruction are available */
#define X86_FEATURE_PCID 0x00020000 /* Process Context IDentifiers are supported */
#define X86_FEATURE_SSE41 0x00080000 /* SSE 4.1 is supported */
#define X86_FEATURE_SSE42 0x00100000 /* SSE 4.2 is supported */
#define X86_FEATURE_POPCNT 0x00800000 /* POPCNT instruction is available */
#define X86_FEATURE_XSAVE 0x04000000 /* XSAVE family are available */
/* EDX extended flags */
#define X86_FEATURE_NX 0x00100000 /* NX support present */
#define X86_EXT_FEATURE_SSE3 0x00000001 /* SSE3 extension present */
#define X86_EXT_FEATURE_3DNOW 0x40000000 /* 3DNOW! extension present */

46
ntoskrnl/ke/amd64/cpu.c
View file

@ -152,31 +152,31 @@ KiGetFeatureBits(VOID)
Prcb->InitialApicId = (UCHAR)(CpuInfo.Ebx >> 24);
/* Convert all CPUID Feature bits into our format */
if (CpuInfo.Edx & 0x00000002) FeatureBits |= KF_V86_VIS | KF_CR4;
if (CpuInfo.Edx & 0x00000008) FeatureBits |= KF_LARGE_PAGE | KF_CR4;
if (CpuInfo.Edx & 0x00000010) FeatureBits |= KF_RDTSC;
if (CpuInfo.Edx & 0x00000100) FeatureBits |= KF_CMPXCHG8B;
if (CpuInfo.Edx & 0x00000800) FeatureBits |= KF_FAST_SYSCALL;
if (CpuInfo.Edx & 0x00001000) FeatureBits |= KF_MTRR;
if (CpuInfo.Edx & 0x00002000) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4;
if (CpuInfo.Edx & 0x00008000) FeatureBits |= KF_CMOV;
if (CpuInfo.Edx & 0x00010000) FeatureBits |= KF_PAT;
if (CpuInfo.Edx & 0x00200000) FeatureBits |= KF_DTS;
if (CpuInfo.Edx & 0x00800000) FeatureBits |= KF_MMX;
if (CpuInfo.Edx & 0x01000000) FeatureBits |= KF_FXSR;
if (CpuInfo.Edx & 0x02000000) FeatureBits |= KF_XMMI;
if (CpuInfo.Edx & 0x04000000) FeatureBits |= KF_XMMI64;
if (CpuInfo.Edx & X86_FEATURE_VME) FeatureBits |= KF_V86_VIS | KF_CR4;
if (CpuInfo.Edx & X86_FEATURE_PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4;
if (CpuInfo.Edx & X86_FEATURE_TSC) FeatureBits |= KF_RDTSC;
if (CpuInfo.Edx & X86_FEATURE_CX8) FeatureBits |= KF_CMPXCHG8B;
if (CpuInfo.Edx & X86_FEATURE_SYSCALL) FeatureBits |= KF_FAST_SYSCALL;
if (CpuInfo.Edx & X86_FEATURE_MTTR) FeatureBits |= KF_MTRR;
if (CpuInfo.Edx & X86_FEATURE_PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4;
if (CpuInfo.Edx & X86_FEATURE_CMOV) FeatureBits |= KF_CMOV;
if (CpuInfo.Edx & X86_FEATURE_PAT) FeatureBits |= KF_PAT;
if (CpuInfo.Edx & X86_FEATURE_DS) FeatureBits |= KF_DTS;
if (CpuInfo.Edx & X86_FEATURE_MMX) FeatureBits |= KF_MMX;
if (CpuInfo.Edx & X86_FEATURE_FXSR) FeatureBits |= KF_FXSR;
if (CpuInfo.Edx & X86_FEATURE_SSE) FeatureBits |= KF_XMMI;
if (CpuInfo.Edx & X86_FEATURE_SSE2) FeatureBits |= KF_XMMI64;
if (CpuInfo.Ecx & 0x00000001) FeatureBits |= KF_SSE3;
//if (CpuInfo.Ecx & 0x00000008) FeatureBits |= KF_MONITOR;
//if (CpuInfo.Ecx & 0x00000200) FeatureBits |= KF_SSE3SUP;
if (CpuInfo.Ecx & 0x00002000) FeatureBits |= KF_CMPXCHG16B;
//if (CpuInfo.Ecx & 0x00080000) FeatureBits |= KF_SSE41;
//if (CpuInfo.Ecx & 0x00800000) FeatureBits |= KF_POPCNT;
if (CpuInfo.Ecx & 0x04000000) FeatureBits |= KF_XSTATE;
if (CpuInfo.Ecx & X86_FEATURE_SSE3) FeatureBits |= KF_SSE3;
//if (CpuInfo.Ecx & X86_FEATURE_MONITOR) FeatureBits |= KF_MONITOR;
//if (CpuInfo.Ecx & X86_FEATURE_SSSE3) FeatureBits |= KF_SSE3SUP;
if (CpuInfo.Ecx & X86_FEATURE_CX16) FeatureBits |= KF_CMPXCHG16B;
//if (CpuInfo.Ecx & X86_FEATURE_SSE41) FeatureBits |= KF_SSE41;
//if (CpuInfo.Ecx & X86_FEATURE_POPCNT) FeatureBits |= KF_POPCNT;
if (CpuInfo.Ecx & X86_FEATURE_XSAVE) FeatureBits |= KF_XSTATE;
/* Check if the CPU has hyper-threading */
if (CpuInfo.Ecx & 0x10000000)
if (CpuInfo.Edx & X86_FEATURE_HT)
{
/* Set the number of logical CPUs */
Prcb->LogicalProcessorsPerPhysicalProcessor = (UCHAR)(CpuInfo.Ebx >> 16);
@ -203,7 +203,7 @@ KiGetFeatureBits(VOID)
KiCpuId(&CpuInfo, 0x80000001);
/* Check if NX-bit is supported */
if (CpuInfo.Edx & 0x00100000) FeatureBits |= KF_NX_BIT;
if (CpuInfo.Edx & X86_FEATURE_NX) FeatureBits |= KF_NX_BIT;
/* Now handle each features for each CPU Vendor */
switch (Vendor)