[HALX86] Convert the PCI Ids files to LF ('\n') endlines, and adjust the parsing code. (#4905)

This allows to somewhat reduce their size, and the resulting size
of the generated hal.dll file.

pci_classes.ids
Before: 6,207 bytes
After : 5,968 bytes
Reduction: 239 bytes --> 4%

pci_vendors.ids
Before: 1,370,248 bytes
After : 1,334,622 bytes
Reduction: 35,626 bytes --> 2.6%

Co-authored-by: Stanislav Motylkov <x86corez@gmail.com>
This commit is contained in:
Hermès Bélusca-Maïto 2022-11-25 16:34:52 +01:00
parent 97277b4deb
commit eba1244b00
No known key found for this signature in database
GPG key ID: 3B2539C65E7B93D0
4 changed files with 29 additions and 35890 deletions

View file

@ -1,3 +1,3 @@
# The HAL expects these files to be in CR-LF. # The HAL expects these files to be in LF.
pci_classes.ids text eol=crlf pci_classes.ids text eol=lf
pci_vendors.ids text eol=crlf pci_vendors.ids text eol=lf

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@ -1,239 +0,0 @@
#
# Extracted from the pci.ids database at https://pci-ids.ucw.cz/
#
#
# List of PCI ID's
#
# Version: 2022.11.25
# Date: 2022-11-25 03:15:01
#
# Maintained by Albert Pool, Martin Mares, and other volunteers from
# the PCI ID Project at https://pci-ids.ucw.cz/.
#
# New data are always welcome, especially if they are accurate. If you have
# anything to contribute, please follow the instructions at the web site.
#
# This file can be distributed under either the GNU General Public License
# (version 2 or higher) or the 3-clause BSD License.
#
# The database is a compilation of factual data, and as such the copyright
# only covers the aggregation and formatting. The copyright is held by
# Martin Mares and Albert Pool.
#
# List of known device classes, subclasses and programming interfaces
# Syntax:
# C class class_name
# subclass subclass_name <-- single tab
# prog-if prog-if_name <-- two tabs
C 00 Unclassified device
00 Non-VGA unclassified device
01 VGA compatible unclassified device
05 Image coprocessor
C 01 Mass storage controller
00 SCSI storage controller
01 IDE interface
00 ISA Compatibility mode-only controller
05 PCI native mode-only controller
0a ISA Compatibility mode controller, supports both channels switched to PCI native mode
0f PCI native mode controller, supports both channels switched to ISA compatibility mode
80 ISA Compatibility mode-only controller, supports bus mastering
85 PCI native mode-only controller, supports bus mastering
8a ISA Compatibility mode controller, supports both channels switched to PCI native mode, supports bus mastering
8f PCI native mode controller, supports both channels switched to ISA compatibility mode, supports bus mastering
02 Floppy disk controller
03 IPI bus controller
04 RAID bus controller
05 ATA controller
20 ADMA single stepping
30 ADMA continuous operation
06 SATA controller
00 Vendor specific
01 AHCI 1.0
02 Serial Storage Bus
07 Serial Attached SCSI controller
01 Serial Storage Bus
08 Non-Volatile memory controller
01 NVMHCI
02 NVM Express
80 Mass storage controller
C 02 Network controller
00 Ethernet controller
01 Token ring network controller
02 FDDI network controller
03 ATM network controller
04 ISDN controller
05 WorldFip controller
06 PICMG controller
07 Infiniband controller
08 Fabric controller
80 Network controller
C 03 Display controller
00 VGA compatible controller
00 VGA controller
01 8514 controller
01 XGA compatible controller
02 3D controller
80 Display controller
C 04 Multimedia controller
00 Multimedia video controller
01 Multimedia audio controller
02 Computer telephony device
03 Audio device
80 Multimedia controller
C 05 Memory controller
00 RAM memory
01 FLASH memory
02 CXL
00 CXL Memory Device - vendor specific
10 CXL Memory Device (CXL 2.x)
80 Memory controller
C 06 Bridge
00 Host bridge
01 ISA bridge
02 EISA bridge
03 MicroChannel bridge
04 PCI bridge
00 Normal decode
01 Subtractive decode
05 PCMCIA bridge
06 NuBus bridge
07 CardBus bridge
08 RACEway bridge
00 Transparent mode
01 Endpoint mode
09 Semi-transparent PCI-to-PCI bridge
40 Primary bus towards host CPU
80 Secondary bus towards host CPU
0a InfiniBand to PCI host bridge
80 Bridge
C 07 Communication controller
00 Serial controller
00 8250
01 16450
02 16550
03 16650
04 16750
05 16850
06 16950
01 Parallel controller
00 SPP
01 BiDir
02 ECP
03 IEEE1284
fe IEEE1284 Target
02 Multiport serial controller
03 Modem
00 Generic
01 Hayes/16450
02 Hayes/16550
03 Hayes/16650
04 Hayes/16750
04 GPIB controller
05 Smard Card controller
80 Communication controller
C 08 Generic system peripheral
00 PIC
00 8259
01 ISA PIC
02 EISA PIC
10 IO-APIC
20 IO(X)-APIC
01 DMA controller
00 8237
01 ISA DMA
02 EISA DMA
02 Timer
00 8254
01 ISA Timer
02 EISA Timers
03 HPET
03 RTC
00 Generic
01 ISA RTC
04 PCI Hot-plug controller
05 SD Host controller
06 IOMMU
80 System peripheral
99 Timing Card
# PTP Grandmaster Source Clock
01 TAP Timing Card
C 09 Input device controller
00 Keyboard controller
01 Digitizer Pen
02 Mouse controller
03 Scanner controller
04 Gameport controller
00 Generic
10 Extended
80 Input device controller
C 0a Docking station
00 Generic Docking Station
80 Docking Station
C 0b Processor
00 386
01 486
02 Pentium
10 Alpha
20 Power PC
30 MIPS
40 Co-processor
C 0c Serial bus controller
00 FireWire (IEEE 1394)
00 Generic
10 OHCI
01 ACCESS Bus
02 SSA
03 USB controller
00 UHCI
10 OHCI
20 EHCI
30 XHCI
40 USB4 Host Interface
80 Unspecified
fe USB Device
04 Fibre Channel
05 SMBus
06 InfiniBand
07 IPMI Interface
00 SMIC
01 KCS
02 BT (Block Transfer)
08 SERCOS interface
09 CANBUS
80 Serial bus controller
C 0d Wireless controller
00 IRDA controller
01 Consumer IR controller
10 RF controller
11 Bluetooth
12 Broadband
20 802.1a controller
21 802.1b controller
80 Wireless controller
C 0e Intelligent controller
00 I2O
C 0f Satellite communications controller
01 Satellite TV controller
02 Satellite audio communication controller
03 Satellite voice communication controller
04 Satellite data communication controller
C 10 Encryption controller
00 Network and computing encryption device
10 Entertainment encryption device
80 Encryption controller
C 11 Signal processing controller
00 DPIO module
01 Performance counters
10 Communication synchronizer
20 Signal processing management
80 Signal processing controller
C 12 Processing accelerators
00 Processing accelerators
01 SNIA Smart Data Accelerator Interface (SDXI) controller
C 13 Non-Essential Instrumentation
C 40 Coprocessor
C ff Unassigned class

File diff suppressed because it is too large Load diff

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@ -679,7 +679,8 @@ HalpGetPciBridgeConfig(IN ULONG PciType,
if (!HalpIsBridgeDevice(PciData)) continue; if (!HalpIsBridgeDevice(PciData)) continue;
/* Not supported */ /* Not supported */
if (!WarningsGiven[2]++) DPRINT1("Your machine has a PCI-to-PCI or CardBUS Bridge. PCI devices may fail!\n"); if (!WarningsGiven[2]++)
DPRINT1("Your machine has a PCI-to-PCI or CardBUS Bridge. PCI devices may fail!\n");
continue; continue;
} }
} }
@ -708,7 +709,8 @@ HalpFixupPciSupportedRanges(IN ULONG BusCount)
while (ParentBus) while (ParentBus)
{ {
/* Should merge addresses */ /* Should merge addresses */
if (!WarningsGiven[0]++) DPRINT1("Found parent bus (indicating PCI Bridge). PCI devices may fail!\n"); if (!WarningsGiven[0]++)
DPRINT1("Found parent bus (indicating PCI Bridge). PCI devices may fail!\n");
/* Check the next parent */ /* Check the next parent */
ParentBus = ParentBus->ParentHandler; ParentBus = ParentBus->ParentHandler;
@ -732,7 +734,8 @@ HalpFixupPciSupportedRanges(IN ULONG BusCount)
if (ParentBus->InterfaceType == PCIBus) if (ParentBus->InterfaceType == PCIBus)
{ {
/* Should trim addresses */ /* Should trim addresses */
if (!WarningsGiven[1]++) DPRINT1("Found parent PCI Bus (indicating PCI-to-PCI Bridge). PCI devices may fail!\n"); if (!WarningsGiven[1]++)
DPRINT1("Found parent PCI Bus (indicating PCI-to-PCI Bridge). PCI devices may fail!\n");
} }
/* Check the next parent */ /* Check the next parent */
@ -782,6 +785,7 @@ ShowSize(ULONG x)
* These includes are required to define * These includes are required to define
* the ClassTable and VendorTable arrays. * the ClassTable and VendorTable arrays.
*/ */
#define NEWLINE "\n" // "\r\n"
#include "pci_classes.h" #include "pci_classes.h"
#include "pci_vendors.h" #include "pci_vendors.h"
CODE_SEG("INIT") CODE_SEG("INIT")
@ -813,8 +817,8 @@ HalpDebugPciDumpBus(IN PBUS_HANDLER BusHandler,
{ {
/* Isolate the subclass name */ /* Isolate the subclass name */
ClassName += strlen("C 00 "); ClassName += strlen("C 00 ");
Boundary = strstr(ClassName, "\nC "); Boundary = strstr(ClassName, NEWLINE "C ");
sprintf(LookupString, "\n\t%02x ", PciData->SubClass); sprintf(LookupString, NEWLINE "\t%02x ", PciData->SubClass);
SubClassName = strstr(ClassName, LookupString); SubClassName = strstr(ClassName, LookupString);
if (Boundary && SubClassName > Boundary) if (Boundary && SubClassName > Boundary)
{ {
@ -826,33 +830,33 @@ HalpDebugPciDumpBus(IN PBUS_HANDLER BusHandler,
} }
else else
{ {
SubClassName += strlen("\n\t00 "); SubClassName += strlen(NEWLINE "\t00 ");
} }
/* Copy the subclass into our buffer */ /* Copy the subclass into our buffer */
p = strpbrk(SubClassName, "\r\n"); p = strpbrk(SubClassName, NEWLINE);
Length = p - SubClassName; Length = p - SubClassName;
if (Length >= sizeof(bSubClassName)) Length = sizeof(bSubClassName) - 1; Length = min(Length, sizeof(bSubClassName) - 1);
strncpy(bSubClassName, SubClassName, Length); strncpy(bSubClassName, SubClassName, Length);
bSubClassName[Length] = '\0'; bSubClassName[Length] = '\0';
} }
/* Isolate the vendor name */ /* Isolate the vendor name */
sprintf(LookupString, "\r\n%04x ", PciData->VendorID); sprintf(LookupString, NEWLINE "%04x ", PciData->VendorID);
VendorName = strstr((PCHAR)VendorTable, LookupString); VendorName = strstr((PCHAR)VendorTable, LookupString);
if (VendorName) if (VendorName)
{ {
/* Copy the vendor name into our buffer */ /* Copy the vendor name into our buffer */
VendorName += strlen("\r\n0000 "); VendorName += strlen(NEWLINE "0000 ");
p = strpbrk(VendorName, "\r\n"); p = strpbrk(VendorName, NEWLINE);
Length = p - VendorName; Length = p - VendorName;
if (Length >= sizeof(bVendorName)) Length = sizeof(bVendorName) - 1; Length = min(Length, sizeof(bVendorName) - 1);
strncpy(bVendorName, VendorName, Length); strncpy(bVendorName, VendorName, Length);
bVendorName[Length] = '\0'; bVendorName[Length] = '\0';
p += strlen("\r\n"); p += strlen(NEWLINE);
while (*p == '\t' || *p == '#') while (*p == '\t' || *p == '#')
{ {
p = strpbrk(p, "\r\n"); p = strpbrk(p, NEWLINE);
p += strlen("\r\n"); p += strlen(NEWLINE);
} }
Boundary = p; Boundary = p;
@ -867,16 +871,16 @@ HalpDebugPciDumpBus(IN PBUS_HANDLER BusHandler,
{ {
/* Copy the product name into our buffer */ /* Copy the product name into our buffer */
ProductName += strlen("\t0000 "); ProductName += strlen("\t0000 ");
p = strpbrk(ProductName, "\r\n"); p = strpbrk(ProductName, NEWLINE);
Length = p - ProductName; Length = p - ProductName;
if (Length >= sizeof(bProductName)) Length = sizeof(bProductName) - 1; Length = min(Length, sizeof(bProductName) - 1);
strncpy(bProductName, ProductName, Length); strncpy(bProductName, ProductName, Length);
bProductName[Length] = '\0'; bProductName[Length] = '\0';
p += strlen("\r\n"); p += strlen(NEWLINE);
while ((*p == '\t' && *(p + 1) == '\t') || *p == '#') while ((*p == '\t' && *(p + 1) == '\t') || *p == '#')
{ {
p = strpbrk(p, "\r\n"); p = strpbrk(p, NEWLINE);
p += strlen("\r\n"); p += strlen(NEWLINE);
} }
Boundary = p; Boundary = p;
SubVendorName = NULL; SubVendorName = NULL;
@ -898,9 +902,9 @@ HalpDebugPciDumpBus(IN PBUS_HANDLER BusHandler,
{ {
/* Copy the subvendor name into our buffer */ /* Copy the subvendor name into our buffer */
SubVendorName += strlen("\t\t0000 0000 "); SubVendorName += strlen("\t\t0000 0000 ");
p = strpbrk(SubVendorName, "\r\n"); p = strpbrk(SubVendorName, NEWLINE);
Length = p - SubVendorName; Length = p - SubVendorName;
if (Length >= sizeof(bSubVendorName)) Length = sizeof(bSubVendorName) - 1; Length = min(Length, sizeof(bSubVendorName) - 1);
strncpy(bSubVendorName, SubVendorName, Length); strncpy(bSubVendorName, SubVendorName, Length);
bSubVendorName[Length] = '\0'; bSubVendorName[Length] = '\0';
} }