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https://github.com/reactos/reactos.git
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- Changed Video Mode setting routines to directly modify VGA registers instead on relying on Int 0x10 services.
- Removed unused code. svn path=/trunk/; revision=8531
This commit is contained in:
Filip Navara
parent
1849adaa6b
commit
eab00ba2a1
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@ -1,129 +1,119 @@
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#include <ntddk.h>
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#include <rosrtl/string.h>
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#include "vgavideo.h"
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#define NDEBUG
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#include <debug.h>
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void outxay(PUSHORT ad, UCHAR x, UCHAR y)
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static VGA_REGISTERS Mode12Regs =
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{
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USHORT xy = (x << 8) + y;
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VideoPortWritePortUshort(ad, xy);
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}
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void setMode(VideoMode mode)
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{
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unsigned char x;
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VideoPortWritePortUchar((PUCHAR)MISC, mode.Misc);
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VideoPortWritePortUchar((PUCHAR)STATUS, 0);
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VideoPortWritePortUchar((PUCHAR)FEATURE, mode.Feature);
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for(x=0; x<5; x++)
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{
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outxay((PUSHORT)SEQ, mode.Seq[x], x);
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}
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VideoPortWritePortUshort((PUSHORT)CRTC, 0x11);
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VideoPortWritePortUshort((PUSHORT)CRTC, (mode.Crtc[0x11] & 0x7f));
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for(x=0; x<25; x++)
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{
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outxay((PUSHORT)CRTC, mode.Crtc[x], x);
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}
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for(x=0; x<9; x++)
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{
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outxay((PUSHORT)GRAPHICS, mode.Gfx[x], x);
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}
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x=VideoPortReadPortUchar((PUCHAR)FEATURE);
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for(x=0; x<21; x++)
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{
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VideoPortWritePortUchar((PUCHAR)ATTRIB, x);
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VideoPortWritePortUchar((PUCHAR)ATTRIB, mode.Attrib[x]);
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}
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x=VideoPortReadPortUchar((PUCHAR)STATUS);
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VideoPortWritePortUchar((PUCHAR)ATTRIB, 0x20);
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}
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VideoMode Mode12 = {
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0xa000, 0xe3, 0x00,
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{0x03, 0x01, 0x0f, 0x00, 0x06 },
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{0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, 0x00, 0x40, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x59, 0xea, 0x8c, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3,
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0xff},
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{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff},
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{0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
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0x0c, 0x0d, 0x0e, 0x0f, 0x81, 0x00, 0x0f, 0x00, 0x00}
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/* CRT Controller Registers */
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{0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0x0B, 0x3E, 0x00, 0x40, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x59, 0xEA, 0x8C, 0xDF, 0x28, 0x00, 0xE7, 0x04, 0xE3},
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/* Attribute Controller Registers */
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{0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
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0x0C, 0x0D, 0x0E, 0x0F, 0x81, 0x00, 0x0F, 0x00, 0x00},
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/* Graphics Controller Registers */
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{0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x0F, 0xFF},
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/* Sequencer Registers */
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{0x03, 0x01, 0x0F, 0x00, 0x06},
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/* Misc Output Register */
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0xE3
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};
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void InitVGAMode()
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VGA_REGISTERS TextModeRegs;
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STATIC VOID FASTCALL
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vgaSaveRegisters(PVGA_REGISTERS Registers)
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{
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int i;
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VIDEO_X86_BIOS_ARGUMENTS vxba;
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VP_STATUS vps;
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// FIXME: Use Vidport to map the memory properly
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vidmem = (char *)(0xd0000000 + 0xa0000);
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memset(&vxba, 0, sizeof(vxba));
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vxba.Eax = 0x0012;
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vps = VideoPortInt10(NULL, &vxba);
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int i;
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// Get VGA registers into the correct state (mainly for setting up the palette registers correctly)
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setMode(Mode12);
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for (i = 0; i < sizeof(Registers->CRT); i++)
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{
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VideoPortWritePortUchar(CRTC, i);
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Registers->CRT[i] = VideoPortReadPortUchar(CRTCDATA);
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}
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// Get the VGA into the mode we want to work with
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WRITE_PORT_UCHAR((PUCHAR)GRA_I,0x08); // Set
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WRITE_PORT_UCHAR((PUCHAR)GRA_D,0); // the MASK
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WRITE_PORT_USHORT((PUSHORT)GRA_I,0x0205); // write mode = 2 (bits 0,1) read mode = 0 (bit 3)
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i = READ_REGISTER_UCHAR(vidmem); // Update bit buffer
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WRITE_REGISTER_UCHAR(vidmem, 0); // Write the pixel
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WRITE_PORT_UCHAR((PUCHAR)GRA_I,0x08);
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WRITE_PORT_UCHAR((PUCHAR)GRA_D,0xff);
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for (i = 0; i < sizeof(Registers->Attribute); i++)
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{
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VideoPortReadPortUchar(STATUS);
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VideoPortWritePortUchar(ATTRIB, i);
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Registers->Attribute[i] = VideoPortReadPortUchar(ATTRIBREAD);
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}
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// Zero out video memory (clear a possibly trashed screen)
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RtlZeroMemory(vidmem, 64000);
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for (i = 0; i < sizeof(Registers->Graphics); i++)
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{
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VideoPortWritePortUchar(GRAPHICS, i);
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Registers->Graphics[i] = VideoPortReadPortUchar(GRAPHICSDATA);
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}
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vgaPreCalc();
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for (i = 0; i < sizeof(Registers->Sequencer); i++)
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{
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VideoPortWritePortUchar(SEQ, i);
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Registers->Sequencer[i] = VideoPortReadPortUchar(SEQDATA);
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}
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Registers->Misc = VideoPortReadPortUchar(MISC);
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}
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VOID VGAResetDevice(OUT PSTATUS_BLOCK StatusBlock)
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STATIC VOID FASTCALL
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vgaSetRegisters(PVGA_REGISTERS Registers)
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{
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HANDLE Event;
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OBJECT_ATTRIBUTES Attr;
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UNICODE_STRING Name = ROS_STRING_INITIALIZER(L"\\TextConsoleRefreshEvent");
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NTSTATUS Status;
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VIDEO_X86_BIOS_ARGUMENTS vxba;
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VP_STATUS vps;
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ULONG ThreadRelease = 1;
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CHECKPOINT;
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Event = 0;
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int i;
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memset(&vxba, 0, sizeof(vxba));
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vxba.Eax = 0x0003;
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vps = VideoPortInt10(NULL, &vxba);
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memset(&vxba, 0, sizeof(vxba));
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vxba.Eax = 0x1112;
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vps = VideoPortInt10(NULL, &vxba);
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InitializeObjectAttributes( &Attr, &Name, 0, 0, 0 );
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Status = ZwOpenEvent( &Event, STANDARD_RIGHTS_ALL, &Attr );
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if( !NT_SUCCESS( Status ) )
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DbgPrint( "VGA: Failed to open refresh event\n" );
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else {
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ZwSetEvent( Event, &ThreadRelease );
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ZwClose( Event );
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}
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/* Update misc output register */
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VideoPortWritePortUchar(MISC, Registers->Misc);
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/* Synchronous reset on */
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VideoPortWritePortUchar(SEQ, 0x00);
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VideoPortWritePortUchar(SEQDATA, 0x01);
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/* Write sequencer registers */
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for (i = 1; i < sizeof(Registers->Sequencer); i++)
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{
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VideoPortWritePortUchar(SEQ, i);
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VideoPortWritePortUchar(SEQDATA, Registers->Sequencer[i]);
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}
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/* Synchronous reset off */
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VideoPortWritePortUchar(SEQ, 0x00);
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VideoPortWritePortUchar(SEQDATA, 0x03);
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/* Deprotect CRT registers 0-7 */
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VideoPortWritePortUchar(CRTC, 0x11);
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VideoPortWritePortUchar(CRTCDATA, Registers->CRT[0x11] & 0x7f);
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/* Write CRT registers */
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for (i = 0; i < sizeof(Registers->CRT); i++)
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{
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VideoPortWritePortUchar(CRTC, i);
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VideoPortWritePortUchar(CRTCDATA, Registers->CRT[i]);
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}
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/* Write graphics controller registers */
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for (i = 0; i < sizeof(Registers->Graphics); i++)
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{
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VideoPortWritePortUchar(GRAPHICS, i);
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VideoPortWritePortUchar(GRAPHICSDATA, Registers->Graphics[i]);
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}
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/* Write attribute controller registers */
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for (i = 0; i < sizeof(Registers->Attribute); i++)
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{
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VideoPortReadPortUchar(STATUS);
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VideoPortWritePortUchar(ATTRIB, i);
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VideoPortWritePortUchar(ATTRIB, Registers->Attribute[i]);
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}
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}
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VOID
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InitVGAMode()
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{
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vgaSaveRegisters(&TextModeRegs);
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vgaSetRegisters(&Mode12Regs);
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}
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VOID
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VGAResetDevice(OUT PSTATUS_BLOCK StatusBlock)
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{
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vgaSetRegisters(&TextModeRegs);
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}
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@ -1,4 +1,4 @@
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# $Id: makefile,v 1.1 2004/01/10 14:39:21 navaraf Exp $
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# $Id: makefile,v 1.2 2004/03/04 18:49:58 navaraf Exp $
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PATH_TO_TOP = ../../../..
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@ -12,8 +12,7 @@ TARGET_CFLAGS = -Werror -Wall
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TARGET_OBJECTS = \
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initvga.o \
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vgamp.o \
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vgavideo.o
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vgamp.o
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include $(PATH_TO_TOP)/rules.mak
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@ -1,94 +0,0 @@
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#include "vgavideo.h"
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div_t div(int num, int denom)
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{
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div_t r;
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if (num > 0 && denom < 0) {
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num = -num;
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denom = -denom;
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}
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r.quot = num / denom;
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r.rem = num % denom;
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if (num < 0 && denom > 0)
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{
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if (r.rem > 0)
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{
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r.quot++;
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r.rem -= denom;
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}
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}
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return r;
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}
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int mod(int num, int denom)
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{
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div_t dvt = div(num, denom);
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return dvt.rem;
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}
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VOID vgaPreCalc()
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{
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ULONG j;
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startmasks[1] = 127;
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startmasks[2] = 63;
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startmasks[3] = 31;
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startmasks[4] = 15;
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startmasks[5] = 7;
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startmasks[6] = 3;
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startmasks[7] = 1;
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startmasks[8] = 255;
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endmasks[0] = 128;
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endmasks[1] = 192;
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endmasks[2] = 224;
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endmasks[3] = 240;
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endmasks[4] = 248;
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endmasks[5] = 252;
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endmasks[6] = 254;
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endmasks[7] = 255;
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endmasks[8] = 255;
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for(j=0; j<80; j++)
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{
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maskbit[j*8] = 128;
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maskbit[j*8+1] = 64;
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maskbit[j*8+2] = 32;
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maskbit[j*8+3] = 16;
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maskbit[j*8+4] = 8;
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maskbit[j*8+5] = 4;
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maskbit[j*8+6] = 2;
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maskbit[j*8+7] = 1;
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bit8[j*8] = 7;
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bit8[j*8+1] = 6;
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bit8[j*8+2] = 5;
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bit8[j*8+3] = 4;
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bit8[j*8+4] = 3;
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bit8[j*8+5] = 2;
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bit8[j*8+6] = 1;
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bit8[j*8+7] = 0;
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}
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for(j=0; j<480; j++)
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{
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y80[j] = j*80;
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}
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for(j=0; j<640; j++)
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{
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xconv[j] = j >> 3;
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}
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}
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void vgaSetWriteMode(char mode)
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{
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VideoPortWritePortUchar((PUCHAR)GRA_I, 0x03);
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VideoPortWritePortUchar((PUCHAR)GRA_D, mode);
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}
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void vgaSetColor(int cindex, int red, int green, int blue)
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{
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VideoPortWritePortUchar((PUCHAR)0x03c8, cindex);
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VideoPortWritePortUchar((PUCHAR)0x03c9, red);
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VideoPortWritePortUchar((PUCHAR)0x03c9, green);
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VideoPortWritePortUchar((PUCHAR)0x03c9, blue);
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}
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@ -6,36 +6,26 @@
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#define VGA_OR 16
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#define VGA_XOR 24
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//This is in mingw standard headers
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//typedef struct { int quot, rem; } div_t;
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#define MISC (PUCHAR)0x3c2
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#define SEQ (PUCHAR)0x3c4
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#define SEQDATA (PUCHAR)0x3c5
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#define CRTC (PUCHAR)0x3d4
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#define CRTCDATA (PUCHAR)0x3d5
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#define GRAPHICS (PUCHAR)0x3ce
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#define GRAPHICSDATA (PUCHAR)0x3cf
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#define ATTRIB (PUCHAR)0x3c0
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#define ATTRIBREAD (PUCHAR)0x3c1
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#define STATUS (PUCHAR)0x3da
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#define PELMASK (PUCHAR)0x3c6
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#define PELINDEX (PUCHAR)0x3c8
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#define PELDATA (PUCHAR)0x3c9
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#define FEATURE (PUCHAR)0x3da
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int maskbit[640], y80[480], xconv[640], bit8[640], startmasks[8], endmasks[8];
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char* vidmem;
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#define MISC 0x3c2
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#define SEQ 0x3c4
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#define CRTC 0x3d4
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#define GRAPHICS 0x3ce
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#define FEATURE 0x3da
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#define ATTRIB 0x3c0
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#define STATUS 0x3da
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#define SEQ_I 0x3C4 /* Sequencer Index */
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#define SEQ_D 0x3C5 /* Sequencer Data Register */
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#define GRA_I 0x3CE /* Graphics Controller Index */
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#define GRA_D 0x3CF /* Graphics Controller Data Register */
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typedef struct _VideoMode {
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unsigned short VidSeg;
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unsigned char Misc;
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unsigned char Feature;
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unsigned short Seq[6];
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unsigned short Crtc[25];
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unsigned short Gfx[9];
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unsigned char Attrib[21];
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} VideoMode;
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VOID vgaPreCalc();
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typedef struct _VGA_REGISTERS
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{
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UCHAR CRT[24];
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UCHAR Attribute[21];
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UCHAR Graphics[9];
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UCHAR Sequencer[5];
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UCHAR Misc;
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} VGA_REGISTERS, *PVGA_REGISTERS;
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