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- Stored the informations from the cpuid instruction within the KPCR of each processor.
svn path=/trunk/; revision=11648
This commit is contained in:
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59881376cd
commit
ea6e7df66a
4 changed files with 61 additions and 55 deletions
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@ -1,4 +1,4 @@
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/* $Id: sysinfo.c,v 1.58 2004/11/06 16:04:58 ekohl Exp $
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/* $Id: sysinfo.c,v 1.59 2004/11/13 23:08:35 hbirr Exp $
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*
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* COPYRIGHT: See COPYING in the top level directory
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* PROJECT: ReactOS kernel
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@ -23,9 +23,6 @@ ULONGLONG STDCALL KeQueryInterruptTime(VOID);
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VOID MmPrintMemoryStatistic(VOID);
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extern ULONG Ke386CpuidFlags;
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extern ULONG Ke386Cpuid;
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/* FUNCTIONS *****************************************************************/
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/*
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@ -375,7 +372,7 @@ QSI_DEF(SystemProcessorInformation)
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{
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PSYSTEM_PROCESSOR_INFORMATION Spi
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= (PSYSTEM_PROCESSOR_INFORMATION) Buffer;
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PKPCR Pcr;
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*ReqSize = sizeof (SYSTEM_PROCESSOR_INFORMATION);
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/*
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* Check user buffer's size
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@ -384,11 +381,12 @@ QSI_DEF(SystemProcessorInformation)
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{
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return (STATUS_INFO_LENGTH_MISMATCH);
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}
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Pcr = KeGetCurrentKPCR();
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Spi->ProcessorArchitecture = 0; /* Intel Processor */
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Spi->ProcessorLevel = ((Ke386Cpuid >> 8) & 0xf);
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Spi->ProcessorRevision = (Ke386Cpuid & 0xf) | ((Ke386Cpuid << 4) & 0xf00);
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Spi->ProcessorLevel = Pcr->PrcbData.CpuType;
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Spi->ProcessorRevision = Pcr->PrcbData.CpuStep;
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Spi->Unknown = 0;
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Spi->FeatureBits = Ke386CpuidFlags;
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Spi->FeatureBits = Pcr->PrcbData.FeatureBits;
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DPRINT("Arch %d Level %d Rev 0x%x\n", Spi->ProcessorArchitecture,
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Spi->ProcessorLevel, Spi->ProcessorRevision);
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@ -35,16 +35,14 @@
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ULONG KiPcrInitDone = 0;
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static ULONG PcrsAllocated = 0;
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ULONG Ke386CpuidFlags, Ke386CpuidFlags2, Ke386CpuidExFlags;
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ULONG Ke386Cpuid = 0x300;
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static ULONG Ke386CpuidFlags2, Ke386CpuidExFlags;
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ULONG Ke386CacheAlignment;
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CHAR Ke386CpuidVendor[13] = {0,};
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CHAR Ke386CpuidModel[49] = {0,};
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ULONG Ke386L1CacheSize;
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ULONG Ke386L2CacheSize;
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BOOLEAN Ke386NoExecute = FALSE;
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BOOLEAN Ke386Pae = FALSE;
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BOOLEAN Ke386PaeEnabled = FALSE;
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BOOLEAN Ke386GlobalPagesEnabled = FALSE;
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/* FUNCTIONS *****************************************************************/
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@ -53,39 +51,43 @@ Ki386GetCpuId(VOID)
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{
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ULONG OrigFlags, Flags, FinalFlags;
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ULONG MaxCpuidLevel;
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ULONG Dummy, Ebx, Ecx, Edx;
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ULONG Dummy, Eax, Ebx, Ecx, Edx;
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PKPCR Pcr = KeGetCurrentKPCR();
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Ke386CpuidFlags = Ke386CpuidFlags2 = Ke386CpuidExFlags = 0;
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Ke386CpuidFlags2 = Ke386CpuidExFlags = 0;
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Ke386CacheAlignment = 32;
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/* Try to toggle the id bit in eflags. */
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__asm__ ("pushfl\n\t"
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"popl %0\n\t"
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: "=r" (OrigFlags));
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Ke386SaveFlags(OrigFlags);
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Flags = OrigFlags ^ X86_EFLAGS_ID;
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__asm__ ("pushl %1\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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: "=r" (FinalFlags)
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: "r" (Flags));
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Ke386RestoreFlags(Flags);
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Ke386SaveFlags(FinalFlags);
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if ((OrigFlags & X86_EFLAGS_ID) == (FinalFlags & X86_EFLAGS_ID))
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{
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/* No cpuid supported. */
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Pcr->PrcbData.CpuID = FALSE;
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Pcr->PrcbData.CpuType = 3;
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return;
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}
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Pcr->PrcbData.CpuID = TRUE;
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/* Get the vendor name and the maximum cpuid level supported. */
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Ki386Cpuid(0, &MaxCpuidLevel, (PULONG)&Ke386CpuidVendor[0], (PULONG)&Ke386CpuidVendor[8], (PULONG)&Ke386CpuidVendor[4]);
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Ki386Cpuid(0, &MaxCpuidLevel, (PULONG)&Pcr->PrcbData.VendorString[0], (PULONG)&Pcr->PrcbData.VendorString[8], (PULONG)&Pcr->PrcbData.VendorString[4]);
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if (MaxCpuidLevel > 0)
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{
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/* Get the feature flags. */
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Ki386Cpuid(1, &Ke386Cpuid, &Ebx, &Ke386CpuidFlags2, &Ke386CpuidFlags);
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Ki386Cpuid(1, &Eax, &Ebx, &Ke386CpuidFlags2, &Pcr->PrcbData.FeatureBits);
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/* Get the cache alignment, if it is available */
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if (Ke386CpuidFlags & (1<<19))
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if (Pcr->PrcbData.FeatureBits & (1<<19))
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{
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Ke386CacheAlignment = ((Ebx >> 8) & 0xff) * 8;
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}
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Pcr->PrcbData.CpuType = (Eax >> 8) & 0xf;
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Pcr->PrcbData.CpuStep = (Eax & 0xf) | ((Eax << 4) & 0xf00);
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}
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else
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{
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Pcr->PrcbData.CpuType = 4;
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}
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/* Get the maximum extended cpuid level supported. */
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@ -99,7 +101,7 @@ Ki386GetCpuId(VOID)
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/* Get the model name. */
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if (MaxCpuidLevel >= 0x80000004)
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{
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PULONG v = (PULONG)&Ke386CpuidModel;
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PULONG v = (PULONG)Ke386CpuidModel;
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Ki386Cpuid(0x80000002, v, v + 1, v + 2, v + 3);
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Ki386Cpuid(0x80000003, v + 4, v + 5, v + 6, v + 7);
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Ki386Cpuid(0x80000004, v + 8, v + 9, v + 10, v + 11);
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@ -120,7 +122,7 @@ Ki386GetCpuId(VOID)
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if (MaxCpuidLevel >= 0x80000006)
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{
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Ki386Cpuid(0x80000006, &Dummy, &Dummy, &Ecx, &Dummy);
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Ke386L2CacheSize = Ecx >> 16;
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Pcr->L2CacheSize = Ecx >> 16;
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}
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}
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@ -164,14 +166,14 @@ KeApplicationProcessorInit(VOID)
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DPRINT("KeApplicationProcessorInit()\n");
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if (Ke386CpuidFlags & X86_FEATURE_PGE)
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if (Ke386GlobalPagesEnabled)
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{
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/* Enable global pages */
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Ke386SetCr4(Ke386GetCr4() | X86_CR4_PGE);
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}
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/* Enable PAE mode */
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if (Ke386CpuidFlags & X86_FEATURE_PAE)
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if (Ke386PaeEnabled)
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{
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MiEnablePAE(NULL);
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}
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@ -186,6 +188,8 @@ KeApplicationProcessorInit(VOID)
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*/
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KiInitializeGdt(Pcr);
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/* Get processor information. */
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Ki386GetCpuId();
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/*
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* It is now safe to process interrupts
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@ -250,10 +254,11 @@ KeInit1(PCHAR CommandLine, PULONG LastKernelAddress)
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/* Get processor information. */
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Ki386GetCpuId();
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if (Ke386CpuidFlags & X86_FEATURE_PGE)
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if (KPCR->PrcbData.FeatureBits & X86_FEATURE_PGE)
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{
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ULONG Flags;
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/* Enable global pages */
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Ke386GlobalPagesEnabled = TRUE;
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Ke386SaveFlags(Flags);
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Ke386DisableInterrupts();
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Ke386SetCr4(Ke386GetCr4() | X86_CR4_PGE);
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@ -288,8 +293,8 @@ KeInit1(PCHAR CommandLine, PULONG LastKernelAddress)
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* FIXME:
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* Make the detection of the noexecute feature more portable.
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*/
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if(((Ke386Cpuid >> 8) & 0xf) == 0xf &&
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0 == strcmp("AuthenticAMD", Ke386CpuidVendor))
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if(KPCR->PrcbData.CpuType == 0xf &&
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0 == strcmp("AuthenticAMD", KPCR->PrcbData.VendorString))
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{
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if (NoExecute)
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{
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@ -311,7 +316,7 @@ KeInit1(PCHAR CommandLine, PULONG LastKernelAddress)
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/* Enable PAE mode */
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if ((Pae && (Ke386CpuidFlags & X86_FEATURE_PAE)) || NoExecute)
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if ((Pae && (KPCR->PrcbData.FeatureBits & X86_FEATURE_PAE)) || NoExecute)
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{
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MiEnablePAE((PVOID*)LastKernelAddress);
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Ke386PaeEnabled = TRUE;
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@ -321,11 +326,13 @@ KeInit1(PCHAR CommandLine, PULONG LastKernelAddress)
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VOID INIT_FUNCTION
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KeInit2(VOID)
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{
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PKPCR Pcr = KeGetCurrentKPCR();
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KeInitializeBugCheck();
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KeInitializeDispatcher();
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KeInitializeTimerImpl();
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if (Ke386CpuidFlags & X86_FEATURE_PAE)
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if (Pcr->PrcbData.FeatureBits & X86_FEATURE_PAE)
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{
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DPRINT1("CPU supports PAE mode\n");
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if (Ke386Pae)
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DPRINT1("CPU doesn't run in PAE mode\n");
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}
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}
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if (Ke386CpuidVendor[0])
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if (Pcr->PrcbData.VendorString[0])
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{
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DPRINT1("CPU Vendor: %s\n", Ke386CpuidVendor);
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DPRINT1("CPU Vendor: %s\n", Pcr->PrcbData.VendorString);
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}
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if (Ke386CpuidModel[0])
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{
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{
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DPRINT1("Ke386L1CacheSize: %dkB\n", Ke386L1CacheSize);
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}
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if (Ke386L2CacheSize)
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if (Pcr->L2CacheSize)
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{
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DPRINT1("Ke386L2CacheSize: %dkB\n", Ke386L2CacheSize);
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DPRINT1("Ke386L2CacheSize: %dkB\n", Pcr->L2CacheSize);
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}
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}
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VOID INIT_FUNCTION
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Ki386SetProcessorFeatures(VOID)
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{
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PKPCR Pcr = KeGetCurrentKPCR();
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SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_PRECISION_ERRATA] = FALSE;
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SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_EMULATED] = FALSE;
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SharedUserData->ProcessorFeatures[PF_COMPARE_EXCHANGE_DOUBLE] =
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(Ke386CpuidFlags & X86_FEATURE_CX8);
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(Pcr->PrcbData.FeatureBits & X86_FEATURE_CX8);
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SharedUserData->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] =
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(Ke386CpuidFlags & X86_FEATURE_MMX);
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(Pcr->PrcbData.FeatureBits & X86_FEATURE_MMX);
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SharedUserData->ProcessorFeatures[PF_PPC_MOVEMEM_64BIT_OK] = FALSE;
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SharedUserData->ProcessorFeatures[PF_ALPHA_BYTE_INSTRUCTIONS] = FALSE;
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SharedUserData->ProcessorFeatures[PF_XMMI_INSTRUCTIONS_AVAILABLE] =
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(Ke386CpuidFlags & X86_FEATURE_SSE);
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(Pcr->PrcbData.FeatureBits & X86_FEATURE_SSE);
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SharedUserData->ProcessorFeatures[PF_3DNOW_INSTRUCTIONS_AVAILABLE] =
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(Ke386CpuidExFlags & X86_EXT_FEATURE_3DNOW);
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SharedUserData->ProcessorFeatures[PF_RDTSC_INSTRUCTION_AVAILABLE] =
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(Ke386CpuidFlags & X86_FEATURE_TSC);
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(Pcr->PrcbData.FeatureBits & X86_FEATURE_TSC);
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SharedUserData->ProcessorFeatures[PF_PAE_ENABLED] = Ke386PaeEnabled;
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SharedUserData->ProcessorFeatures[PF_XMMI64_INSTRUCTIONS_AVAILABLE] =
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(Ke386CpuidFlags & X86_FEATURE_SSE2);
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(Pcr->PrcbData.FeatureBits & X86_FEATURE_SSE2);
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}
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@ -10,7 +10,7 @@
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.globl _KeFlushCurrentTb@0
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_KeFlushCurrentTb@0:
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/* Check for global page support */
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testl $X86_FEATURE_PGE, (_Ke386CpuidFlags)
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testb $0xff, (_Ke386GlobalPagesEnabled)
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jz .L1
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/* Modifying the PSE, PGE or PAE Flag in CR4 causes the TLB to be flushed */
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@ -16,7 +16,7 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/* $Id: page.c,v 1.76 2004/11/11 22:23:52 ion Exp $
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/* $Id: page.c,v 1.77 2004/11/13 23:08:35 hbirr Exp $
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*
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* PROJECT: ReactOS kernel
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* FILE: ntoskrnl/mm/i386/page.c
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@ -77,10 +77,9 @@ __inline LARGE_INTEGER PTE_TO_PAGE(ULONG npage)
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}
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#endif
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extern ULONG Ke386CpuidFlags;
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extern ULONG Ke386Cpuid;
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extern BOOLEAN Ke386Pae;
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extern BOOLEAN Ke386NoExecute;
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extern BOOLEAN Ke386GlobalPagesEnabled;
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/* FUNCTIONS ***************************************************************/
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KEBUGCHECK(0);
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}
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Entry = PAE_PFN_TO_PTE(Pfn) | PA_PRESENT | PA_READWRITE;
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if (Ke386CpuidFlags & X86_FEATURE_PGE)
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if (Ke386GlobalPagesEnabled)
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{
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Entry |= PA_GLOBAL;
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}
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KEBUGCHECK(0);
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}
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Entry = PFN_TO_PTE(Pfn) | PA_PRESENT | PA_READWRITE;
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if (Ke386CpuidFlags & X86_FEATURE_PGE)
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if (Ke386GlobalPagesEnabled)
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{
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Entry |= PA_GLOBAL;
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}
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NoExecute = TRUE;
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}
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Attributes &= 0xfff;
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if (Ke386CpuidFlags & X86_FEATURE_PGE)
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if (Ke386GlobalPagesEnabled)
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{
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Attributes |= PA_GLOBAL;
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}
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if (Address >= (PVOID)KERNEL_BASE)
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{
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Attributes &= ~PA_USER;
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if (Ke386CpuidFlags & X86_FEATURE_PGE)
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if (Ke386GlobalPagesEnabled)
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{
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Attributes |= PA_GLOBAL;
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}
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if (Address >= (PVOID)KERNEL_BASE)
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{
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Attributes &= ~PA_USER;
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if (Ke386CpuidFlags & X86_FEATURE_PGE)
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if (Ke386GlobalPagesEnabled)
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{
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Attributes |= PA_GLOBAL;
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}
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0LL == MmGlobalKernelPageDirectoryForPAE[i] && 0LL != CurrentPageDirectory[i])
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{
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ExfpInterlockedExchange64(&MmGlobalKernelPageDirectoryForPAE[i], &CurrentPageDirectory[i]);
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if (Ke386CpuidFlags & X86_FEATURE_PGE)
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if (Ke386GlobalPagesEnabled)
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{
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MmGlobalKernelPageDirectoryForPAE[i] |= PA_GLOBAL;
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}
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0 == MmGlobalKernelPageDirectory[i] && 0 != CurrentPageDirectory[i])
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{
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MmGlobalKernelPageDirectory[i] = CurrentPageDirectory[i];
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if (Ke386CpuidFlags & X86_FEATURE_PGE)
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if (Ke386GlobalPagesEnabled)
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{
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MmGlobalKernelPageDirectory[i] |= PA_GLOBAL;
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}
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