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[BOOTVID] Add boot video driver for NEC PC-98 series (#2787)

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Dmitry Borisov 2020-05-14 16:36:55 +06:00 • committed by Stanislav Motylkov
parent 2bd6bfdd90
commit e901489574
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6 changed files with 767 additions and 63 deletions
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273
sdk/include/reactos/drivers/pc98/video.h
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@ -9,16 +9,19 @@
/* Video memory ***************************************************************/
#define VRAM_NORMAL_PLANE_B 0xA8000
#define VRAM_NORMAL_PLANE_G 0xB0000
#define VRAM_NORMAL_PLANE_R 0xB8000
#define VRAM_NORMAL_PLANE_I 0xE0000
#define VRAM_NORMAL_PLANE_B 0xA8000 /* Blue */
#define VRAM_NORMAL_PLANE_G 0xB0000 /* Green */
#define VRAM_NORMAL_PLANE_R 0xB8000 /* Red */
#define VRAM_NORMAL_PLANE_I 0xE0000 /* Intensity */
#define VRAM_PLANE_SIZE 0x08000
#define VRAM_NORMAL_TEXT 0xA0000
#define VRAM_TEXT_ATTR_OFFSET 0x02000
#define VRAM_TEXT_SIZE 0x02000
#define VRAM_ATTR_SIZE 0x02000
#define PEGC_FRAMEBUFFER_PACKED 0xF00000
#define PEGC_FRAMEBUFFER_SIZE 0x080000
/* High-resolution machine */
#define VRAM_HI_RESO_PLANE_B 0xC0000
#define VRAM_HI_RESO_PLANE_G 0xC8000
@ -52,14 +55,118 @@
#define GDC_ATTR_YELLOW 0xC0
#define GDC_ATTR_WHITE 0xE0
#define GDC_COMMAND_RESET 0x00
/* Operation type */
#define GDC_MOD_REPLACE 0x00
#define GDC_MOD_COMPLEMENT 0x01 /* XOR */
#define GDC_MOD_CLEAR 0x02 /* AND */
#define GDC_MOD_SET 0x03 /* OR */
#define GDC_GRAPHICS_DRAWING 0x40
#define GDC_COMMAND_RESET1 0x00
#define GDC_COMMAND_RESET2 0x01
#define GDC_COMMAND_STOP2 0x05
#define GDC_COMMAND_RESET3 0x09
#define GDC_COMMAND_BCTRL_STOP 0x0C
#define GDC_COMMAND_BCTRL_START 0x0D
#define GDC_COMMAND_SYNC_ON 0x0E
typedef struct _SYNCPARAM
{
UCHAR Flags;
#define SYNC_DISPLAY_MODE_GRAPHICS_AND_CHARACTERS 0x00
#define SYNC_DISPLAY_MODE_GRAPHICS 0x02
#define SYNC_DISPLAY_MODE_CHARACTERS 0x20
#define SYNC_VIDEO_FRAMING_NONINTERLACED 0x00
#define SYNC_VIDEO_FRAMING_INTERLACED_REPEAT_FOR_CHARACTERS 0x08
#define SYNC_VIDEO_FRAMING_INTERLACED 0x09
#define SYNC_DRAW_DURING_ACTIVE_DISPLAY_TIME_AND_RETRACE_BLANKING 0x00
#define SYNC_DRAW_ONLY_DURING_RETRACE_BLANKING 0x10
#define SYNC_STATIC_RAM_NO_REFRESH 0x00
#define SYNC_DYNAMIC_RAM_REFRESH 0x04
UCHAR ScreenWidthChars;
UCHAR HorizontalSyncWidth;
UCHAR VerticalSyncWidth;
UCHAR HorizontalFrontPorchWidth;
UCHAR HorizontalBackPorchWidth;
UCHAR VerticalFrontPorchWidth;
USHORT ScreenWidthLines;
UCHAR VerticalBackPorchWidth;
} SYNCPARAM, *PSYNCPARAM;
FORCEINLINE
VOID
WRITE_GDC_SYNC(PUCHAR Port, PSYNCPARAM SyncParameters)
{
WRITE_PORT_UCHAR(Port, SyncParameters->Flags & 0x3F);
WRITE_PORT_UCHAR(Port, SyncParameters->ScreenWidthChars - 2);
WRITE_PORT_UCHAR(Port, (SyncParameters->VerticalSyncWidth & 0x07) << 5 |
(SyncParameters->HorizontalSyncWidth - 1));
WRITE_PORT_UCHAR(Port, ((SyncParameters->HorizontalFrontPorchWidth - 1) << 2) |
((SyncParameters->VerticalSyncWidth & 0x18) >> 3));
WRITE_PORT_UCHAR(Port, SyncParameters->HorizontalBackPorchWidth - 1);
WRITE_PORT_UCHAR(Port, SyncParameters->VerticalFrontPorchWidth);
WRITE_PORT_UCHAR(Port, SyncParameters->ScreenWidthLines & 0xFF);
WRITE_PORT_UCHAR(Port, (SyncParameters->VerticalBackPorchWidth << 2) |
((SyncParameters->ScreenWidthLines & 0x300) >> 8));
}
#define GDC_COMMAND_SYNC_OFF 0x0F
#define GDC_COMMAND_WRITE 0x20
#define GDC_COMMAND_SLAVE 0x6E
#define GDC_COMMAND_MASTER 0x6F
#define GDC_COMMAND_DMAW 0x24
#define GDC_COMMAND_ZOOM 0x46
typedef struct _ZOOMPARAM
{
UCHAR DisplayZoomFactor;
UCHAR WritingZoomFactor;
} ZOOMPARAM, *PZOOMPARAM;
FORCEINLINE
VOID
WRITE_GDC_ZOOM(PUCHAR Port, PZOOMPARAM ZoomParameters)
{
WRITE_PORT_UCHAR(Port, ZoomParameters->DisplayZoomFactor << 4 | ZoomParameters->WritingZoomFactor);
}
#define GDC_COMMAND_PITCH 0x47
typedef struct _PITCHPARAM
{
ULONG WordsPerScanline;
} PITCHPARAM, *PPITCHPARAM;
FORCEINLINE
VOID
WRITE_GDC_PITCH(PUCHAR Port, PPITCHPARAM PitchParameters)
{
WRITE_PORT_UCHAR(Port, PitchParameters->WordsPerScanline);
}
#define GDC_COMMAND_CSRW 0x49
typedef struct _CSRWPARAM
{
ULONG CursorAddress;
UCHAR DotAddress;
} CSRWPARAM, *PCSRWPARAM;
FORCEINLINE
VOID
WRITE_GDC_CSRW(PUCHAR Port, PCSRWPARAM CursorParameters)
{
ASSERT(CursorParameters->CursorAddress < 0xF00000);
ASSERT(CursorParameters->DotAddress < 0x10);
WRITE_PORT_UCHAR(Port, CursorParameters->CursorAddress & 0xFF);
WRITE_PORT_UCHAR(Port, (CursorParameters->CursorAddress >> 8) & 0xFF);
WRITE_PORT_UCHAR(Port, (CursorParameters->DotAddress << 4) |
((CursorParameters->CursorAddress >> 16) & 0x03));
}
#define GDC_COMMAND_MASK 0x4A
#define GDC_COMMAND_CSRFORM 0x4B
typedef struct _CSRFORMPARAM
@ -83,40 +190,38 @@ WRITE_GDC_CSRFORM(PUCHAR Port, PCSRFORMPARAM CursorParameters)
WRITE_PORT_UCHAR(Port, (CursorParameters->EndScanLine << 3) | ((CursorParameters->BlinkRate & 0x1C) >> 2));
}
#define GDC_COMMAND_FIGS 0x4C
#define GDC_COMMAND_GCHRD 0x68
#define GDC_COMMAND_START 0x6B
#define GDC_COMMAND_ZOOM 0x46
#define GDC_COMMAND_FIGD 0x6C
#define GDC_COMMAND_SLAVE 0x6E
#define GDC_COMMAND_MASTER 0x6F
#define GDC_COMMAND_CSRW 0x49
typedef struct _CSRWPARAM
#define GDC_COMMAND_PRAM 0x70
typedef struct _PRAMPARAM
{
ULONG CursorAddress;
UCHAR DotAddress;
} CSRWPARAM, *PCSRWPARAM;
ULONG StartingAddress;
USHORT Length;
BOOLEAN ImageBit;
BOOLEAN WideDisplay;
} PRAMPARAM, *PPRAMPARAM;
FORCEINLINE
VOID
WRITE_GDC_CSRW(PUCHAR Port, PCSRWPARAM CursorParameters)
WRITE_GDC_PRAM(PUCHAR Port, PPRAMPARAM RamParameters)
{
ASSERT(CursorParameters->CursorAddress < 0xF00000);
ASSERT(CursorParameters->DotAddress < 0x10);
WRITE_PORT_UCHAR(Port, CursorParameters->CursorAddress & 0xFF);
WRITE_PORT_UCHAR(Port, (CursorParameters->CursorAddress >> 8) & 0xFF);
WRITE_PORT_UCHAR(Port, (CursorParameters->DotAddress << 4) |
((CursorParameters->CursorAddress >> 16) & 0x03));
WRITE_PORT_UCHAR(Port, RamParameters->StartingAddress & 0xFF);
WRITE_PORT_UCHAR(Port, (RamParameters->StartingAddress >> 8) & 0xFF);
WRITE_PORT_UCHAR(Port, ((RamParameters->Length & 0x0F) << 4) | ((RamParameters->StartingAddress >> 16) & 0x03));
WRITE_PORT_UCHAR(Port, ((RamParameters->WideDisplay & 0x01) << 7) | ((RamParameters->ImageBit & 0x01) << 6) |
((RamParameters->Length >> 4) & 0x3F));
}
#define GDC_COMMAND_PRAM 0x70
#define GDC_COMMAND_PITCH 0x47
#define GDC_COMMAND_MASK 0x4A
#define GDC_COMMAND_FIGS 0x4C
#define GDC_COMMAND_FIGD 0x6C
#define GDC_COMMAND_GCHRD 0x68
#define GDC_COMMAND_TEXTW 0x78
#define GDC_COMMAND_READ 0xA0
#define GDC_COMMAND_CURD 0xE0
#define GDC_COMMAND_LPRD 0xC0
#define GDC_COMMAND_DMAR 0xA4
#define GDC_COMMAND_DMAW 0x24
#define GDC_COMMAND_LPRD 0xC0
#define GDC_COMMAND_CURD 0xE0
/* Master GDC *****************************************************************/
@ -131,20 +236,20 @@ WRITE_GDC_CSRW(PUCHAR Port, PCSRWPARAM CursorParameters)
#define GDC1_IO_o_MODE_FLIPFLOP1 0x68
#define GDC1_MODE_VERTICAL_LINE 0x00 /* Character attribute */
#define GDC1_MODE_SIMPLE_GRAPHICS 0x01
#define GDC1_MODE_COLORED 0x02
#define GDC1_MODE_MONOCHROME 0x03
#define GRAPH_MODE_COLORED 0x02
#define GRAPH_MODE_MONOCHROME 0x03
#define GDC1_MODE_COLS_80 0x04
#define GDC1_MODE_COLS_40 0x05
#define GDC1_MODE_ANK_6_8 0x06
#define GDC1_MODE_ANK_7_13 0x07
#define GDC1_MODE_LINES_400 0x08
#define GDC1_MODE_LINES_200 0x09 /* Hide odd raster line */
#define GDC2_MODE_ODD_RLINE_SHOW 0x08
#define GDC2_MODE_ODD_RLINE_HIDE 0x09
#define GDC1_MODE_KCG_CODE 0x0A /* CG access during V-SYNC */
#define GDC1_MODE_KCG_BITMAP 0x0B
#define GDC1_NVMW_PROTECT 0x0C
#define GDC1_NVMW_UNPROTECT 0x0D /* Memory at TextVramSegment:(3FE2-3FFEh) */
#define GDC1_MODE_DISPLAY_DISABLE 0x0E
#define GDC1_MODE_DISPLAY_ENABLE 0x0F
#define GDC1_NVRAM_PROTECT 0x0C
#define GDC1_NVRAM_UNPROTECT 0x0D /* Memory at TextVramSegment:(3FE2-3FFEh) */
#define GRAPH_MODE_DISPLAY_DISABLE 0x0E
#define GRAPH_MODE_DISPLAY_ENABLE 0x0F
#define GDC1_IO_o_BORDER_COLOR 0x6C /* PC-H98 */
@ -177,7 +282,7 @@ WRITE_GDC_CSRW(PUCHAR Port, PCSRWPARAM CursorParameters)
#define GDC2_MODE_EGC 0x05
#define GDC2_EGC_FF_PROTECT 0x06
#define GDC2_EGC_FF_UNPROTECT 0x07 /* Unprotect the EGC F/F registers */
#define GDC2_MODE_PEGS_DISABLE 0x20
#define GDC2_MODE_PEGC_DISABLE 0x20
#define GDC2_MODE_PEGC_ENABLE 0x21
// #define GDC2_MODE_ 0x26
// #define GDC2_MODE_ 0x27
@ -189,7 +294,7 @@ WRITE_GDC_CSRW(PUCHAR Port, PCSRWPARAM CursorParameters)
// #define GDC2_MODE_ 0x2D
#define GDC2_MODE_CRT 0x40
#define GDC2_MODE_LCD 0x41
// #define GDC2_MODE_VRAM_PLAIN 0x62 /* PC-H98 */
// #define GDC2_MODE_VRAM_PLANAR 0x62 /* PC-H98 */
// #define GDC2_MODE_VRAM_PACKED 0x63
#define GDC2_MODE_LINES_400 0x68 /* 128 kB VRAM boundary */
#define GDC2_MODE_LINES_800 0x69 /* 256 kB VRAM boundary */
@ -234,6 +339,36 @@ WRITE_GDC2_COMMAND(UCHAR Command)
WRITE_PORT_UCHAR((PUCHAR)GDC2_IO_o_COMMAND, Command);
}
/* Miscellaneous **************************************************************/
#define GRAPH_IO_i_STATUS 0x9A0
#define GRAPH_STATUS_SET 0x01
#define GRAPH_GDC_CLOCK2_5MHZ 0x02
#define GRAPH_IO_o_STATUS_SELECT 0x9A0
#define GRAPH_STATUS_GDC_CLOCK1_5MHZ 0x09
#define GRAPH_STATUS_PEGC 0x0A
#define GRAPH_IO_i_DPMS 0x9A2
#define GRAPH_IO_o_DPMS 0x9A2
#define GRAPH_IO_i_HORIZONTAL_SCAN_RATE 0x9A8
#define GRAPH_IO_o_HORIZONTAL_SCAN_RATE 0x9A8
#define GRAPH_HF_24KHZ 0x00
#define GRAPH_HF_31KHZ 0x01
#define GRAPH_IO_i_RELAY 0xFAC
#define GRAPH_RELAY_0 0x01
#define GRAPH_RELAY_1 0x02
#define GRAPH_IO_o_RELAY 0xFAC
/* Relay 0 */
#define GRAPH_VID_SRC_INTERNAL 0x00
#define GRAPH_VID_SRC_EXTERNAL 0x01
/* Relay 1 */
#define GRAPH_SRC_GDC 0x00
#define GRAPH_SRC_WAB 0x02
/* CRT Controller *************************************************************/
#define CRTC_IO_o_SCANLINE_START 0x70
@ -247,25 +382,11 @@ WRITE_GDC2_COMMAND(UCHAR Command)
#define GRCG_IO_i_MODE 0x7C
#define GRCG_IO_o_MODE 0x7C
typedef union _GRCG_MODE_REGISTER
{
struct
{
UCHAR DisablePlaneB:1;
UCHAR DisablePlaneR:1;
UCHAR DisablePlaneG:1;
UCHAR DisablePlaneI:1;
UCHAR Unused:2;
UCHAR Mode:1;
#define GRCG_MODE_TILE_DIRECT_WRITE 0
#define GRCG_MODE_TILE_COMPARE_READ 0
#define GRCG_MODE_READ_MODIFY_WRITE 1
UCHAR Enable:1;
};
UCHAR Bits;
} GRCG_MODE_REGISTER, *PGRCG_MODE_REGISTER;
#define GRCG_DISABLE 0x00
#define GRCG_ENABLE 0x80
#define GRCG_MODE_TILE_DIRECT_WRITE 0x80
#define GRCG_MODE_TILE_COMPARE_READ 0x80
#define GRCG_MODE_READ_MODIFY_WRITE 0xC0
#define GRCG_IO_o_TILE_PATTERN 0x7E
@ -277,3 +398,37 @@ typedef union _GRCG_MODE_REGISTER
#define KCG_IO_o_PATTERN 0xA9
#define KCG_IO_i_PATTERN 0xA9
/* EGC blitter ****************************************************************/
#define EGC_IO_o_PLANE_ACCESS 0x4A0
#define EGC_IO_o_PATTERN_DATA_PLANE_READ 0x4A2
#define EGC_IO_o_READ_WRITE_MODE 0x4A4
#define EGC_IO_o_FG_COLOR 0x4A6
#define EGC_IO_o_MASK 0x4A8
#define EGC_IO_o_BG_COLOR 0x4AA
#define EGC_IO_o_BIT_ADDRESS 0x4AC
#define EGC_IO_o_BIT_LENGTH 0x4AE
#define PEGC_MMIO_BANK_0 0x004
#define PEGC_MMIO_BANK_1 0x006
#define PEGC_MMIO_MODE 0x100
#define PEGC_MODE_PACKED 0x00
#define PEGC_MODE_PLANAR 0x01
#define PEGC_MMIO_FRAMEBUFFER 0x102
#define PEGC_FB_UNMAP 0x00
#define PEGC_FB_MAP 0x01
#define PEGC_FB_UNKNOWN1 0x02
#define PEGC_FB_UNKNOWN2 0x03
#define PEGC_MMIO_PLANE_ACCESS 0x104
#define PEGC_MMIO_ROP 0x108
#define PEGC_MMIO_DATA_SELECT 0x10A
#define PEGC_MMIO_MASK 0x10C
#define PEGC_MMIO_BIT_LENGTH 0x110
#define PEGC_MMIO_BIT_ADDRESS 0x112
#define PEGC_MMIO_FG_COLOR 0x114
#define PEGC_MMIO_BG_COLOR 0x118
#define PEGC_MMIO_ROP_PATTERN 0x120