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[INTRIN]
- Implement _mm_sfence, _mm_lfence, __faststorefence (for amd64) - Don't use __sync_synchronize() for _ReadWriteBarrier, as it issues an mfence instruction and this is not what we want - Remove "BUGBUG" comment, because the fact that _ReadBarrier and _WriteBarrier are full (compiler) barriers isn't critical. svn path=/trunk/; revision=50456
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@ -79,22 +79,37 @@ extern "C" {
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#define _alloca(s) __builtin_alloca(s)
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#endif
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/*** Atomic operations ***/
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/*** Memory barriers ***/
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#if (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) > 40100
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#define _ReadWriteBarrier() __sync_synchronize()
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#else
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__INTRIN_INLINE void _MemoryBarrier(void)
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#ifdef _x86_64
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__INTRIN_INLINE void __faststorefence(void)
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{
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long local;
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__asm__ __volatile__("lock; orl $0, %0;" : : "m"(local));
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}
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#endif
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__INTRIN_INLINE void _mm_lfence(void)
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{
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__asm__ __volatile__("lfence");
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}
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__INTRIN_INLINE void _mm_sfence(void)
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{
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__asm__ __volatile__("sfence");
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}
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__INTRIN_INLINE void _ReadWriteBarrier(void)
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{
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__asm__ __volatile__("" : : : "memory");
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}
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#define _ReadWriteBarrier() _MemoryBarrier()
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#endif
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/* BUGBUG: GCC only supports full barriers */
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/* GCC only supports full barriers */
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#define _ReadBarrier _ReadWriteBarrier
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#define _WriteBarrier _ReadWriteBarrier
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/*** Atomic operations ***/
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#if (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) > 40100
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__INTRIN_INLINE char _InterlockedCompareExchange8(volatile char * const Destination, const char Exchange, const char Comperand)
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