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[REACTOS] Fix build with VS 17.14.2 / CL 19.44.35207.1

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This commit is contained in:
Timo Kreuzer 2025-05-28 21:56:38 +03:00
parent d663eb4466
commit e431470ff9
13 changed files with 43 additions and 14 deletions
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8
sdk/lib/fast486/extraops.c
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@ -622,7 +622,7 @@ FAST486_OPCODE_HANDLER(Fast486ExtOpcodeLoadControlReg)
/* Get the value */
Value = State->GeneralRegs[ModRegRm.SecondRegister].Long;
if (ModRegRm.Register == (INT)FAST486_REG_CR0)
if (ModRegRm.Register == (FAST486_GEN_REGS)FAST486_REG_CR0)
{
/* CR0 checks */
@ -640,7 +640,7 @@ FAST486_OPCODE_HANDLER(Fast486ExtOpcodeLoadControlReg)
State->PrefetchValid = FALSE;
#endif
if (ModRegRm.Register == (INT)FAST486_REG_CR3)
if (ModRegRm.Register == (FAST486_GEN_REGS)FAST486_REG_CR3)
{
/* Flush the TLB */
Fast486FlushTlb(State);
@ -688,12 +688,12 @@ FAST486_OPCODE_HANDLER(Fast486ExtOpcodeLoadDebugReg)
/* Load a value to the debug register */
State->DebugRegisters[ModRegRm.Register] = State->GeneralRegs[ModRegRm.SecondRegister].Long;
if (ModRegRm.Register == (INT)FAST486_REG_DR4)
if (ModRegRm.Register == (FAST486_GEN_REGS)FAST486_REG_DR4)
{
/* The reserved bits are 1 */
State->DebugRegisters[ModRegRm.Register] |= FAST486_DR4_RESERVED;
}
else if (ModRegRm.Register == (INT)FAST486_REG_DR5)
else if (ModRegRm.Register == (FAST486_GEN_REGS)FAST486_REG_DR5)
{
/* The reserved bits are 0 */
State->DebugRegisters[ModRegRm.Register] &= ~FAST486_DR5_RESERVED;