mirror of
https://github.com/reactos/reactos.git
synced 2024-08-08 12:18:13 +00:00
Fixed some bugs in KeFillFixedEntryTb -- we actually needed to map the PTE into memory (then we can umap it).
We were doing the initial PCR/PDR page allocation completely wrong since we're using 1MB section pages, not 4KB pages (this needs to be fixed later). Piggyhack arm_kprintf on top of DebugService which we now define. DPRINT1 and ASSERT now work! Send ARC paths and normalized command-line in the loader parameter block. Current state: FreeLoader v3.0 for ARM Bootargs: rdbase=0x2000000 rdsize=0x1400000 Detecting Hardware... Loading... Reading NTOSKRNL.EXE Reading BOOTVID.DLL Reading HAL.DLL Reading HAL.DLL Reading c_1252.nls Reading c_437.nls Reading l_intl.nls Reading scsiport.sys Reading atapi.sys Reading buslogic.sys Reading pci.sys Reading class2.sys Reading disk.sys Reading vfatfs.sys Reading ndis.sys Mapped serial port to 0xc00f1000 (ntoskrnl/ke/arm/kiinit.c:135) ----------------------------------------------------- (ntoskrnl/ke/arm/kiinit.c:136) ReactOS 0.4-SVN (Build 20080207-r32151) (ntoskrnl/ke/arm/kiinit.c:137) Command Line: DEBUG DEBUGPORT=COM1 BAUDRATE=115200 SOS (ntoskrnl/ke/arm/kiinit.c:138) ARC Paths: ramdisk(0) \ ramdisk(0) \ReactOS\ svn path=/trunk/; revision=32328
This commit is contained in:
parent
b8a06afb8c
commit
e28048569a
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@ -17,6 +17,11 @@
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ULONG PageDirectoryStart, PageDirectoryEnd;
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ULONG PageDirectoryStart, PageDirectoryEnd;
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LOADER_PARAMETER_BLOCK ArmLoaderBlock;
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LOADER_PARAMETER_BLOCK ArmLoaderBlock;
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CHAR ArmCommandLine[256];
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CHAR ArmArcBootPath[64];
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CHAR ArmArcHalPath[64];
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CHAR ArmNtHalPath[64];
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CHAR ArmNtBootPath[64];
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LOADER_PARAMETER_EXTENSION ArmExtension;
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LOADER_PARAMETER_EXTENSION ArmExtension;
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extern ARM_TRANSLATION_TABLE ArmTranslationTable;
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extern ARM_TRANSLATION_TABLE ArmTranslationTable;
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extern ROS_KERNEL_ENTRY_POINT KernelEntryPoint;
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extern ROS_KERNEL_ENTRY_POINT KernelEntryPoint;
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@ -143,7 +148,12 @@ ArmSetupPagingAndJump(IN ULONG Magic)
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ControlRegister.DCacheEnabled = TRUE;
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ControlRegister.DCacheEnabled = TRUE;
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KeArmControlRegisterSet(ControlRegister);
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KeArmControlRegisterSet(ControlRegister);
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ArmBoardBlock->UartRegisterBase = UART_VIRTUAL | (ArmBoardBlock->UartRegisterBase & ((1<<TTB_SHIFT)-1));
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//
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// Reconfigure UART0
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//
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ArmBoardBlock->UartRegisterBase = UART_VIRTUAL |
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(ArmBoardBlock->UartRegisterBase &
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((1 << TTB_SHIFT) - 1));
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TuiPrintf("Mapped serial port to 0x%x\n", ArmBoardBlock->UartRegisterBase);
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TuiPrintf("Mapped serial port to 0x%x\n", ArmBoardBlock->UartRegisterBase);
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//
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//
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@ -157,6 +167,7 @@ ArmPrepareForReactOS(IN BOOLEAN Setup)
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{
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{
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ARM_CACHE_REGISTER CacheReg;
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ARM_CACHE_REGISTER CacheReg;
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PVOID Base;
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PVOID Base;
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PCHAR BootPath, HalPath;
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//
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//
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// Initialize the loader block
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// Initialize the loader block
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@ -196,9 +207,47 @@ ArmPrepareForReactOS(IN BOOLEAN Setup)
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//
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//
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//
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//
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// Send the command line
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// Make a copy of the command line
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//
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//
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ArmLoaderBlock.LoadOptions = reactos_kernel_cmdline;
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ArmLoaderBlock.LoadOptions = ArmCommandLine;
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strcpy(ArmCommandLine, reactos_kernel_cmdline);
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//
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// Find the first \, separating the ARC path from NT path
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//
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BootPath = strchr(ArmCommandLine, '\\');
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*BootPath = ANSI_NULL;
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//
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// Set the ARC Boot Path
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//
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strncpy(ArmArcBootPath, ArmCommandLine, 63);
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ArmLoaderBlock.ArcBootDeviceName = ArmArcBootPath;
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//
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// The rest of the string is the NT path
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//
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HalPath = strchr(BootPath + 1, ' ');
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*HalPath = ANSI_NULL;
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ArmNtBootPath[0] = '\\';
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strncat(ArmNtBootPath, BootPath + 1, 63);
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strcat(ArmNtBootPath,"\\");
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ArmLoaderBlock.NtBootPathName = ArmNtBootPath;
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//
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// Set the HAL paths
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//
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strncpy(ArmArcHalPath, ArmArcBootPath, 63);
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ArmLoaderBlock.ArcHalDeviceName = ArmArcHalPath;
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strcpy(ArmNtHalPath, "\\");
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ArmLoaderBlock.NtHalPathName = ArmNtHalPath;
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/* Use this new command line */
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strncpy(ArmLoaderBlock.LoadOptions, HalPath + 2, 255);
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/* Parse it and change every slash to a space */
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BootPath = ArmLoaderBlock.LoadOptions;
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do {if (*BootPath == '/') *BootPath = ' ';} while (*BootPath++);
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//
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//
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// Setup cache information
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// Setup cache information
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@ -234,16 +283,17 @@ ArmPrepareForReactOS(IN BOOLEAN Setup)
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ArmLoaderBlock.u.Arm.PanicStack = KSEG0_BASE | (ULONG)Base;
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ArmLoaderBlock.u.Arm.PanicStack = KSEG0_BASE | (ULONG)Base;
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//
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//
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// Allocate the PCRs (1MB each for now!)
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// Allocate the PCR page -- align it to 1MB (we only need 4KB)
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//
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//
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Base = MmAllocateMemoryWithType(2 * 1024 * 1024, LoaderStartupPcrPage);
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Base = MmAllocateMemoryWithType(2 * 1024 * 1024, LoaderStartupPcrPage);
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Base = (PVOID)ROUND_UP(Base, 1 * 1024 * 1024);
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ArmLoaderBlock.u.Arm.PcrPage = (ULONG)Base >> TTB_SHIFT;
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ArmLoaderBlock.u.Arm.PcrPage = (ULONG)Base >> TTB_SHIFT;
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ArmLoaderBlock.u.Arm.PcrPage2 = ArmLoaderBlock.u.Arm.PcrPage + 1;
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//
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//
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// Allocate PDR pages
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// Allocate PDR pages -- align them to 1MB (we only need 3xKB)
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//
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//
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Base = MmAllocateMemoryWithType(3 * 1024 * 1024, LoaderStartupPdrPage);
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Base = MmAllocateMemoryWithType(4 * 1024 * 1024, LoaderStartupPdrPage);
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Base = (PVOID)ROUND_UP(Base, 1 * 1024 * 1024);
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ArmLoaderBlock.u.Arm.PdrPage = (ULONG)Base >> TTB_SHIFT;
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ArmLoaderBlock.u.Arm.PdrPage = (ULONG)Base >> TTB_SHIFT;
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//
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//
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@ -274,6 +324,5 @@ FrLdrStartup(IN ULONG Magic)
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//
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//
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// Initialize paging and load NTOSKRNL
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// Initialize paging and load NTOSKRNL
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//
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//
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TuiPrintf("Kernel Command Line: %s\n", ArmLoaderBlock.LoadOptions);
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ArmSetupPagingAndJump(Magic);
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ArmSetupPagingAndJump(Magic);
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}
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}
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@ -46,7 +46,7 @@ typedef struct _KPCR
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{
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{
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ULONG MinorVersion;
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ULONG MinorVersion;
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ULONG MajorVersion;
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ULONG MajorVersion;
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PKINTERRUPT_ROUTINE InterruptRoutine[64];
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PKINTERRUPT_ROUTINE InterruptRoutine[16];
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PVOID XcodeDispatch;
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PVOID XcodeDispatch;
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ULONG FirstLevelDcacheSize;
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ULONG FirstLevelDcacheSize;
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ULONG FirstLevelDcacheFillSize;
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ULONG FirstLevelDcacheFillSize;
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@ -71,6 +71,7 @@ typedef struct _KPCR
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PVOID DataBusError;
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PVOID DataBusError;
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PVOID InstructionBusError;
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PVOID InstructionBusError;
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ULONG CachePolicy;
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ULONG CachePolicy;
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ULONG AlignedCachePolicy;
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UCHAR IrqlMask[64];
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UCHAR IrqlMask[64];
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UCHAR IrqlTable[64];
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UCHAR IrqlTable[64];
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UCHAR CurrentIrql;
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UCHAR CurrentIrql;
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@ -38,6 +38,14 @@ KeArmLockdownRegisterGet(VOID)
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return Value;
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return Value;
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}
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}
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FORCEINLINE
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ARM_TTB_REGISTER
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KeArmTranslationTableRegisterGet(VOID)
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{
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ARM_TTB_REGISTER Value;
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__asm__ __volatile__ ("mrc p15, 0, %0, c2, c0, 0" : "=r"(Value.AsUlong) : : "cc");
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return Value;
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}
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FORCEINLINE
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FORCEINLINE
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ARM_CACHE_REGISTER
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ARM_CACHE_REGISTER
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@ -9,8 +9,8 @@
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//
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//
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//Lockdown TLB entries
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//Lockdown TLB entries
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//
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//
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#define PCR_ENTRY, 0
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#define PCR_ENTRY 0
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#define PDR_ENTRY, 2
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#define PDR_ENTRY 2
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#define KeArchHaltProcessor() KeArmHaltProcessor()
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#define KeArchHaltProcessor() KeArmHaltProcessor()
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@ -12,8 +12,6 @@
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#define NDEBUG
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#define NDEBUG
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#include <debug.h>
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#include <debug.h>
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void arm_kprintf(const char *fmt, ...);
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/* GLOBALS ********************************************************************/
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/* GLOBALS ********************************************************************/
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BOOLEAN KeIsArmV6;
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BOOLEAN KeIsArmV6;
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@ -23,8 +21,26 @@ ULONG KeNumberTbEntries;
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#define __ARMV6__ KeIsArmV6
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#define __ARMV6__ KeIsArmV6
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//
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// METAFIXME: We need to stop using 1MB Section Entry TTEs!
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//
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/* FUNCTIONS ******************************************************************/
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/* FUNCTIONS ******************************************************************/
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VOID
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DebugService(IN ULONG ServiceType,
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IN PCHAR Buffer,
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IN ULONG Length,
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IN ULONG Component,
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IN ULONG Level)
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{
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//
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// ARM Bring-up Hack
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//
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void arm_kprintf(const char *fmt, ...);
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arm_kprintf("%s", Buffer);
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}
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VOID
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VOID
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KiFlushSingleTb(IN BOOLEAN Invalid,
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KiFlushSingleTb(IN BOOLEAN Invalid,
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IN PVOID Virtual)
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IN PVOID Virtual)
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@ -42,14 +58,19 @@ KeFillFixedEntryTb(IN ARM_PTE Pte,
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{
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{
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ARM_LOCKDOWN_REGISTER LockdownRegister;
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ARM_LOCKDOWN_REGISTER LockdownRegister;
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ULONG OldVictimCount;
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ULONG OldVictimCount;
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ULONG Temp;
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volatile unsigned long Temp;
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UNREFERENCED_PARAMETER(Pte);
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PARM_TRANSLATION_TABLE TranslationTable;
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UNREFERENCED_PARAMETER(Index);
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//
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// Hack for 1MB Section Entries
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//
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Virtual = (PVOID)((ULONG)Virtual & 0xFFF00000);
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//
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//
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// On ARM, we can't set the index ourselves, so make sure that we are not
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// On ARM, we can't set the index ourselves, so make sure that we are not
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// locking down more than 8 entries.
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// locking down more than 8 entries.
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//
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//
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UNREFERENCED_PARAMETER(Index);
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KeFixedTbEntries++;
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KeFixedTbEntries++;
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ASSERT(KeFixedTbEntries <= 8);
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ASSERT(KeFixedTbEntries <= 8);
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@ -66,6 +87,12 @@ KeFillFixedEntryTb(IN ARM_PTE Pte,
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OldVictimCount = LockdownRegister.Victim;
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OldVictimCount = LockdownRegister.Victim;
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KeArmLockdownRegisterSet(LockdownRegister);
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KeArmLockdownRegisterSet(LockdownRegister);
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//
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// Map the PTE for this virtual address
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//
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TranslationTable = (PVOID)KeArmTranslationTableRegisterGet().AsUlong;
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TranslationTable->Pte[(ULONG)Virtual >> TTB_SHIFT] = Pte;
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//
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//
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// Now force a miss
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// Now force a miss
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//
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//
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@ -78,6 +105,11 @@ KeFillFixedEntryTb(IN ARM_PTE Pte,
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LockdownRegister.Preserve = FALSE;
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LockdownRegister.Preserve = FALSE;
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ASSERT(LockdownRegister.Victim == OldVictimCount + 1);
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ASSERT(LockdownRegister.Victim == OldVictimCount + 1);
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KeArmLockdownRegisterSet(LockdownRegister);
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KeArmLockdownRegisterSet(LockdownRegister);
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//
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// Clear the PTE
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//
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TranslationTable->Pte[(ULONG)Virtual >> TTB_SHIFT].AsUlong = 0;
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}
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}
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VOID
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VOID
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@ -93,7 +125,16 @@ VOID
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KiInitializeSystem(IN ULONG Magic,
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KiInitializeSystem(IN ULONG Magic,
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IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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{
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{
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arm_kprintf("%s:%i\n", __func__, __LINE__);
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ARM_PTE Pte;
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PKPCR Pcr;
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DPRINT1("-----------------------------------------------------\n");
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DPRINT1("ReactOS-ARM "KERNEL_VERSION_STR" (Build "KERNEL_VERSION_BUILD_STR")\n");
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DPRINT1("Command Line: %s\n", LoaderBlock->LoadOptions);
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DPRINT1("ARC Paths: %s %s %s %s\n", LoaderBlock->ArcBootDeviceName,
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LoaderBlock->NtHalPathName,
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LoaderBlock->ArcHalDeviceName,
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LoaderBlock->NtBootPathName);
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//
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//
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// Detect ARM version (Architecture 6 is the ARMv5TE-J, go figure!)
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// Detect ARM version (Architecture 6 is the ARMv5TE-J, go figure!)
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//
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//
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KeFlushTb();
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KeFlushTb();
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//
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//
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// Build the KIPCR pte
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//
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//
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//
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Pte.L1.Section.Type = SectionPte;
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Pte.L1.Section.Buffered = FALSE;
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Pte.L1.Section.Cached = FALSE;
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Pte.L1.Section.Reserved = 1; // ARM926EJ-S manual recommends setting to 1
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Pte.L1.Section.Domain = Domain0;
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Pte.L1.Section.Access = SupervisorAccess;
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Pte.L1.Section.BaseAddress = LoaderBlock->u.Arm.PcrPage;
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Pte.L1.Section.Ignored = Pte.L1.Section.Ignored1 = 0;
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//
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// Map it into kernel address space by locking it into the TLB
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//
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KeFillFixedEntryTb(Pte, (PVOID)KIPCR, PCR_ENTRY);
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//
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// Now map the PCR into user address space as well (read-only)
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//
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Pte.L1.Section.Access = SharedAccess;
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KeFillFixedEntryTb(Pte, (PVOID)USPCR, PCR_ENTRY + 1);
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//
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// Now we should be able to use the PCR... set the cache policies
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//
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Pcr = (PKPCR)KeGetPcr();
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Pcr->CachePolicy = 0;
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Pcr->AlignedCachePolicy = 0;
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while (TRUE);
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while (TRUE);
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}
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}
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@ -146,7 +146,6 @@ GENERATE_ARM_STUB RtlInitializeContext
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GENERATE_ARM_STUB RtlpGetExceptionAddress
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GENERATE_ARM_STUB RtlpGetExceptionAddress
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GENERATE_ARM_STUB RtlDispatchException
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GENERATE_ARM_STUB RtlDispatchException
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GENERATE_ARM_STUB DebugService2
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GENERATE_ARM_STUB DebugService2
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GENERATE_ARM_STUB DebugService
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GENERATE_ARM_STUB KdPortPutByteEx
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GENERATE_ARM_STUB KdPortPutByteEx
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GENERATE_ARM_STUB KdPortInitializeEx
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GENERATE_ARM_STUB KdPortInitializeEx
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GENERATE_ARM_STUB KdpGdbStubInit
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GENERATE_ARM_STUB KdpGdbStubInit
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