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- Implement init and start of OHCI controller (interrupts are still disabled, because corresponding code is not implemented).
- Implement stubbed HCD interface functions for OHCI. - Add Endpoint Descriptor and Transfer Descriptor structs from Linux. svn path=/trunk/; revision=30607
This commit is contained in:
Aleksey Bragin
parent
0fdacaa71e
commit
de4fffafa1
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@ -87,6 +87,12 @@ static u32 roothub_portstatus (struct ohci_hcd *hc, int i)
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*/
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/* For initializing controller (mask in an HCFS mode too) */
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#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
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#define OHCI_INTR_INIT \
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(OHCI_INTR_MIE | OHCI_INTR_UE | OHCI_INTR_RD | OHCI_INTR_WDH)
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VOID
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ohci_wait_ms(POHCI_DEV ohci, LONG ms)
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{
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@ -161,6 +167,28 @@ PDEVICE_OBJECT ohci_probe(PDRIVER_OBJECT drvr_obj, PUNICODE_STRING reg_path,
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return NULL;
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}
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BOOLEAN ohci_mem_init (POHCI_DEVICE_EXTENSION dev_ext)
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{
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dev_ext->ohci->td_cache = HalAllocateCommonBuffer(dev_ext->padapter,
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sizeof(OHCI_TD), &dev_ext->ohci->td_logic_addr, FALSE);
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if (!dev_ext->ohci->td_cache)
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return FALSE;
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dev_ext->ohci->ed_cache = HalAllocateCommonBuffer(dev_ext->padapter,
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sizeof(OHCI_ED), &dev_ext->ohci->ed_logic_addr, FALSE);
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if (!dev_ext->ohci->ed_cache)
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{
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HalFreeCommonBuffer(dev_ext->padapter, sizeof(OHCI_TD), dev_ext->ohci->td_logic_addr,
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dev_ext->ohci->td_cache, FALSE);
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return FALSE;
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}
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return TRUE;
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}
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PDEVICE_OBJECT
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ohci_alloc(PDRIVER_OBJECT drvr_obj, PUNICODE_STRING reg_path, ULONG bus_addr, PUSB_DEV_MANAGER dev_mgr)
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{
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@ -201,7 +229,9 @@ ohci_alloc(PDRIVER_OBJECT drvr_obj, PUNICODE_STRING reg_path, ULONG bus_addr, PU
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dev_desc.Dma32BitAddresses = TRUE;
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dev_desc.BusNumber = bus;
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dev_desc.InterfaceType = PCIBus;
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//dev_desc.MaximumLength = EHCI_MAX_SIZE_TRANSFER;
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dev_desc.MaximumLength = EHCI_MAX_SIZE_TRANSFER;
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pdev_ext->map_regs = 2; // we do not use it seriously
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pdev_ext->padapter = HalGetAdapter(&dev_desc, &pdev_ext->map_regs);
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DbgPrint("ohci_alloc(): reg_path=0x%x, \n \
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ohci_alloc(): bus=0x%x, bus_addr=0x%x \n \
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@ -333,13 +363,20 @@ ohci_alloc(PDRIVER_OBJECT drvr_obj, PUNICODE_STRING reg_path, ULONG bus_addr, PU
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DbgPrint("OHCI: %d ports\n", pdev_ext->ohci->num_ports);
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//ohci->hcca = dma_alloc_coherent (ohci_to_hcd(ohci)->self.controller,
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// sizeof *ohci->hcca, &ohci->hcca_dma, 0);
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//if (!ohci->hcca)
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// return -ENOMEM;
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pdev_ext->ohci->hcca = HalAllocateCommonBuffer(pdev_ext->padapter,
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sizeof(*pdev_ext->ohci->hcca), &pdev_ext->ohci->hcca_logic_addr, FALSE);
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//if ((ret = ohci_mem_init (ohci)) < 0)
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// ohci_stop (ohci_to_hcd(ohci));
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if (!pdev_ext->ohci->hcca)
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{
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DbgPrint("OHCI: HCCA allocation failed!\n");
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return NULL;
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}
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if (!ohci_mem_init(pdev_ext))
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{
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DbgPrint("OHCI: Mem init failed!\n");
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return NULL;
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}
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#if 0
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//init ehci_caps
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@ -464,72 +501,137 @@ ohci_create_device(PDRIVER_OBJECT drvr_obj, PUSB_DEV_MANAGER dev_mgr)
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BOOLEAN
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ohci_start(PHCD hcd)
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{
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//ULONG tmp;
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ULONG temp, mask;
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//PBYTE base;
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//PEHCI_USBCMD_CONTENT usbcmd;
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//POHCI_DEV ohci;
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POHCI_DEV ohci;
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ULONG hc_control;
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if (hcd == NULL)
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return FALSE;
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return TRUE;
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ohci = struct_ptr(hcd, OHCI_DEV, hcd_interf);
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/* Reset USB nearly "by the book". RemoteWakeupConnected
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* saved if boot firmware (BIOS/SMM/...) told us it's connected
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* (for OHCI integrated on mainboard, it normally is)
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*/
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hc_control = OHCI_READ_PORT_ULONG((PULONG)&ohci->regs->control);
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DbgPrint("resetting from state %x, control = 0x%x\n",
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(hc_control & OHCI_CTRL_HCFS),
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hc_control);
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//if (hc_control & OHCI_CTRL_RWC
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// && !(ohci->flags & OHCI_QUIRK_AMD756))
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// ohci_to_hcd(ohci)->can_wakeup = 1;
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switch (hc_control & OHCI_CTRL_HCFS) {
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case OHCI_USB_OPER:
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temp = 0;
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break;
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case OHCI_USB_SUSPEND:
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case OHCI_USB_RESUME:
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hc_control &= OHCI_CTRL_RWC;
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hc_control |= OHCI_USB_RESUME;
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temp = 10 /* msec wait */;
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break;
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// case OHCI_USB_RESET:
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default:
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hc_control &= OHCI_CTRL_RWC;
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hc_control |= OHCI_USB_RESET;
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temp = 50 /* msec wait */;
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break;
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}
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OHCI_WRITE_PORT_ULONG((PULONG)&ohci->regs->control, hc_control);
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// flush the writes
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(VOID)OHCI_READ_PORT_ULONG((PULONG)&ohci->regs->control);
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ohci_wait_ms(ohci, temp);
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temp = roothub_a (ohci);
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if (!(temp & RH_A_NPS)) {
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/* power down each port */
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for (temp = 0; temp < ohci->num_ports; temp++)
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{
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OHCI_WRITE_PORT_ULONG((PULONG)&ohci->regs->roothub.portstatus [temp], RH_PS_LSDA);
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}
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}
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// flush those writes
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(VOID)OHCI_READ_PORT_ULONG((PULONG)&ohci->regs->control);
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RtlZeroMemory(ohci->hcca, sizeof(OHCI_HCCA));
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/* 2msec timelimit here means no irqs/preempt */
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//spin_lock_irq (&ohci->lock);
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//retry:
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/* HC Reset requires max 10 us delay */
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OHCI_WRITE_PORT_ULONG((PULONG)&ohci->regs->cmdstatus, OHCI_HCR);
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temp = 30; /* ... allow extra time */
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while ((OHCI_READ_PORT_ULONG ((PULONG)&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
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if (--temp == 0) {
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//spin_unlock_irq (&ohci->lock);
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//ohci_err (ohci, "USB HC reset timed out!\n");
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DbgPrint("OHCI: USB HC reset timed out!\n");
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return FALSE;
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}
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KeStallExecutionProcessor(1);
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}
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/* now we're in the SUSPEND state ... must go OPERATIONAL
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* within 2msec else HC enters RESUME
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*
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* ... but some hardware won't init fmInterval "by the book"
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* (SiS, OPTi ...), so reset again instead. SiS doesn't need
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* this if we write fmInterval after we're OPERATIONAL.
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* Unclear about ALi, ServerWorks, and others ... this could
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* easily be a longstanding bug in chip init on Linux.
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*/
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#if 0
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ehci = struct_ptr(hcd, EHCI_DEV, hcd_interf);
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base = ehci->port_base;
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// stop the controller
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tmp = EHCI_READ_PORT_ULONG((PULONG) (base + EHCI_USBCMD));
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usbcmd = (PEHCI_USBCMD_CONTENT) & tmp;
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usbcmd->run_stop = 0;
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_USBCMD), tmp);
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// wait the controller stop( ehci spec, 16 microframe )
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usb_wait_ms_dpc(2);
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// reset the controller
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usbcmd = (PEHCI_USBCMD_CONTENT) & tmp;
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usbcmd->hcreset = TRUE;
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_USBCMD), tmp);
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for(;;)
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{
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// interval.QuadPart = -100 * 10000; // 10 ms
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// KeDelayExecutionThread( KernelMode, FALSE, &interval );
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KeStallExecutionProcessor(10);
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tmp = EHCI_READ_PORT_ULONG((PULONG) (base + EHCI_USBCMD));
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if (!usbcmd->hcreset)
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break;
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}
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// prepare the registers
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_CTRLDSSEGMENT), 0);
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// turn on all the int
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_USBINTR),
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EHCI_USBINTR_INTE | EHCI_USBINTR_ERR | EHCI_USBINTR_ASYNC | EHCI_USBINTR_HSERR
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// EHCI_USBINTR_FLROVR | \ // it is noisy
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// EHCI_USBINTR_PC // we detect it by polling
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);
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// write the list base reg
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_PERIODICLISTBASE), ehci->frame_list_phys_addr.LowPart);
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_ASYNCLISTBASE), ehci->skel_async_qh->phys_addr & ~(0x1f));
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usbcmd->int_threshold = 1;
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_USBCMD), tmp);
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// let's rock
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usbcmd->run_stop = 1;
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_USBCMD), tmp);
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// set the configuration flag
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_CONFIGFLAG), 1);
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// enable the list traversaling
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usbcmd->async_enable = 1;
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usbcmd->periodic_enable = 1;
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EHCI_WRITE_PORT_ULONG((PULONG) (base + EHCI_USBCMD), tmp);
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if (ohci->flags & OHCI_QUIRK_INITRESET) {
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ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
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// flush those writes
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(void) ohci_readl (ohci, &ohci->regs->control);
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}
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#endif
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/* Tell the controller where the control and bulk lists are
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* The lists are empty now. */
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OHCI_WRITE_PORT_ULONG((PULONG)&ohci->regs->ed_controlhead, 0);
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OHCI_WRITE_PORT_ULONG((PULONG)&ohci->regs->ed_bulkhead, 0);
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/* a reset clears this */
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OHCI_WRITE_PORT_ULONG((PULONG)&ohci->regs->hcca, (ULONG)ohci->hcca_logic_addr.LowPart);
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//periodic_reinit (ohci);
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/* start controller operations */
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hc_control &= OHCI_CTRL_RWC;
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hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
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OHCI_WRITE_PORT_ULONG((PULONG)&ohci->regs->control, hc_control);
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//ohci_to_hcd(ohci)->state = HC_STATE_RUNNING;
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/* wake on ConnectStatusChange, matching external hubs */
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OHCI_WRITE_PORT_ULONG((PULONG)&ohci->regs->roothub.status, RH_HS_DRWE);
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/* Choose the interrupts we care about now, others later on demand */
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mask = OHCI_INTR_INIT;
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//OHCI_WRITE_PORT_ULONG((PULONG)&ohci->regs->intrstatus, mask);
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//OHCI_WRITE_PORT_ULONG((PULONG)&ohci->regs->intrenable, mask);
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/* handle root hub init quirks ... */
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temp = roothub_a(ohci);
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temp &= ~(RH_A_PSM | RH_A_OCPM);
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OHCI_WRITE_PORT_ULONG((PULONG)&ohci->regs->roothub.status, RH_HS_LPSC);
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OHCI_WRITE_PORT_ULONG((PULONG)&ohci->regs->roothub.b, (temp & RH_A_NPS) ? 0 : RH_B_PPCM);
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// flush those writes
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(VOID)OHCI_READ_PORT_ULONG((PULONG)&ohci->regs->control);
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//spin_unlock_irq (&ohci->lock);
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// POTPGT delay is bits 24-31, in 2 ms units.
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ohci_wait_ms(ohci, (temp >> 23) & 0x1fe);
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//ohci_to_hcd(ohci)->state = HC_STATE_RUNNING;
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return TRUE;
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}
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@ -607,21 +709,49 @@ ohci_rh_reset_port(PHCD hcd, UCHAR port_idx)
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//ULONG i;
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POHCI_DEV ohci;
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//ULONG status;
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//UCHAR port_count;
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if (hcd == NULL)
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return FALSE;
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ohci = ohci_from_hcd(hcd);
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//port_count = (UCHAR) ((PEHCI_HCS_CONTENT) & ehci->ehci_caps.hcs_params)->port_count;
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//if (port_idx < 1 || port_idx > port_count)
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// return FALSE;
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//if (port_idx < 1 || port_idx > ohci->num_ports)
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// return FALSE;
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//usb_dbg_print(DBGLVL_MAXIMUM, ("ohci_rh_reset_port(): status after written=0x%x\n", status));
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return TRUE;
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}
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BOOLEAN
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ohci_rh_get_dev_change(PHCD hcd, PBYTE buf) //must have the rh dev_lock acquired
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{
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POHCI_DEV ohci;
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LONG i;
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ULONG status;
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if (hcd == NULL)
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return FALSE;
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ohci = ohci_from_hcd(hcd);
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for(i = 0; i < ohci->num_ports; i++)
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{
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status = OHCI_READ_PORT_ULONG((PULONG)(ohci->regs->roothub.portstatus[i]));
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if (status != 0)
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{
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ohci_dbg_print(DBGLVL_MAXIMUM, ("ohci_rh_get_dev_change(): erh port%d status=0x%x\n", i, status));
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}
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if (status & (RH_PS_PESC | RH_PS_CSC | RH_PS_OCIC))
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{
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buf[(i + 1) >> 3] |= (1 << ((i + 1) & 7));
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}
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}
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return TRUE;
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}
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NTSTATUS
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ohci_hcd_dispatch(PHCD hcd, LONG disp_code, PVOID param)
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{
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@ -630,24 +760,24 @@ ohci_hcd_dispatch(PHCD hcd, LONG disp_code, PVOID param)
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if (hcd == NULL)
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return STATUS_INVALID_PARAMETER;
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ohci = ohci_from_hcd(hcd);
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#if 0
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switch (disp_code)
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{
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case HCD_DISP_READ_PORT_COUNT:
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{
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if (param == NULL)
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return STATUS_INVALID_PARAMETER;
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*((PUCHAR) param) = (UCHAR) HCS_N_PORTS(ehci->ehci_caps.hcs_params);
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*((PUCHAR) param) = ohci->num_ports;
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return STATUS_SUCCESS;
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}
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case HCD_DISP_READ_RH_DEV_CHANGE:
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{
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if (ehci_rh_get_dev_change(hcd, param) == FALSE)
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if (ohci_rh_get_dev_change(hcd, param) == FALSE)
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return STATUS_INVALID_PARAMETER;
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return STATUS_SUCCESS;
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}
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}
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#endif
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return STATUS_NOT_IMPLEMENTED;
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}
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@ -114,6 +114,146 @@
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#define RH_A_NOCP (1 << 12) /* no over current protection */
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#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
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/*
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* OHCI Endpoint Descriptor (ED) ... holds TD queue
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* See OHCI spec, section 4.2
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*
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* This is a "Queue Head" for those transfers, which is why
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* both EHCI and UHCI call similar structures a "QH".
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*/
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typedef struct _OHCI_ED {
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/* first fields are hardware-specified */
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ULONG hwINFO; /* endpoint config bitmap */
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/* info bits defined by hcd */
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#define ED_DEQUEUE (1 << 27)
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/* info bits defined by the hardware */
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#define ED_ISO (1 << 15)
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#define ED_SKIP (1 << 14)
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#define ED_LOWSPEED (1 << 13)
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#define ED_OUT (0x01 << 11)
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#define ED_IN (0x02 << 11)
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ULONG hwTailP; /* tail of TD list */
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ULONG hwHeadP; /* head of TD list (hc r/w) */
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#define ED_C (0x02) /* toggle carry */
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#define ED_H (0x01) /* halted */
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ULONG hwNextED; /* next ED in list */
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/* rest are purely for the driver's use */
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#if 0
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dma_addr_t dma; /* addr of ED */
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struct _OHCI_TD *dummy; /* next TD to activate */
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/* host's view of schedule */
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struct _OHCI_ED *ed_next; /* on schedule or rm_list */
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struct _OHCI_ED *ed_prev; /* for non-interrupt EDs */
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struct list_head td_list; /* "shadow list" of our TDs */
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/* create --> IDLE --> OPER --> ... --> IDLE --> destroy
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* usually: OPER --> UNLINK --> (IDLE | OPER) --> ...
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*/
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UCHAR state; /* ED_{IDLE,UNLINK,OPER} */
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#define ED_IDLE 0x00 /* NOT linked to HC */
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#define ED_UNLINK 0x01 /* being unlinked from hc */
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#define ED_OPER 0x02 /* IS linked to hc */
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UCHAR type; /* PIPE_{BULK,...} */
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/* periodic scheduling params (for intr and iso) */
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UCHAR branch;
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USHORT interval;
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USHORT load;
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USHORT last_iso; /* iso only */
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/* HC may see EDs on rm_list until next frame (frame_no == tick) */
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USHORT tick;
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||||
#endif
|
||||
} OHCI_ED, *POHCI_ED;
|
||||
|
||||
#define ED_MASK ((u32)~0x0f) /* strip hw status in low addr bits */
|
||||
|
||||
|
||||
/*
|
||||
* OHCI Transfer Descriptor (TD) ... one per transfer segment
|
||||
* See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
|
||||
* and 4.3.2 (iso)
|
||||
*/
|
||||
typedef struct _OHCI_TD {
|
||||
/* first fields are hardware-specified */
|
||||
ULONG hwINFO; /* transfer info bitmask */
|
||||
|
||||
/* hwINFO bits for both general and iso tds: */
|
||||
#define TD_CC 0xf0000000 /* condition code */
|
||||
#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
|
||||
//#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
|
||||
#define TD_DI 0x00E00000 /* frames before interrupt */
|
||||
#define TD_DI_SET(X) (((X) & 0x07)<< 21)
|
||||
/* these two bits are available for definition/use by HCDs in both
|
||||
* general and iso tds ... others are available for only one type
|
||||
*/
|
||||
#define TD_DONE 0x00020000 /* retired to donelist */
|
||||
#define TD_ISO 0x00010000 /* copy of ED_ISO */
|
||||
|
||||
/* hwINFO bits for general tds: */
|
||||
#define TD_EC 0x0C000000 /* error count */
|
||||
#define TD_T 0x03000000 /* data toggle state */
|
||||
#define TD_T_DATA0 0x02000000 /* DATA0 */
|
||||
#define TD_T_DATA1 0x03000000 /* DATA1 */
|
||||
#define TD_T_TOGGLE 0x00000000 /* uses ED_C */
|
||||
#define TD_DP 0x00180000 /* direction/pid */
|
||||
#define TD_DP_SETUP 0x00000000 /* SETUP pid */
|
||||
#define TD_DP_IN 0x00100000 /* IN pid */
|
||||
#define TD_DP_OUT 0x00080000 /* OUT pid */
|
||||
/* 0x00180000 rsvd */
|
||||
#define TD_R 0x00040000 /* round: short packets OK? */
|
||||
|
||||
/* (no hwINFO #defines yet for iso tds) */
|
||||
|
||||
ULONG hwCBP; /* Current Buffer Pointer (or 0) */
|
||||
ULONG hwNextTD; /* Next TD Pointer */
|
||||
ULONG hwBE; /* Memory Buffer End Pointer */
|
||||
|
||||
/* PSW is only for ISO. Only 1 PSW entry is used, but on
|
||||
* big-endian PPC hardware that's the second entry.
|
||||
*/
|
||||
#define MAXPSW 2
|
||||
USHORT hwPSW [MAXPSW];
|
||||
|
||||
/* rest are purely for the driver's use */
|
||||
#if 0
|
||||
UCHAR index;
|
||||
struct ed *ed;
|
||||
struct td *td_hash; /* dma-->td hashtable */
|
||||
struct td *next_dl_td;
|
||||
struct urb *urb;
|
||||
|
||||
dma_addr_t td_dma; /* addr of this TD */
|
||||
dma_addr_t data_dma; /* addr of data it points to */
|
||||
|
||||
struct list_head td_list; /* "shadow list", TDs on same ED */
|
||||
#endif
|
||||
} OHCI_TD, *POHCI_TD;
|
||||
|
||||
/*
|
||||
* The HCCA (Host Controller Communications Area) is a 256 byte
|
||||
* structure defined section 4.4.1 of the OHCI spec. The HC is
|
||||
* told the base address of it. It must be 256-byte aligned.
|
||||
*/
|
||||
typedef struct _OHCI_HCCA
|
||||
{
|
||||
#define NUM_INTS 32
|
||||
ULONG int_table [NUM_INTS]; /* periodic schedule */
|
||||
|
||||
/*
|
||||
* OHCI defines u16 frame_no, followed by u16 zero pad.
|
||||
* Since some processors can't do 16 bit bus accesses,
|
||||
* portable access must be a 32 bits wide.
|
||||
*/
|
||||
ULONG frame_no; /* current frame number */
|
||||
ULONG done_head; /* info returned for an interrupt */
|
||||
UCHAR reserved_for_hc [116];
|
||||
UCHAR what [4]; /* spec only identifies 252 bytes :) */
|
||||
} OHCI_HCCA, *POHCI_HCCA;
|
||||
|
||||
/*
|
||||
* This is the structure of the OHCI controller's memory mapped I/O region.
|
||||
* You must use readl() and writel() (in <asm/io.h>) to access these fields!!
|
||||
|
|
@ -165,6 +305,13 @@ typedef struct _OHCI_DEV
|
|||
BOOLEAN port_mapped;
|
||||
PBYTE port_base; // note: added by ehci_caps.length, operational regs base addr, not the actural base
|
||||
struct _OHCI_REGS *regs;
|
||||
struct _OHCI_HCCA *hcca;
|
||||
PVOID td_cache;
|
||||
PVOID ed_cache;
|
||||
|
||||
PHYSICAL_ADDRESS hcca_logic_addr;
|
||||
PHYSICAL_ADDRESS td_logic_addr;
|
||||
PHYSICAL_ADDRESS ed_logic_addr;
|
||||
|
||||
USHORT num_ports;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue