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[NTOSKRNL]
- Add MiPdeToAddress and MI_IS_PAGE_LARGE for amd64 - Fix a pragma message - Add some missing globals for amd64 svn path=/branches/cmake-bringup/; revision=50209
This commit is contained in:
Timo Kreuzer
parent
78cc22ef6f
commit
dd830cafba
3 changed files with 23 additions and 15 deletions
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@ -131,6 +131,7 @@ MiPteToAddress(PMMPTE Pte)
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Temp >>= 16;
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return (PVOID)Temp;
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}
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#define MiPdeToAddress MiPteToAddress
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BOOLEAN
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FORCEINLINE
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@ -199,6 +200,7 @@ MmInitGlobalKernelPageDirectory(VOID)
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#define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
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#define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
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#define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
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#define MI_IS_PAGE_LARGE(x) ((x)->u.Hard.LargePage == 1)
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#if !defined(CONFIG_SMP)
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#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
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#else
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@ -549,7 +549,7 @@ IoAllocateIrp(IN CCHAR StackSize,
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if (ChargeQuota) Flags |= IRP_QUOTA_CHARGED;
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/* FIXME: Implement Lookaside Floats */
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/* Figure out which Lookaside List to use */
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if ((StackSize <= 8) && (ChargeQuota == FALSE))
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{
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@ -1823,7 +1823,7 @@ NTAPI
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IoIs32bitProcess(
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IN PIRP Irp OPTIONAL)
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{
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#pragma message IoIs32bitProcess is hardcoded to FALSE
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#pragma message "IoIs32bitProcess is hardcoded to FALSE"
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return FALSE;
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}
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#endif
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@ -27,10 +27,16 @@ HalInitializeBios(ULONG Unknown, PLOADER_PARAMETER_BLOCK LoaderBlock);
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/* GLOBALS *****************************************************************/
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/* Template PTE and PDE for a kernel page */
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MMPTE ValidKernelPde = {.u.Hard.Valid = 1, .u.Hard.Write = 1, .u.Hard.Dirty = 1, .u.Hard.Accessed = 1};
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MMPTE ValidKernelPte = {.u.Hard.Valid = 1, .u.Hard.Write = 1, .u.Hard.Dirty = 1, .u.Hard.Accessed = 1};
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MMPDE DemandZeroPde = {.u.Long = (MM_READWRITE << MM_PTE_SOFTWARE_PROTECTION_BITS)};
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MMPTE PrototypePte = {.u.Long = (MM_READWRITE << MM_PTE_SOFTWARE_PROTECTION_BITS) | PTE_PROTOTYPE | 0xFFFFF000};
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MMPTE ValidKernelPde = {{PTE_VALID|PTE_READWRITE|PTE_DIRTY|PTE_ACCESSED}};
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MMPTE ValidKernelPte = {{PTE_VALID|PTE_READWRITE|PTE_DIRTY|PTE_ACCESSED}};
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/* Template PDE for a demand-zero page */
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MMPDE DemandZeroPde = {{MM_READWRITE << MM_PTE_SOFTWARE_PROTECTION_BITS}};
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MMPTE DemandZeroPte = {{MM_READWRITE << MM_PTE_SOFTWARE_PROTECTION_BITS}};
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/* Template PTE for prototype page */
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MMPTE PrototypePte = {{(MM_READWRITE << MM_PTE_SOFTWARE_PROTECTION_BITS) |
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PTE_PROTOTYPE | (MI_PTE_LOOKUP_NEEDED << PAGE_SHIFT)}};
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/* Sizes */
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///SIZE_T MmSessionSize = MI_SESSION_SIZE;
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@ -413,7 +419,7 @@ MiInitializePageTable()
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TmplPte.u.Flush.Write = 1;
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HyperTemplatePte = TmplPte;
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/* Create PDPTs (72 KB) for shared system address space,
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/* Create PDPTs (72 KB) for shared system address space,
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* skip page tables and hyperspace */
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/* Loop the PXEs */
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@ -492,7 +498,7 @@ MiBuildNonPagedPool(VOID)
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/* Page-align the nonpaged pool size */
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MmSizeOfNonPagedPoolInBytes &= ~(PAGE_SIZE - 1);
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/* Now, check if there was a registry size for the maximum size */
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if (!MmMaximumNonPagedPoolInBytes)
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{
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@ -501,7 +507,7 @@ MiBuildNonPagedPool(VOID)
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MmMaximumNonPagedPoolInBytes += (MmNumberOfPhysicalPages - 1024) /
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256 * MmMaxAdditionNonPagedPoolPerMb;
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}
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/* Don't let the maximum go too high */
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if (MmMaximumNonPagedPoolInBytes > MI_MAX_NONPAGED_POOL_SIZE)
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{
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@ -517,7 +523,7 @@ MiBuildNonPagedPool(VOID)
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{
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/* Put non paged pool after the PFN database */
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MmNonPagedPoolStart = (PCHAR)MmPfnDatabase + MxPfnSizeInBytes;
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MmMaximumNonPagedPoolInBytes = (ULONG64)MmNonPagedPoolEnd -
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MmMaximumNonPagedPoolInBytes = (ULONG64)MmNonPagedPoolEnd -
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(ULONG64)MmNonPagedPoolStart;
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}
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@ -688,7 +694,7 @@ MiBuildPagedPool_x(VOID)
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PMMPTE Pte;
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MMPTE TmplPte;
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ULONG Size, BitMapSize;
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/* Default size for paged pool is 4 times non paged pool */
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MmSizeOfPagedPoolInBytes = 4 * MmMaximumNonPagedPoolInBytes;
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@ -767,7 +773,7 @@ MiBuildPagedPool_x(VOID)
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// Allocate the allocation bitmap, which tells us which regions have not yet
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// been mapped into memory
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MmPagedPoolInfo.PagedPoolAllocationMap =
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MmPagedPoolInfo.PagedPoolAllocationMap =
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ExAllocatePoolWithTag(NonPagedPool, Size, ' mM');
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ASSERT(MmPagedPoolInfo.PagedPoolAllocationMap);
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@ -783,7 +789,7 @@ MiBuildPagedPool_x(VOID)
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// Given the allocation bitmap and a base address, we can therefore figure
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// out which page is the last page of that allocation, and thus how big the
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// entire allocation is.
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MmPagedPoolInfo.EndOfPagedPoolBitmap =
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MmPagedPoolInfo.EndOfPagedPoolBitmap =
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ExAllocatePoolWithTag(NonPagedPool, Size, ' mM');
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ASSERT(MmPagedPoolInfo.EndOfPagedPoolBitmap);
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@ -859,7 +865,7 @@ MmArmInitSystem_x(IN ULONG Phase,
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//MmPagedPoolSize = MM_PAGED_POOL_SIZE;
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//ASSERT((PCHAR)MmPagedPoolBase + MmPagedPoolSize < (PCHAR)MmNonPagedSystemStart);
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HalInitializeBios(0, LoaderBlock);
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}
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@ -871,7 +877,7 @@ FASTCALL
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MiSyncARM3WithROS(IN PVOID AddressStart,
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IN PVOID AddressEnd)
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{
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}
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NTSTATUS
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