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- pciidex: Fix Hardware IDs returned for channel PDOs
- pciidex: Better test to see if the PCI controller is in compatible or native mode before getting channel resources - pciidex: Change IDE_DRIVE_IDENTIFY structure to IDENTIFY_DATA structure - pciide: Implement PciIdeUseDma - pciide: Tell that channel state is unknown instead of enabled svn path=/trunk/; revision=19092
This commit is contained in:
parent
a1713a521f
commit
dc3bd90918
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@ -44,10 +44,7 @@ PciIdeChannelEnabled(
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return ChannelDisabled;
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}
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/* FIXME: I don't know where to find the enabled/disabled
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* bits for channels, so assume they are always enabled
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*/
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return ChannelEnabled;
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return ChannelStateUnknown;
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}
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BOOLEAN NTAPI
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@ -74,15 +71,16 @@ PciIdeTransferModeSelect(
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return STATUS_SUCCESS;
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}
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BOOLEAN NTAPI
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ULONG NTAPI
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PciIdeUseDma(
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IN PVOID DeviceExtension,
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IN PUCHAR CdbCommand,
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IN PUCHAR Slave)
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{
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DPRINT1("PciIdeUseDma(%p %p %p)\n", DeviceExtension, CdbCommand, Slave);
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DPRINT("PciIdeUseDma(%p %p %p)\n", DeviceExtension, CdbCommand, Slave);
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return FALSE;
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/* Nothing should prevent us to use DMA */
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return 1;
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}
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NTSTATUS NTAPI
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@ -99,7 +97,7 @@ PciIdeGetControllerProperties(
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ControllerProperties->IgnoreActiveBitForAtaDevice = FALSE;
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ControllerProperties->AlwaysClearBusMasterInterrupt = TRUE;
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ControllerProperties->PciIdeUseDma = PciIdeUseDma;
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ControllerProperties->AlignmentRequirement = 1; /* FIXME */
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ControllerProperties->AlignmentRequirement = 1;
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ControllerProperties->DefaultPIO = 0; /* FIXME */
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ControllerProperties->PciIdeUdmaModesSupported = NULL; /* optional */
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@ -82,7 +82,6 @@ cleanup:
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return Status;
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}
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/*
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static NTSTATUS
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ReleaseBusInterface(
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IN PFDO_DEVICE_EXTENSION DeviceExtension)
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@ -99,7 +98,6 @@ ReleaseBusInterface(
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return Status;
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}
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*/
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NTSTATUS NTAPI
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PciIdeXAddDevice(
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@ -109,6 +107,8 @@ PciIdeXAddDevice(
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PPCIIDEX_DRIVER_EXTENSION DriverExtension;
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PFDO_DEVICE_EXTENSION DeviceExtension;
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PDEVICE_OBJECT Fdo;
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ULONG BytesRead;
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PCI_COMMON_CONFIG PciConfig;
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NTSTATUS Status;
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DPRINT("PciIdeXAddDevice(%p %p)\n", DriverObject, Pdo);
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@ -145,10 +145,28 @@ PciIdeXAddDevice(
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Status = GetBusInterface(DeviceExtension);
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if (!NT_SUCCESS(Status))
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{
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DPRINT("GetBusInterface() failed() failed with status 0x%08lx\n", Status);
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DPRINT("GetBusInterface() failed with status 0x%08lx\n", Status);
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IoDetachDevice(DeviceExtension->LowerDevice);
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return Status;
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}
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BytesRead = (*DeviceExtension->BusInterface->GetBusData)(
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DeviceExtension->BusInterface->Context,
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PCI_WHICHSPACE_CONFIG,
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&PciConfig,
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0,
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PCI_COMMON_HDR_LENGTH);
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if (BytesRead != PCI_COMMON_HDR_LENGTH)
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{
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DPRINT("BusInterface->GetBusData() failed()\n");
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ReleaseBusInterface(DeviceExtension);
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IoDetachDevice(DeviceExtension->LowerDevice);
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return STATUS_IO_DEVICE_ERROR;
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}
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DeviceExtension->VendorId = PciConfig.VendorID;
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DeviceExtension->DeviceId = PciConfig.DeviceID;
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Fdo->Flags &= ~DO_DEVICE_INITIALIZING;
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return STATUS_SUCCESS;
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@ -156,7 +174,7 @@ PciIdeXAddDevice(
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static NTSTATUS NTAPI
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PciIdeXUdmaModesSupported(
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IN IDE_DRIVE_IDENTIFY IdentifyData,
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IN IDENTIFY_DATA IdentifyData,
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OUT PULONG BestXferMode,
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OUT PULONG CurrentXferMode)
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{
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@ -317,7 +335,7 @@ PciIdeXFdoQueryBusRelations(
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}
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ChannelState = DeviceExtension->Properties.PciIdeChannelEnabled(
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DeviceExtension->MiniControllerExtension, i);
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if (ChannelState != ChannelEnabled)
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if (ChannelState == ChannelDisabled)
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{
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DPRINT("Channel %lu is disabled\n", i);
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continue;
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@ -67,7 +67,7 @@ PciIdeXGetBusData(
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{
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PFDO_DEVICE_EXTENSION FdoDeviceExtension;
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ULONG BytesRead = 0;
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NTSTATUS Status = STATUS_UNSUCCESSFUL;
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NTSTATUS Status = STATUS_IO_DEVICE_ERROR;
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DPRINT("PciIdeXGetBusData(%p %p 0x%lx 0x%lx)\n",
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DeviceExtension, Buffer, ConfigDataOffset, BufferLength);
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@ -32,6 +32,8 @@ typedef struct _FDO_DEVICE_EXTENSION
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PHYSICAL_ADDRESS BusMasterPortBase;
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PDEVICE_OBJECT LowerDevice;
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PDEVICE_OBJECT Pdo[MAX_IDE_CHANNEL];
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USHORT VendorId;
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USHORT DeviceId;
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PBYTE MiniControllerExtension[0];
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} FDO_DEVICE_EXTENSION, *PFDO_DEVICE_EXTENSION;
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@ -18,6 +18,7 @@ PciIdeXPdoQueryId(
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OUT ULONG_PTR* Information)
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{
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PPDO_DEVICE_EXTENSION DeviceExtension;
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PFDO_DEVICE_EXTENSION FdoDeviceExtension;
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WCHAR Buffer[256];
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ULONG Index = 0;
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ULONG IdType;
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@ -27,6 +28,7 @@ PciIdeXPdoQueryId(
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IdType = IoGetCurrentIrpStackLocation(Irp)->Parameters.QueryId.IdType;
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DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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FdoDeviceExtension = (PFDO_DEVICE_EXTENSION)DeviceExtension->ControllerFdo->DeviceExtension;
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switch (IdType)
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{
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@ -40,26 +42,62 @@ PciIdeXPdoQueryId(
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{
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DPRINT("IRP_MJ_PNP / IRP_MN_QUERY_ID / BusQueryHardwareIDs\n");
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switch (FdoDeviceExtension->VendorId)
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{
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case 0x0e11:
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Index += swprintf(&Buffer[Index], L"Compaq-%04x", FdoDeviceExtension->DeviceId) + 1;
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break;
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case 0x1039:
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Index += swprintf(&Buffer[Index], L"SiS-%04x", FdoDeviceExtension->DeviceId) + 1;
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break;
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case 0x1050:
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Index += swprintf(&Buffer[Index], L"WinBond-%04x", FdoDeviceExtension->DeviceId) + 1;
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break;
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case 0x1095:
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Index += swprintf(&Buffer[Index], L"CMD-%04x", FdoDeviceExtension->DeviceId) + 1;
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break;
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case 0x8086:
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{
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switch (FdoDeviceExtension->DeviceId)
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{
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case 0x1230:
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Index += swprintf(&Buffer[Index], L"Intel-PIIX") + 1;
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break;
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case 0x7010:
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Index += swprintf(&Buffer[Index], L"Intel-PIIX3") + 1;
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break;
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case 0x7111:
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Index += swprintf(&Buffer[Index], L"Intel-PIIX4") + 1;
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break;
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default:
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Index += swprintf(&Buffer[Index], L"Intel-%04x", FdoDeviceExtension->DeviceId) + 1;
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break;
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}
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break;
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}
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default:
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break;
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}
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if (DeviceExtension->Channel == 0)
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Index += swprintf(&Buffer[Index], L"Primary_IDE_Channel");
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Index += swprintf(&Buffer[Index], L"Primary_IDE_Channel") + 1;
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else
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Index += swprintf(&Buffer[Index], L"Secondary_IDE_Channel");
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Index++;
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Index += swprintf(&Buffer[Index], L"Secondary_IDE_Channel") + 1;
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Index += swprintf(&Buffer[Index], L"*PNP0600") + 1;
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Buffer[Index] = UNICODE_NULL;
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SourceString.Length = SourceString.MaximumLength = Index * sizeof(WCHAR);
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SourceString.Buffer = Buffer;
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break;
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}
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case BusQueryCompatibleIDs:
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{
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DPRINT("IRP_MJ_PNP / IRP_MN_QUERY_ID / BusQueryCompatibleIDs\n");
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Index += swprintf(&Buffer[Index],
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L"*PNP0600");
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Index++;
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Index += swprintf(&Buffer[Index], L"*PNP0600") + 1;
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Buffer[Index] = UNICODE_NULL;
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SourceString.Length = SourceString.MaximumLength = Index * sizeof(WCHAR);
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SourceString.Buffer = Buffer;
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break;
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}
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case BusQueryInstanceID:
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{
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DPRINT("IRP_MJ_PNP / IRP_MN_QUERY_ID / BusQueryInstanceID\n");
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}
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default:
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DPRINT1("IRP_MJ_PNP / IRP_MN_QUERY_ID / unknown query id type 0x%lx\n", IdType);
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#ifndef NDEBUG
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DbgBreakPoint();
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#endif
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ASSERT(FALSE);
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return STATUS_NOT_SUPPORTED;
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}
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@ -94,21 +130,22 @@ GetCurrentResources(
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PPDO_DEVICE_EXTENSION DeviceExtension;
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PFDO_DEVICE_EXTENSION FdoDeviceExtension;
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ULONG BaseIndex;
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ULONG BytesRead;
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PCI_COMMON_CONFIG PciConfig;
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NTSTATUS Status;
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NTSTATUS ret = STATUS_UNSUCCESSFUL;
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DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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FdoDeviceExtension = (PFDO_DEVICE_EXTENSION)DeviceExtension->ControllerFdo->DeviceExtension;
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BaseIndex = DeviceExtension->Channel * 2;
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Status = PciIdeXGetBusData(
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FdoDeviceExtension->MiniControllerExtension,
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BytesRead = (*FdoDeviceExtension->BusInterface->GetBusData)(
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FdoDeviceExtension->BusInterface->Context,
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PCI_WHICHSPACE_CONFIG,
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&PciConfig,
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0,
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PCI_COMMON_HDR_LENGTH);
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if (!NT_SUCCESS(Status))
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return Status;
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if (BytesRead != PCI_COMMON_HDR_LENGTH)
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return STATUS_IO_DEVICE_ERROR;
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/* We have found a known native pci ide controller */
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if ((PciConfig.ProgIf & 0x80) && (PciConfig.u.type0.BaseAddresses[4] & PCI_ADDRESS_IO_SPACE))
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*BusMasterPortBase = 0;
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}
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if ((PciConfig.ProgIf >> BaseIndex) & 0x1)
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{
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/* Native mode */
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if ((PciConfig.u.type0.BaseAddresses[BaseIndex + 0] & PCI_ADDRESS_IO_SPACE) &&
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(PciConfig.u.type0.BaseAddresses[BaseIndex + 1] & PCI_ADDRESS_IO_SPACE))
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{
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*InterruptVector = PciConfig.u.type0.InterruptLine;
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ret = STATUS_SUCCESS;
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}
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}
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else
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{
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/* Compatibility mode */
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switch (DeviceExtension->Channel)
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{
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case 0:
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}
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default:
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DPRINT1("IRP_MJ_PNP / IRP_MN_QUERY_DEVICE_TEXT / unknown type 0x%lx\n", DeviceTextType);
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#ifndef NDEBUG
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DbgBreakPoint();
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#endif
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ASSERT(FALSE);
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return STATUS_NOT_SUPPORTED;
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}
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@ -370,9 +410,7 @@ PciIdeXPdoPnpDispatch(
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{
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DPRINT1("IRP_MJ_PNP / IRP_MN_QUERY_DEVICE_RELATIONS / Unknown type 0x%lx\n",
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Stack->Parameters.QueryDeviceRelations.Type);
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#ifndef NDEBUG
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DbgBreakPoint();
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#endif
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ASSERT(FALSE);
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Status = STATUS_NOT_SUPPORTED;
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break;
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}
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@ -456,9 +494,7 @@ PciIdeXPdoPnpDispatch(
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/* We can't forward request to the lower driver, because
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* we are a Pdo, so we don't have lower driver... */
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DPRINT1("IRP_MJ_PNP / Unknown minor function 0x%lx\n", MinorFunction);
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#ifndef NDEBUG
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DbgBreakPoint();
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#endif
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ASSERT(FALSE);
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Information = Irp->IoStatus.Information;
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Status = Irp->IoStatus.Status;
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}
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@ -32,87 +32,173 @@ extern "C" {
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#endif
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#define MAX_IDE_CHANNEL 2
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#define MAX_IDE_LINE 2
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#define MAX_IDE_DEVICE 2
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#include <pshpack1.h>
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typedef struct _IDE_DRIVE_IDENTIFY
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{
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USHORT GeneralConfiguration;
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USHORT NumberOfCylinders;
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USHORT Reserved1;
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USHORT NumberOfHeads;
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USHORT UnformattedBytesPerTrack;
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USHORT UnformattedBytesPerSector;
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USHORT SectorsPerTrack;
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USHORT VendorUnique1[3];
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BYTE SerialNumber[20];
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USHORT BufferType;
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USHORT BufferSectorSize;
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USHORT NumberOfEccBytes;
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BYTE FirmwareRevision[8];
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BYTE ModelNumber[40];
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BYTE MaximumBlockTransfer;
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BYTE VendorUnique2;
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USHORT DoubleWordIo;
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USHORT Capabilities;
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USHORT Reserved2;
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BYTE VendorUnique3;
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BYTE PioCycleTimingMode;
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BYTE VendorUnique4;
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BYTE DmaCycleTimingMode;
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USHORT TranslationFieldsValid:3;
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USHORT Reserved3:13;
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USHORT NumberOfCurrentCylinders;
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USHORT NumberOfCurrentHeads;
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USHORT CurrentSectorsPerTrack;
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ULONG CurrentSectorCapacity;
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USHORT CurrentMultiSectorSetting;
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ULONG UserAddressableSectors;
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USHORT SingleWordDMASupport : 8;
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USHORT SingleWordDMAActive : 8;
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USHORT MultiWordDMASupport : 8;
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USHORT MultiWordDMAActive : 8;
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USHORT AdvancedPIOModes : 8;
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USHORT Reserved4 : 8;
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USHORT MinimumMWXferCycleTime;
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USHORT RecommendedMWXferCycleTime;
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USHORT MinimumPIOCycleTime;
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USHORT MinimumPIOCycleTimeIORDY;
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USHORT Reserved5[11];
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USHORT MajorRevision;
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USHORT MinorRevision;
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USHORT Reserved6[6];
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USHORT UltraDMASupport : 8;
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USHORT UltraDMAActive : 8;
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USHORT Reserved7[37];
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USHORT LastLun:3;
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USHORT Reserved8:13;
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USHORT MediaStatusNotification:2;
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USHORT Reserved9:6;
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USHORT DeviceWriteProtect:1;
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USHORT Reserved10:7;
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USHORT Reserved11[128];
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} IDE_DRIVE_IDENTIFY, *PIDE_DRIVE_IDENTIFY;
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typedef struct _IDENTIFY_DATA {
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USHORT GeneralConfiguration; /* 00 */
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USHORT NumCylinders; /* 02 */
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USHORT Reserved1; /* 04 */
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USHORT NumHeads; /* 06 */
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USHORT UnformattedBytesPerTrack; /* 08 */
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USHORT UnformattedBytesPerSector; /* 10 */
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USHORT NumSectorsPerTrack; /* 12 */
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USHORT VendorUnique1[3]; /* 14 */
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UCHAR SerialNumber[20]; /* 20 */
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USHORT BufferType; /* 40 */
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USHORT BufferSectorSize; /* 42 */
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USHORT NumberOfEccBytes; /* 44 */
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UCHAR FirmwareRevision[8]; /* 46 */
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UCHAR ModelNumber[40]; /* 54 */
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UCHAR MaximumBlockTransfer; /* 94 */
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UCHAR VendorUnique2; /* 95 */
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USHORT DoubleWordIo; /* 96 */
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USHORT Capabilities; /* 98 */
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USHORT Reserved2; /* 100 */
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UCHAR VendorUnique3; /* 102 */
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UCHAR PioCycleTimingMode; /* 103 */
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UCHAR VendorUnique4; /* 104 */
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UCHAR DmaCycleTimingMode; /* 105 */
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USHORT TranslationFieldsValid:3; /* 106 */
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USHORT Reserved3:13; /* - */
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USHORT NumberOfCurrentCylinders; /* 108 */
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USHORT NumberOfCurrentHeads; /* 110 */
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USHORT CurrentSectorsPerTrack; /* 112 */
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ULONG CurrentSectorCapacity; /* 114 */
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USHORT CurrentMultiSectorSetting; /* 118 */
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ULONG UserAddressableSectors; /* 120 */
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USHORT SingleWordDMASupport:8; /* 124 */
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USHORT SingleWordDMAActive:8; /* - */
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USHORT MultiWordDMASupport:8; /* 126 */
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USHORT MultiWordDMAActive:8; /* - */
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USHORT AdvancedPIOModes:8; /* 128 */
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USHORT Reserved4:8; /* - */
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USHORT MinimumMWXferCycleTime; /* 130 */
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USHORT RecommendedMWXferCycleTime; /* 132 */
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USHORT MinimumPIOCycleTime; /* 134 */
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USHORT MinimumPIOCycleTimeIORDY; /* 136 */
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USHORT Reserved5[11]; /* 138 */
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USHORT MajorRevision; /* 160 */
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USHORT MinorRevision; /* 162 */
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USHORT Reserved6; /* 164 */
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USHORT CommandSetSupport; /* 166 */
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USHORT Reserved6a[2]; /* 168 */
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USHORT CommandSetActive; /* 172 */
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USHORT Reserved6b; /* 174 */
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USHORT UltraDMASupport:8; /* 176 */
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USHORT UltraDMAActive:8; /* - */
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USHORT Reserved7[11]; /* 178 */
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ULONG Max48BitLBA[2]; /* 200 */
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USHORT Reserved7a[22]; /* 208 */
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USHORT LastLun:3; /* 252 */
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USHORT Reserved8:13; /* - */
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USHORT MediaStatusNotification:2; /* 254 */
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USHORT Reserved9:6; /* - */
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USHORT DeviceWriteProtect:1; /* - */
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USHORT Reserved10:7; /* - */
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USHORT Reserved11[128]; /* 256 */
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} IDENTIFY_DATA, *PIDENTIFY_DATA;
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typedef struct _EXTENDED_IDENTIFY_DATA {
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USHORT GeneralConfiguration; /* 00 */
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USHORT NumCylinders; /* 02 */
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USHORT Reserved1; /* 04 */
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USHORT NumHeads; /* 06 */
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USHORT UnformattedBytesPerTrack; /* 08 */
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||||
USHORT UnformattedBytesPerSector; /* 10 */
|
||||
USHORT NumSectorsPerTrack; /* 12 */
|
||||
union
|
||||
{
|
||||
USHORT VendorUnique1[3]; /* 14 */
|
||||
struct
|
||||
{
|
||||
UCHAR InterSectorGap; /* 14 */
|
||||
UCHAR InterSectorGapSize; /* - */
|
||||
UCHAR Reserved16; /* 16 */
|
||||
UCHAR BytesInPLO; /* - */
|
||||
USHORT VendorUniqueCnt; /* 18 */
|
||||
} u;
|
||||
};
|
||||
UCHAR SerialNumber[20]; /* 20 */
|
||||
USHORT BufferType; /* 40 */
|
||||
USHORT BufferSectorSize; /* 42 */
|
||||
USHORT NumberOfEccBytes; /* 44 */
|
||||
UCHAR FirmwareRevision[8]; /* 46 */
|
||||
UCHAR ModelNumber[40]; /* 54 */
|
||||
UCHAR MaximumBlockTransfer; /* 94 */
|
||||
UCHAR VendorUnique2; /* 95 */
|
||||
USHORT DoubleWordIo; /* 96 */
|
||||
USHORT Capabilities; /* 98 */
|
||||
USHORT Reserved2; /* 100 */
|
||||
UCHAR VendorUnique3; /* 102 */
|
||||
UCHAR PioCycleTimingMode; /* 103 */
|
||||
UCHAR VendorUnique4; /* 104 */
|
||||
UCHAR DmaCycleTimingMode; /* 105 */
|
||||
USHORT TranslationFieldsValid:3; /* 106 */
|
||||
USHORT Reserved3:13; /* - */
|
||||
USHORT NumberOfCurrentCylinders; /* 108 */
|
||||
USHORT NumberOfCurrentHeads; /* 110 */
|
||||
USHORT CurrentSectorsPerTrack; /* 112 */
|
||||
ULONG CurrentSectorCapacity; /* 114 */
|
||||
USHORT CurrentMultiSectorSetting; /* 118 */
|
||||
ULONG UserAddressableSectors; /* 120 */
|
||||
USHORT SingleWordDMASupport:8; /* 124 */
|
||||
USHORT SingleWordDMAActive:8; /* - */
|
||||
USHORT MultiWordDMASupport:8; /* 126 */
|
||||
USHORT MultiWordDMAActive:8; /* - */
|
||||
USHORT AdvancedPIOModes:8; /* 128 */
|
||||
USHORT Reserved4:8; /* - */
|
||||
USHORT MinimumMWXferCycleTime; /* 130 */
|
||||
USHORT RecommendedMWXferCycleTime; /* 132 */
|
||||
USHORT MinimumPIOCycleTime; /* 134 */
|
||||
USHORT MinimumPIOCycleTimeIORDY; /* 136 */
|
||||
USHORT Reserved5[11]; /* 138 */
|
||||
USHORT MajorRevision; /* 160 */
|
||||
USHORT MinorRevision; /* 162 */
|
||||
USHORT Reserved6; /* 164 */
|
||||
USHORT CommandSetSupport; /* 166 */
|
||||
USHORT Reserved6a[2]; /* 168 */
|
||||
USHORT CommandSetActive; /* 172 */
|
||||
USHORT Reserved6b; /* 174 */
|
||||
USHORT UltraDMASupport:8; /* 176 */
|
||||
USHORT UltraDMAActive:8; /* - */
|
||||
USHORT Reserved7[11]; /* 178 */
|
||||
ULONG Max48BitLBA[2]; /* 200 */
|
||||
USHORT Reserved7a[22]; /* 208 */
|
||||
USHORT LastLun:3; /* 252 */
|
||||
USHORT Reserved8:13; /* - */
|
||||
USHORT MediaStatusNotification:2; /* 254 */
|
||||
USHORT Reserved9:6; /* - */
|
||||
USHORT DeviceWriteProtect:1; /* - */
|
||||
USHORT Reserved10:7; /* - */
|
||||
USHORT Reserved11[128]; /* 256 */
|
||||
} EXTENDED_IDENTIFY_DATA, *PEXTENDED_IDENTIFY_DATA;
|
||||
#include <poppack.h>
|
||||
|
||||
typedef struct _PCIIDE_TRANSFER_MODE_SELECT
|
||||
{
|
||||
ULONG Channel;
|
||||
BOOLEAN DevicePresent[MAX_IDE_DEVICE];
|
||||
BOOLEAN FixedDisk[MAX_IDE_DEVICE];
|
||||
BOOLEAN IoReadySupported[MAX_IDE_DEVICE];
|
||||
ULONG DeviceTransferModeSupported[MAX_IDE_DEVICE];
|
||||
ULONG BestPioCycleTime[MAX_IDE_DEVICE];
|
||||
ULONG BestSwDmaCycleTime[MAX_IDE_DEVICE];
|
||||
ULONG BestMwDmaCycleTime[MAX_IDE_DEVICE];
|
||||
ULONG BestUDmaCycleTime[MAX_IDE_DEVICE];
|
||||
ULONG DeviceTransferModeCurrent[MAX_IDE_DEVICE];
|
||||
ULONG DeviceTransferModeSelected[MAX_IDE_DEVICE];
|
||||
BOOLEAN DevicePresent[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||
BOOLEAN FixedDisk[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||
BOOLEAN IoReadySupported[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||
ULONG DeviceTransferModeSupported[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||
ULONG BestPioCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||
ULONG BestSwDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||
ULONG BestMwDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||
ULONG BestUDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||
ULONG DeviceTransferModeCurrent[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||
ULONG UserChoiceTransferMode[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||
ULONG EnableUDMA66;
|
||||
IDENTIFY_DATA IdentifyData[MAX_IDE_DEVICE];
|
||||
ULONG DeviceTransferModeSelected[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||
PULONG TransferModeTimingTable;
|
||||
ULONG TransferModeTableLength;
|
||||
} PCIIDE_TRANSFER_MODE_SELECT, *PPCIIDE_TRANSFER_MODE_SELECT;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ChannelDisabled,
|
||||
ChannelDisabled = 0,
|
||||
ChannelEnabled,
|
||||
ChannelStateUnknown
|
||||
} IDE_CHANNEL_STATE;
|
||||
|
@ -131,7 +217,7 @@ typedef NTSTATUS
|
|||
IN PVOID DeviceExtension,
|
||||
IN OUT PPCIIDE_TRANSFER_MODE_SELECT XferMode);
|
||||
|
||||
typedef BOOLEAN
|
||||
typedef ULONG
|
||||
(NTAPI *PCIIDE_USEDMA_FUNC)(
|
||||
IN PVOID DeviceExtension,
|
||||
IN PUCHAR CdbCommand,
|
||||
|
@ -139,7 +225,7 @@ typedef BOOLEAN
|
|||
|
||||
typedef NTSTATUS
|
||||
(NTAPI *PCIIDE_UDMA_MODES_SUPPORTED)(
|
||||
IN IDE_DRIVE_IDENTIFY IdentifyData,
|
||||
IN IDENTIFY_DATA IdentifyData,
|
||||
OUT PULONG BestXferMode,
|
||||
OUT PULONG CurrentXferMode);
|
||||
|
||||
|
@ -210,6 +296,7 @@ PciIdeXSetBusData(
|
|||
#define UDMA_MODE2 (1 << 13)
|
||||
#define UDMA_MODE3 (1 << 14)
|
||||
#define UDMA_MODE4 (1 << 15)
|
||||
#define UDMA_MODE5 (1 << 16)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue