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- pciidex: Fix Hardware IDs returned for channel PDOs
- pciidex: Better test to see if the PCI controller is in compatible or native mode before getting channel resources - pciidex: Change IDE_DRIVE_IDENTIFY structure to IDENTIFY_DATA structure - pciide: Implement PciIdeUseDma - pciide: Tell that channel state is unknown instead of enabled svn path=/trunk/; revision=19092
This commit is contained in:
parent
a1713a521f
commit
dc3bd90918
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@ -44,10 +44,7 @@ PciIdeChannelEnabled(
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return ChannelDisabled;
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return ChannelDisabled;
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}
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}
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/* FIXME: I don't know where to find the enabled/disabled
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return ChannelStateUnknown;
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* bits for channels, so assume they are always enabled
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*/
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return ChannelEnabled;
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}
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}
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BOOLEAN NTAPI
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BOOLEAN NTAPI
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@ -74,15 +71,16 @@ PciIdeTransferModeSelect(
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return STATUS_SUCCESS;
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return STATUS_SUCCESS;
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}
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}
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BOOLEAN NTAPI
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ULONG NTAPI
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PciIdeUseDma(
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PciIdeUseDma(
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IN PVOID DeviceExtension,
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IN PVOID DeviceExtension,
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IN PUCHAR CdbCommand,
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IN PUCHAR CdbCommand,
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IN PUCHAR Slave)
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IN PUCHAR Slave)
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{
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{
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DPRINT1("PciIdeUseDma(%p %p %p)\n", DeviceExtension, CdbCommand, Slave);
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DPRINT("PciIdeUseDma(%p %p %p)\n", DeviceExtension, CdbCommand, Slave);
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return FALSE;
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/* Nothing should prevent us to use DMA */
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return 1;
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}
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}
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NTSTATUS NTAPI
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NTSTATUS NTAPI
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@ -99,7 +97,7 @@ PciIdeGetControllerProperties(
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ControllerProperties->IgnoreActiveBitForAtaDevice = FALSE;
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ControllerProperties->IgnoreActiveBitForAtaDevice = FALSE;
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ControllerProperties->AlwaysClearBusMasterInterrupt = TRUE;
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ControllerProperties->AlwaysClearBusMasterInterrupt = TRUE;
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ControllerProperties->PciIdeUseDma = PciIdeUseDma;
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ControllerProperties->PciIdeUseDma = PciIdeUseDma;
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ControllerProperties->AlignmentRequirement = 1; /* FIXME */
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ControllerProperties->AlignmentRequirement = 1;
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ControllerProperties->DefaultPIO = 0; /* FIXME */
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ControllerProperties->DefaultPIO = 0; /* FIXME */
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ControllerProperties->PciIdeUdmaModesSupported = NULL; /* optional */
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ControllerProperties->PciIdeUdmaModesSupported = NULL; /* optional */
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@ -82,7 +82,6 @@ cleanup:
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return Status;
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return Status;
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}
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}
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/*
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static NTSTATUS
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static NTSTATUS
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ReleaseBusInterface(
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ReleaseBusInterface(
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IN PFDO_DEVICE_EXTENSION DeviceExtension)
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IN PFDO_DEVICE_EXTENSION DeviceExtension)
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@ -99,7 +98,6 @@ ReleaseBusInterface(
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return Status;
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return Status;
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}
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}
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*/
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NTSTATUS NTAPI
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NTSTATUS NTAPI
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PciIdeXAddDevice(
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PciIdeXAddDevice(
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@ -109,6 +107,8 @@ PciIdeXAddDevice(
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PPCIIDEX_DRIVER_EXTENSION DriverExtension;
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PPCIIDEX_DRIVER_EXTENSION DriverExtension;
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PFDO_DEVICE_EXTENSION DeviceExtension;
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PFDO_DEVICE_EXTENSION DeviceExtension;
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PDEVICE_OBJECT Fdo;
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PDEVICE_OBJECT Fdo;
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ULONG BytesRead;
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PCI_COMMON_CONFIG PciConfig;
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NTSTATUS Status;
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NTSTATUS Status;
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DPRINT("PciIdeXAddDevice(%p %p)\n", DriverObject, Pdo);
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DPRINT("PciIdeXAddDevice(%p %p)\n", DriverObject, Pdo);
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@ -145,10 +145,28 @@ PciIdeXAddDevice(
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Status = GetBusInterface(DeviceExtension);
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Status = GetBusInterface(DeviceExtension);
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if (!NT_SUCCESS(Status))
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if (!NT_SUCCESS(Status))
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{
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{
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DPRINT("GetBusInterface() failed() failed with status 0x%08lx\n", Status);
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DPRINT("GetBusInterface() failed with status 0x%08lx\n", Status);
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IoDetachDevice(DeviceExtension->LowerDevice);
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return Status;
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return Status;
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}
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}
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BytesRead = (*DeviceExtension->BusInterface->GetBusData)(
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DeviceExtension->BusInterface->Context,
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PCI_WHICHSPACE_CONFIG,
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&PciConfig,
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0,
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PCI_COMMON_HDR_LENGTH);
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if (BytesRead != PCI_COMMON_HDR_LENGTH)
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{
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DPRINT("BusInterface->GetBusData() failed()\n");
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ReleaseBusInterface(DeviceExtension);
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IoDetachDevice(DeviceExtension->LowerDevice);
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return STATUS_IO_DEVICE_ERROR;
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}
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DeviceExtension->VendorId = PciConfig.VendorID;
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DeviceExtension->DeviceId = PciConfig.DeviceID;
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Fdo->Flags &= ~DO_DEVICE_INITIALIZING;
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Fdo->Flags &= ~DO_DEVICE_INITIALIZING;
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return STATUS_SUCCESS;
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return STATUS_SUCCESS;
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@ -156,7 +174,7 @@ PciIdeXAddDevice(
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static NTSTATUS NTAPI
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static NTSTATUS NTAPI
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PciIdeXUdmaModesSupported(
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PciIdeXUdmaModesSupported(
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IN IDE_DRIVE_IDENTIFY IdentifyData,
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IN IDENTIFY_DATA IdentifyData,
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OUT PULONG BestXferMode,
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OUT PULONG BestXferMode,
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OUT PULONG CurrentXferMode)
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OUT PULONG CurrentXferMode)
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{
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{
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@ -317,7 +335,7 @@ PciIdeXFdoQueryBusRelations(
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}
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}
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ChannelState = DeviceExtension->Properties.PciIdeChannelEnabled(
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ChannelState = DeviceExtension->Properties.PciIdeChannelEnabled(
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DeviceExtension->MiniControllerExtension, i);
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DeviceExtension->MiniControllerExtension, i);
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if (ChannelState != ChannelEnabled)
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if (ChannelState == ChannelDisabled)
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{
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{
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DPRINT("Channel %lu is disabled\n", i);
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DPRINT("Channel %lu is disabled\n", i);
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continue;
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continue;
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@ -67,7 +67,7 @@ PciIdeXGetBusData(
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{
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{
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PFDO_DEVICE_EXTENSION FdoDeviceExtension;
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PFDO_DEVICE_EXTENSION FdoDeviceExtension;
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ULONG BytesRead = 0;
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ULONG BytesRead = 0;
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NTSTATUS Status = STATUS_UNSUCCESSFUL;
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NTSTATUS Status = STATUS_IO_DEVICE_ERROR;
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DPRINT("PciIdeXGetBusData(%p %p 0x%lx 0x%lx)\n",
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DPRINT("PciIdeXGetBusData(%p %p 0x%lx 0x%lx)\n",
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DeviceExtension, Buffer, ConfigDataOffset, BufferLength);
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DeviceExtension, Buffer, ConfigDataOffset, BufferLength);
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@ -32,6 +32,8 @@ typedef struct _FDO_DEVICE_EXTENSION
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PHYSICAL_ADDRESS BusMasterPortBase;
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PHYSICAL_ADDRESS BusMasterPortBase;
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PDEVICE_OBJECT LowerDevice;
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PDEVICE_OBJECT LowerDevice;
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PDEVICE_OBJECT Pdo[MAX_IDE_CHANNEL];
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PDEVICE_OBJECT Pdo[MAX_IDE_CHANNEL];
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USHORT VendorId;
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USHORT DeviceId;
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PBYTE MiniControllerExtension[0];
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PBYTE MiniControllerExtension[0];
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} FDO_DEVICE_EXTENSION, *PFDO_DEVICE_EXTENSION;
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} FDO_DEVICE_EXTENSION, *PFDO_DEVICE_EXTENSION;
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@ -18,6 +18,7 @@ PciIdeXPdoQueryId(
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OUT ULONG_PTR* Information)
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OUT ULONG_PTR* Information)
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{
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{
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PPDO_DEVICE_EXTENSION DeviceExtension;
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PPDO_DEVICE_EXTENSION DeviceExtension;
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PFDO_DEVICE_EXTENSION FdoDeviceExtension;
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WCHAR Buffer[256];
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WCHAR Buffer[256];
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ULONG Index = 0;
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ULONG Index = 0;
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ULONG IdType;
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ULONG IdType;
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@ -27,6 +28,7 @@ PciIdeXPdoQueryId(
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IdType = IoGetCurrentIrpStackLocation(Irp)->Parameters.QueryId.IdType;
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IdType = IoGetCurrentIrpStackLocation(Irp)->Parameters.QueryId.IdType;
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DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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FdoDeviceExtension = (PFDO_DEVICE_EXTENSION)DeviceExtension->ControllerFdo->DeviceExtension;
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switch (IdType)
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switch (IdType)
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{
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{
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@ -40,26 +42,62 @@ PciIdeXPdoQueryId(
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{
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{
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DPRINT("IRP_MJ_PNP / IRP_MN_QUERY_ID / BusQueryHardwareIDs\n");
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DPRINT("IRP_MJ_PNP / IRP_MN_QUERY_ID / BusQueryHardwareIDs\n");
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switch (FdoDeviceExtension->VendorId)
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{
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case 0x0e11:
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Index += swprintf(&Buffer[Index], L"Compaq-%04x", FdoDeviceExtension->DeviceId) + 1;
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break;
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case 0x1039:
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Index += swprintf(&Buffer[Index], L"SiS-%04x", FdoDeviceExtension->DeviceId) + 1;
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break;
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case 0x1050:
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Index += swprintf(&Buffer[Index], L"WinBond-%04x", FdoDeviceExtension->DeviceId) + 1;
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break;
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case 0x1095:
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Index += swprintf(&Buffer[Index], L"CMD-%04x", FdoDeviceExtension->DeviceId) + 1;
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break;
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case 0x8086:
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{
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switch (FdoDeviceExtension->DeviceId)
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{
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case 0x1230:
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Index += swprintf(&Buffer[Index], L"Intel-PIIX") + 1;
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break;
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case 0x7010:
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Index += swprintf(&Buffer[Index], L"Intel-PIIX3") + 1;
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break;
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case 0x7111:
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Index += swprintf(&Buffer[Index], L"Intel-PIIX4") + 1;
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break;
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default:
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Index += swprintf(&Buffer[Index], L"Intel-%04x", FdoDeviceExtension->DeviceId) + 1;
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break;
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}
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break;
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}
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default:
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break;
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}
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if (DeviceExtension->Channel == 0)
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if (DeviceExtension->Channel == 0)
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Index += swprintf(&Buffer[Index], L"Primary_IDE_Channel");
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Index += swprintf(&Buffer[Index], L"Primary_IDE_Channel") + 1;
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else
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else
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Index += swprintf(&Buffer[Index], L"Secondary_IDE_Channel");
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Index += swprintf(&Buffer[Index], L"Secondary_IDE_Channel") + 1;
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Index++;
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Index += swprintf(&Buffer[Index], L"*PNP0600") + 1;
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Buffer[Index] = UNICODE_NULL;
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Buffer[Index] = UNICODE_NULL;
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SourceString.Length = SourceString.MaximumLength = Index * sizeof(WCHAR);
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SourceString.Length = SourceString.MaximumLength = Index * sizeof(WCHAR);
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SourceString.Buffer = Buffer;
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SourceString.Buffer = Buffer;
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break;
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break;
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}
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}
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case BusQueryCompatibleIDs:
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case BusQueryCompatibleIDs:
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{
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DPRINT("IRP_MJ_PNP / IRP_MN_QUERY_ID / BusQueryCompatibleIDs\n");
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DPRINT("IRP_MJ_PNP / IRP_MN_QUERY_ID / BusQueryCompatibleIDs\n");
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Index += swprintf(&Buffer[Index],
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Index += swprintf(&Buffer[Index], L"*PNP0600") + 1;
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L"*PNP0600");
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Index++;
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Buffer[Index] = UNICODE_NULL;
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Buffer[Index] = UNICODE_NULL;
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SourceString.Length = SourceString.MaximumLength = Index * sizeof(WCHAR);
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SourceString.Length = SourceString.MaximumLength = Index * sizeof(WCHAR);
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SourceString.Buffer = Buffer;
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SourceString.Buffer = Buffer;
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break;
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break;
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}
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case BusQueryInstanceID:
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case BusQueryInstanceID:
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{
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{
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DPRINT("IRP_MJ_PNP / IRP_MN_QUERY_ID / BusQueryInstanceID\n");
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DPRINT("IRP_MJ_PNP / IRP_MN_QUERY_ID / BusQueryInstanceID\n");
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@ -69,9 +107,7 @@ PciIdeXPdoQueryId(
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}
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}
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default:
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default:
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DPRINT1("IRP_MJ_PNP / IRP_MN_QUERY_ID / unknown query id type 0x%lx\n", IdType);
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DPRINT1("IRP_MJ_PNP / IRP_MN_QUERY_ID / unknown query id type 0x%lx\n", IdType);
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#ifndef NDEBUG
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ASSERT(FALSE);
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DbgBreakPoint();
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#endif
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return STATUS_NOT_SUPPORTED;
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return STATUS_NOT_SUPPORTED;
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}
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}
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@ -94,21 +130,22 @@ GetCurrentResources(
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PPDO_DEVICE_EXTENSION DeviceExtension;
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PPDO_DEVICE_EXTENSION DeviceExtension;
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PFDO_DEVICE_EXTENSION FdoDeviceExtension;
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PFDO_DEVICE_EXTENSION FdoDeviceExtension;
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ULONG BaseIndex;
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ULONG BaseIndex;
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ULONG BytesRead;
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PCI_COMMON_CONFIG PciConfig;
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PCI_COMMON_CONFIG PciConfig;
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NTSTATUS Status;
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NTSTATUS ret = STATUS_UNSUCCESSFUL;
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NTSTATUS ret = STATUS_UNSUCCESSFUL;
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DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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FdoDeviceExtension = (PFDO_DEVICE_EXTENSION)DeviceExtension->ControllerFdo->DeviceExtension;
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FdoDeviceExtension = (PFDO_DEVICE_EXTENSION)DeviceExtension->ControllerFdo->DeviceExtension;
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BaseIndex = DeviceExtension->Channel * 2;
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BaseIndex = DeviceExtension->Channel * 2;
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Status = PciIdeXGetBusData(
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BytesRead = (*FdoDeviceExtension->BusInterface->GetBusData)(
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FdoDeviceExtension->MiniControllerExtension,
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FdoDeviceExtension->BusInterface->Context,
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PCI_WHICHSPACE_CONFIG,
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&PciConfig,
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&PciConfig,
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0,
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0,
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PCI_COMMON_HDR_LENGTH);
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PCI_COMMON_HDR_LENGTH);
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if (!NT_SUCCESS(Status))
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if (BytesRead != PCI_COMMON_HDR_LENGTH)
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return Status;
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return STATUS_IO_DEVICE_ERROR;
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/* We have found a known native pci ide controller */
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/* We have found a known native pci ide controller */
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if ((PciConfig.ProgIf & 0x80) && (PciConfig.u.type0.BaseAddresses[4] & PCI_ADDRESS_IO_SPACE))
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if ((PciConfig.ProgIf & 0x80) && (PciConfig.u.type0.BaseAddresses[4] & PCI_ADDRESS_IO_SPACE))
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@ -122,17 +159,22 @@ GetCurrentResources(
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*BusMasterPortBase = 0;
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*BusMasterPortBase = 0;
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}
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}
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if ((PciConfig.u.type0.BaseAddresses[BaseIndex + 0] & PCI_ADDRESS_IO_SPACE) &&
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if ((PciConfig.ProgIf >> BaseIndex) & 0x1)
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(PciConfig.u.type0.BaseAddresses[BaseIndex + 1] & PCI_ADDRESS_IO_SPACE))
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{
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{
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/* Channel is enabled */
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/* Native mode */
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*CommandPortBase = PciConfig.u.type0.BaseAddresses[BaseIndex + 0] & PCI_ADDRESS_IO_ADDRESS_MASK;
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if ((PciConfig.u.type0.BaseAddresses[BaseIndex + 0] & PCI_ADDRESS_IO_SPACE) &&
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*ControlPortBase = PciConfig.u.type0.BaseAddresses[BaseIndex + 1] & PCI_ADDRESS_IO_ADDRESS_MASK;
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(PciConfig.u.type0.BaseAddresses[BaseIndex + 1] & PCI_ADDRESS_IO_SPACE))
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*InterruptVector = PciConfig.u.type0.InterruptLine;
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{
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ret = STATUS_SUCCESS;
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/* Channel is enabled */
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*CommandPortBase = PciConfig.u.type0.BaseAddresses[BaseIndex + 0] & PCI_ADDRESS_IO_ADDRESS_MASK;
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*ControlPortBase = PciConfig.u.type0.BaseAddresses[BaseIndex + 1] & PCI_ADDRESS_IO_ADDRESS_MASK;
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*InterruptVector = PciConfig.u.type0.InterruptLine;
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ret = STATUS_SUCCESS;
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}
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}
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}
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else
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else
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{
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{
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/* Compatibility mode */
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switch (DeviceExtension->Channel)
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switch (DeviceExtension->Channel)
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{
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{
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case 0:
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case 0:
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@ -263,9 +305,7 @@ PciIdeXPdoQueryDeviceText(
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}
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}
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default:
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default:
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DPRINT1("IRP_MJ_PNP / IRP_MN_QUERY_DEVICE_TEXT / unknown type 0x%lx\n", DeviceTextType);
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DPRINT1("IRP_MJ_PNP / IRP_MN_QUERY_DEVICE_TEXT / unknown type 0x%lx\n", DeviceTextType);
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#ifndef NDEBUG
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ASSERT(FALSE);
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DbgBreakPoint();
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#endif
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return STATUS_NOT_SUPPORTED;
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return STATUS_NOT_SUPPORTED;
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}
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}
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@ -370,9 +410,7 @@ PciIdeXPdoPnpDispatch(
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{
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{
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DPRINT1("IRP_MJ_PNP / IRP_MN_QUERY_DEVICE_RELATIONS / Unknown type 0x%lx\n",
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DPRINT1("IRP_MJ_PNP / IRP_MN_QUERY_DEVICE_RELATIONS / Unknown type 0x%lx\n",
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Stack->Parameters.QueryDeviceRelations.Type);
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Stack->Parameters.QueryDeviceRelations.Type);
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#ifndef NDEBUG
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ASSERT(FALSE);
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DbgBreakPoint();
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#endif
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Status = STATUS_NOT_SUPPORTED;
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Status = STATUS_NOT_SUPPORTED;
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break;
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break;
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}
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}
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@ -456,9 +494,7 @@ PciIdeXPdoPnpDispatch(
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/* We can't forward request to the lower driver, because
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/* We can't forward request to the lower driver, because
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* we are a Pdo, so we don't have lower driver... */
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* we are a Pdo, so we don't have lower driver... */
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DPRINT1("IRP_MJ_PNP / Unknown minor function 0x%lx\n", MinorFunction);
|
DPRINT1("IRP_MJ_PNP / Unknown minor function 0x%lx\n", MinorFunction);
|
||||||
#ifndef NDEBUG
|
ASSERT(FALSE);
|
||||||
DbgBreakPoint();
|
|
||||||
#endif
|
|
||||||
Information = Irp->IoStatus.Information;
|
Information = Irp->IoStatus.Information;
|
||||||
Status = Irp->IoStatus.Status;
|
Status = Irp->IoStatus.Status;
|
||||||
}
|
}
|
||||||
|
|
|
@ -32,87 +32,173 @@ extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define MAX_IDE_CHANNEL 2
|
#define MAX_IDE_CHANNEL 2
|
||||||
|
#define MAX_IDE_LINE 2
|
||||||
#define MAX_IDE_DEVICE 2
|
#define MAX_IDE_DEVICE 2
|
||||||
|
|
||||||
#include <pshpack1.h>
|
#include <pshpack1.h>
|
||||||
typedef struct _IDE_DRIVE_IDENTIFY
|
typedef struct _IDENTIFY_DATA {
|
||||||
{
|
USHORT GeneralConfiguration; /* 00 */
|
||||||
USHORT GeneralConfiguration;
|
USHORT NumCylinders; /* 02 */
|
||||||
USHORT NumberOfCylinders;
|
USHORT Reserved1; /* 04 */
|
||||||
USHORT Reserved1;
|
USHORT NumHeads; /* 06 */
|
||||||
USHORT NumberOfHeads;
|
USHORT UnformattedBytesPerTrack; /* 08 */
|
||||||
USHORT UnformattedBytesPerTrack;
|
USHORT UnformattedBytesPerSector; /* 10 */
|
||||||
USHORT UnformattedBytesPerSector;
|
USHORT NumSectorsPerTrack; /* 12 */
|
||||||
USHORT SectorsPerTrack;
|
USHORT VendorUnique1[3]; /* 14 */
|
||||||
USHORT VendorUnique1[3];
|
UCHAR SerialNumber[20]; /* 20 */
|
||||||
BYTE SerialNumber[20];
|
USHORT BufferType; /* 40 */
|
||||||
USHORT BufferType;
|
USHORT BufferSectorSize; /* 42 */
|
||||||
USHORT BufferSectorSize;
|
USHORT NumberOfEccBytes; /* 44 */
|
||||||
USHORT NumberOfEccBytes;
|
UCHAR FirmwareRevision[8]; /* 46 */
|
||||||
BYTE FirmwareRevision[8];
|
UCHAR ModelNumber[40]; /* 54 */
|
||||||
BYTE ModelNumber[40];
|
UCHAR MaximumBlockTransfer; /* 94 */
|
||||||
BYTE MaximumBlockTransfer;
|
UCHAR VendorUnique2; /* 95 */
|
||||||
BYTE VendorUnique2;
|
USHORT DoubleWordIo; /* 96 */
|
||||||
USHORT DoubleWordIo;
|
USHORT Capabilities; /* 98 */
|
||||||
USHORT Capabilities;
|
USHORT Reserved2; /* 100 */
|
||||||
USHORT Reserved2;
|
UCHAR VendorUnique3; /* 102 */
|
||||||
BYTE VendorUnique3;
|
UCHAR PioCycleTimingMode; /* 103 */
|
||||||
BYTE PioCycleTimingMode;
|
UCHAR VendorUnique4; /* 104 */
|
||||||
BYTE VendorUnique4;
|
UCHAR DmaCycleTimingMode; /* 105 */
|
||||||
BYTE DmaCycleTimingMode;
|
USHORT TranslationFieldsValid:3; /* 106 */
|
||||||
USHORT TranslationFieldsValid:3;
|
USHORT Reserved3:13; /* - */
|
||||||
USHORT Reserved3:13;
|
USHORT NumberOfCurrentCylinders; /* 108 */
|
||||||
USHORT NumberOfCurrentCylinders;
|
USHORT NumberOfCurrentHeads; /* 110 */
|
||||||
USHORT NumberOfCurrentHeads;
|
USHORT CurrentSectorsPerTrack; /* 112 */
|
||||||
USHORT CurrentSectorsPerTrack;
|
ULONG CurrentSectorCapacity; /* 114 */
|
||||||
ULONG CurrentSectorCapacity;
|
USHORT CurrentMultiSectorSetting; /* 118 */
|
||||||
USHORT CurrentMultiSectorSetting;
|
ULONG UserAddressableSectors; /* 120 */
|
||||||
ULONG UserAddressableSectors;
|
USHORT SingleWordDMASupport:8; /* 124 */
|
||||||
USHORT SingleWordDMASupport : 8;
|
USHORT SingleWordDMAActive:8; /* - */
|
||||||
USHORT SingleWordDMAActive : 8;
|
USHORT MultiWordDMASupport:8; /* 126 */
|
||||||
USHORT MultiWordDMASupport : 8;
|
USHORT MultiWordDMAActive:8; /* - */
|
||||||
USHORT MultiWordDMAActive : 8;
|
USHORT AdvancedPIOModes:8; /* 128 */
|
||||||
USHORT AdvancedPIOModes : 8;
|
USHORT Reserved4:8; /* - */
|
||||||
USHORT Reserved4 : 8;
|
USHORT MinimumMWXferCycleTime; /* 130 */
|
||||||
USHORT MinimumMWXferCycleTime;
|
USHORT RecommendedMWXferCycleTime; /* 132 */
|
||||||
USHORT RecommendedMWXferCycleTime;
|
USHORT MinimumPIOCycleTime; /* 134 */
|
||||||
USHORT MinimumPIOCycleTime;
|
USHORT MinimumPIOCycleTimeIORDY; /* 136 */
|
||||||
USHORT MinimumPIOCycleTimeIORDY;
|
USHORT Reserved5[11]; /* 138 */
|
||||||
USHORT Reserved5[11];
|
USHORT MajorRevision; /* 160 */
|
||||||
USHORT MajorRevision;
|
USHORT MinorRevision; /* 162 */
|
||||||
USHORT MinorRevision;
|
USHORT Reserved6; /* 164 */
|
||||||
USHORT Reserved6[6];
|
USHORT CommandSetSupport; /* 166 */
|
||||||
USHORT UltraDMASupport : 8;
|
USHORT Reserved6a[2]; /* 168 */
|
||||||
USHORT UltraDMAActive : 8;
|
USHORT CommandSetActive; /* 172 */
|
||||||
USHORT Reserved7[37];
|
USHORT Reserved6b; /* 174 */
|
||||||
USHORT LastLun:3;
|
USHORT UltraDMASupport:8; /* 176 */
|
||||||
USHORT Reserved8:13;
|
USHORT UltraDMAActive:8; /* - */
|
||||||
USHORT MediaStatusNotification:2;
|
USHORT Reserved7[11]; /* 178 */
|
||||||
USHORT Reserved9:6;
|
ULONG Max48BitLBA[2]; /* 200 */
|
||||||
USHORT DeviceWriteProtect:1;
|
USHORT Reserved7a[22]; /* 208 */
|
||||||
USHORT Reserved10:7;
|
USHORT LastLun:3; /* 252 */
|
||||||
USHORT Reserved11[128];
|
USHORT Reserved8:13; /* - */
|
||||||
} IDE_DRIVE_IDENTIFY, *PIDE_DRIVE_IDENTIFY;
|
USHORT MediaStatusNotification:2; /* 254 */
|
||||||
|
USHORT Reserved9:6; /* - */
|
||||||
|
USHORT DeviceWriteProtect:1; /* - */
|
||||||
|
USHORT Reserved10:7; /* - */
|
||||||
|
USHORT Reserved11[128]; /* 256 */
|
||||||
|
} IDENTIFY_DATA, *PIDENTIFY_DATA;
|
||||||
|
|
||||||
|
typedef struct _EXTENDED_IDENTIFY_DATA {
|
||||||
|
USHORT GeneralConfiguration; /* 00 */
|
||||||
|
USHORT NumCylinders; /* 02 */
|
||||||
|
USHORT Reserved1; /* 04 */
|
||||||
|
USHORT NumHeads; /* 06 */
|
||||||
|
USHORT UnformattedBytesPerTrack; /* 08 */
|
||||||
|
USHORT UnformattedBytesPerSector; /* 10 */
|
||||||
|
USHORT NumSectorsPerTrack; /* 12 */
|
||||||
|
union
|
||||||
|
{
|
||||||
|
USHORT VendorUnique1[3]; /* 14 */
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
UCHAR InterSectorGap; /* 14 */
|
||||||
|
UCHAR InterSectorGapSize; /* - */
|
||||||
|
UCHAR Reserved16; /* 16 */
|
||||||
|
UCHAR BytesInPLO; /* - */
|
||||||
|
USHORT VendorUniqueCnt; /* 18 */
|
||||||
|
} u;
|
||||||
|
};
|
||||||
|
UCHAR SerialNumber[20]; /* 20 */
|
||||||
|
USHORT BufferType; /* 40 */
|
||||||
|
USHORT BufferSectorSize; /* 42 */
|
||||||
|
USHORT NumberOfEccBytes; /* 44 */
|
||||||
|
UCHAR FirmwareRevision[8]; /* 46 */
|
||||||
|
UCHAR ModelNumber[40]; /* 54 */
|
||||||
|
UCHAR MaximumBlockTransfer; /* 94 */
|
||||||
|
UCHAR VendorUnique2; /* 95 */
|
||||||
|
USHORT DoubleWordIo; /* 96 */
|
||||||
|
USHORT Capabilities; /* 98 */
|
||||||
|
USHORT Reserved2; /* 100 */
|
||||||
|
UCHAR VendorUnique3; /* 102 */
|
||||||
|
UCHAR PioCycleTimingMode; /* 103 */
|
||||||
|
UCHAR VendorUnique4; /* 104 */
|
||||||
|
UCHAR DmaCycleTimingMode; /* 105 */
|
||||||
|
USHORT TranslationFieldsValid:3; /* 106 */
|
||||||
|
USHORT Reserved3:13; /* - */
|
||||||
|
USHORT NumberOfCurrentCylinders; /* 108 */
|
||||||
|
USHORT NumberOfCurrentHeads; /* 110 */
|
||||||
|
USHORT CurrentSectorsPerTrack; /* 112 */
|
||||||
|
ULONG CurrentSectorCapacity; /* 114 */
|
||||||
|
USHORT CurrentMultiSectorSetting; /* 118 */
|
||||||
|
ULONG UserAddressableSectors; /* 120 */
|
||||||
|
USHORT SingleWordDMASupport:8; /* 124 */
|
||||||
|
USHORT SingleWordDMAActive:8; /* - */
|
||||||
|
USHORT MultiWordDMASupport:8; /* 126 */
|
||||||
|
USHORT MultiWordDMAActive:8; /* - */
|
||||||
|
USHORT AdvancedPIOModes:8; /* 128 */
|
||||||
|
USHORT Reserved4:8; /* - */
|
||||||
|
USHORT MinimumMWXferCycleTime; /* 130 */
|
||||||
|
USHORT RecommendedMWXferCycleTime; /* 132 */
|
||||||
|
USHORT MinimumPIOCycleTime; /* 134 */
|
||||||
|
USHORT MinimumPIOCycleTimeIORDY; /* 136 */
|
||||||
|
USHORT Reserved5[11]; /* 138 */
|
||||||
|
USHORT MajorRevision; /* 160 */
|
||||||
|
USHORT MinorRevision; /* 162 */
|
||||||
|
USHORT Reserved6; /* 164 */
|
||||||
|
USHORT CommandSetSupport; /* 166 */
|
||||||
|
USHORT Reserved6a[2]; /* 168 */
|
||||||
|
USHORT CommandSetActive; /* 172 */
|
||||||
|
USHORT Reserved6b; /* 174 */
|
||||||
|
USHORT UltraDMASupport:8; /* 176 */
|
||||||
|
USHORT UltraDMAActive:8; /* - */
|
||||||
|
USHORT Reserved7[11]; /* 178 */
|
||||||
|
ULONG Max48BitLBA[2]; /* 200 */
|
||||||
|
USHORT Reserved7a[22]; /* 208 */
|
||||||
|
USHORT LastLun:3; /* 252 */
|
||||||
|
USHORT Reserved8:13; /* - */
|
||||||
|
USHORT MediaStatusNotification:2; /* 254 */
|
||||||
|
USHORT Reserved9:6; /* - */
|
||||||
|
USHORT DeviceWriteProtect:1; /* - */
|
||||||
|
USHORT Reserved10:7; /* - */
|
||||||
|
USHORT Reserved11[128]; /* 256 */
|
||||||
|
} EXTENDED_IDENTIFY_DATA, *PEXTENDED_IDENTIFY_DATA;
|
||||||
#include <poppack.h>
|
#include <poppack.h>
|
||||||
|
|
||||||
typedef struct _PCIIDE_TRANSFER_MODE_SELECT
|
typedef struct _PCIIDE_TRANSFER_MODE_SELECT
|
||||||
{
|
{
|
||||||
ULONG Channel;
|
ULONG Channel;
|
||||||
BOOLEAN DevicePresent[MAX_IDE_DEVICE];
|
BOOLEAN DevicePresent[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||||
BOOLEAN FixedDisk[MAX_IDE_DEVICE];
|
BOOLEAN FixedDisk[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||||
BOOLEAN IoReadySupported[MAX_IDE_DEVICE];
|
BOOLEAN IoReadySupported[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||||
ULONG DeviceTransferModeSupported[MAX_IDE_DEVICE];
|
ULONG DeviceTransferModeSupported[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||||
ULONG BestPioCycleTime[MAX_IDE_DEVICE];
|
ULONG BestPioCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||||
ULONG BestSwDmaCycleTime[MAX_IDE_DEVICE];
|
ULONG BestSwDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||||
ULONG BestMwDmaCycleTime[MAX_IDE_DEVICE];
|
ULONG BestMwDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||||
ULONG BestUDmaCycleTime[MAX_IDE_DEVICE];
|
ULONG BestUDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||||
ULONG DeviceTransferModeCurrent[MAX_IDE_DEVICE];
|
ULONG DeviceTransferModeCurrent[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||||
ULONG DeviceTransferModeSelected[MAX_IDE_DEVICE];
|
ULONG UserChoiceTransferMode[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||||
|
ULONG EnableUDMA66;
|
||||||
|
IDENTIFY_DATA IdentifyData[MAX_IDE_DEVICE];
|
||||||
|
ULONG DeviceTransferModeSelected[MAX_IDE_DEVICE * MAX_IDE_LINE];
|
||||||
|
PULONG TransferModeTimingTable;
|
||||||
|
ULONG TransferModeTableLength;
|
||||||
} PCIIDE_TRANSFER_MODE_SELECT, *PPCIIDE_TRANSFER_MODE_SELECT;
|
} PCIIDE_TRANSFER_MODE_SELECT, *PPCIIDE_TRANSFER_MODE_SELECT;
|
||||||
|
|
||||||
typedef enum
|
typedef enum
|
||||||
{
|
{
|
||||||
ChannelDisabled,
|
ChannelDisabled = 0,
|
||||||
ChannelEnabled,
|
ChannelEnabled,
|
||||||
ChannelStateUnknown
|
ChannelStateUnknown
|
||||||
} IDE_CHANNEL_STATE;
|
} IDE_CHANNEL_STATE;
|
||||||
|
@ -131,7 +217,7 @@ typedef NTSTATUS
|
||||||
IN PVOID DeviceExtension,
|
IN PVOID DeviceExtension,
|
||||||
IN OUT PPCIIDE_TRANSFER_MODE_SELECT XferMode);
|
IN OUT PPCIIDE_TRANSFER_MODE_SELECT XferMode);
|
||||||
|
|
||||||
typedef BOOLEAN
|
typedef ULONG
|
||||||
(NTAPI *PCIIDE_USEDMA_FUNC)(
|
(NTAPI *PCIIDE_USEDMA_FUNC)(
|
||||||
IN PVOID DeviceExtension,
|
IN PVOID DeviceExtension,
|
||||||
IN PUCHAR CdbCommand,
|
IN PUCHAR CdbCommand,
|
||||||
|
@ -139,7 +225,7 @@ typedef BOOLEAN
|
||||||
|
|
||||||
typedef NTSTATUS
|
typedef NTSTATUS
|
||||||
(NTAPI *PCIIDE_UDMA_MODES_SUPPORTED)(
|
(NTAPI *PCIIDE_UDMA_MODES_SUPPORTED)(
|
||||||
IN IDE_DRIVE_IDENTIFY IdentifyData,
|
IN IDENTIFY_DATA IdentifyData,
|
||||||
OUT PULONG BestXferMode,
|
OUT PULONG BestXferMode,
|
||||||
OUT PULONG CurrentXferMode);
|
OUT PULONG CurrentXferMode);
|
||||||
|
|
||||||
|
@ -210,6 +296,7 @@ PciIdeXSetBusData(
|
||||||
#define UDMA_MODE2 (1 << 13)
|
#define UDMA_MODE2 (1 << 13)
|
||||||
#define UDMA_MODE3 (1 << 14)
|
#define UDMA_MODE3 (1 << 14)
|
||||||
#define UDMA_MODE4 (1 << 15)
|
#define UDMA_MODE4 (1 << 15)
|
||||||
|
#define UDMA_MODE5 (1 << 16)
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in a new issue