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[E1000] Finished an implementation of the driver.
Added PIDs for whole Intel 8254x family. Note: this driver uses legacy interfaces for either receive and transmit descriptors. CORE-14675
This commit is contained in:
Victor Perevertkin
Mark Jansen
parent
1b2ca28107
commit
d9c4d28e59
7 changed files with 262 additions and 160 deletions
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@ -2,7 +2,8 @@
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* PROJECT: ReactOS Intel PRO/1000 Driver
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* LICENSE: GPL-2.0+ (https://spdx.org/licenses/GPL-2.0+)
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* PURPOSE: Hardware specific functions
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* COPYRIGHT: Copyright 2018 Mark Jansen (mark.jansen@reactos.org)
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* COPYRIGHT: 2018 Mark Jansen (mark.jansen@reactos.org)
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* 2019 Victor Perevertkin (victor.perevertkin@reactos.org)
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*/
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#include "nic.h"
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@ -12,7 +13,44 @@
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static USHORT SupportedDevices[] =
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{
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0x100f, // Intel 82545EM (VMWare E1000)
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/* 8254x Family adapters. Not all of them are tested */
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0x1000, // Intel 82542
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0x1001, // Intel 82543GC Fiber
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0x1004, // Intel 82543GC Copper
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0x1008, // Intel 82544EI Copper
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0x1009, // Intel 82544EI Fiber
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0x100A, // Intel 82540EM
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0x100C, // Intel 82544GC Copper
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0x100D, // Intel 82544GC LOM (LAN on Motherboard)
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0x100E, // Intel 82540EM
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0x100F, // Intel 82545EM Copper
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0x1010, // Intel 82546EB Copper
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0x1011, // Intel 82545EM Fiber
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0x1012, // Intel 82546EB Fiber
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0x1013, // Intel 82541EI
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0x1014, // Intel 82541EI LOM
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0x1015, // Intel 82540EM LOM
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0x1016, // Intel 82540EP LOM
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0x1017, // Intel 82540EP
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0x1018, // Intel 82541EI Mobile
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0x1019, // Intel 82547EI
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0x101A, // Intel 82547EI Mobile
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0x101D, // Intel 82546EB Quad Copper
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0x101E, // Intel 82540EP LP (Low profile)
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0x1026, // Intel 82545GM Copper
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0x1027, // Intel 82545GM Fiber
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0x1028, // Intel 82545GM SerDes
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0x1075, // Intel 82547GI
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0x1076, // Intel 82541GI
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0x1077, // Intel 82541GI Mobile
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0x1078, // Intel 82541ER
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0x1079, // Intel 82546GB Copper
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0x107A, // Intel 82546GB Fiber
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0x107B, // Intel 82546GB SerDes
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0x107C, // Intel 82541PI
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0x108A, // Intel 82546GB PCI-E
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0x1099, // Intel 82546GB Quad Copper
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0x10B5, // Intel 82546GB Quad Copper KSP3
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};
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@ -29,7 +67,7 @@ VOID NTAPI E1000WriteUlong(IN PE1000_ADAPTER Adapter, IN ULONG Address, IN ULONG
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NdisWriteRegisterUlong((PULONG)(Adapter->IoBase + Address), Value);
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}
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static VOID E1000ReadUlong(IN PE1000_ADAPTER Adapter, IN ULONG Address, OUT PULONG Value)
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VOID NTAPI E1000ReadUlong(IN PE1000_ADAPTER Adapter, IN ULONG Address, OUT PULONG Value)
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{
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NdisReadRegisterUlong((PULONG)(Adapter->IoBase + Address), Value);
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}
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@ -99,6 +137,8 @@ static ULONG RcvBufRegisterMask(E1000_RCVBUF_SIZE BufSize)
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return Mask;
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}
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#if 0
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/* This function works, but the driver does not use PHY register access right now */
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static BOOLEAN E1000ReadMdic(IN PE1000_ADAPTER Adapter, IN ULONG Address, USHORT *Result)
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{
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ULONG ResultAddress;
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@ -147,11 +187,12 @@ static BOOLEAN E1000ReadMdic(IN PE1000_ADAPTER Adapter, IN ULONG Address, USHORT
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*Result = (USHORT) Mdic;
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return TRUE;
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}
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#endif
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static BOOLEAN E1000ReadEeprom(IN PE1000_ADAPTER Adapter, IN UCHAR Address, USHORT *Result)
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{
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UINT Value;
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ULONG Value;
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UINT n;
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E1000WriteUlong(Adapter, E1000_REG_EERD, E1000_EERD_START | ((UINT)Address << E1000_EERD_ADDR_SHIFT));
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@ -524,10 +565,9 @@ NICSoftReset(
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ULONG Value, ResetAttempts;
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NDIS_DbgPrint(MAX_TRACE, ("Called.\n"));
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//em_get_hw_control(adapter);
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NICDisableInterrupts(Adapter);
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E1000WriteUlong(Adapter, E1000_REG_RCTL, 0);
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E1000WriteUlong(Adapter, E1000_REG_TCTL, 0);
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E1000ReadUlong(Adapter, E1000_REG_CTRL, &Value);
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/* Write this using IO port, some devices cannot ack this otherwise */
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E1000WriteIoUlong(Adapter, E1000_REG_CTRL, Value | E1000_CTRL_RST);
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@ -535,7 +575,8 @@ NICSoftReset(
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for (ResetAttempts = 0; ResetAttempts < MAX_RESET_ATTEMPTS; ResetAttempts++)
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{
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NdisStallExecution(100);
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/* Wait 1us after reset (according to manual) */
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NdisStallExecution(1);
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E1000ReadUlong(Adapter, E1000_REG_CTRL, &Value);
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if (!(Value & E1000_CTRL_RST))
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@ -543,11 +584,13 @@ NICSoftReset(
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NDIS_DbgPrint(MAX_TRACE, ("Device is back (%u)\n", ResetAttempts));
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NICDisableInterrupts(Adapter);
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/* Clear out interrupts */
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/* Clear out interrupts (the register is cleared upon read) */
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E1000ReadUlong(Adapter, E1000_REG_ICR, &Value);
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//NdisWriteRegisterUlong(Adapter->IoBase + E1000_REG_WUFC, 0);
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//NdisWriteRegisterUlong(Adapter->IoBase + E1000_REG_VET, E1000_VET_VLAN);
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E1000ReadUlong(Adapter, E1000_REG_CTRL, &Value);
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Value &= ~(E1000_CTRL_LRST|E1000_CTRL_VME);
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Value |= (E1000_CTRL_ASDE|E1000_CTRL_SLU);
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E1000WriteUlong(Adapter, E1000_REG_CTRL, Value);
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return NDIS_STATUS_SUCCESS;
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}
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@ -582,10 +625,13 @@ NICEnableTxRx(
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E1000WriteUlong(Adapter, E1000_REG_TDT, 0);
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Adapter->CurrentTxDesc = 0;
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/* Set up interrupt timers */
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E1000WriteUlong(Adapter, E1000_REG_TADV, 96); // value is in 1.024 of usec
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E1000WriteUlong(Adapter, E1000_REG_TIDV, 16);
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Value = E1000_TCTL_EN | E1000_TCTL_PSP;
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E1000WriteUlong(Adapter, E1000_REG_TCTL, Value);
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E1000WriteUlong(Adapter, E1000_REG_TCTL, E1000_TCTL_EN | E1000_TCTL_PSP);
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E1000WriteUlong(Adapter, E1000_REG_TIPG, E1000_TIPG_IPGT_DEF | E1000_TIPG_IPGR1_DEF | E1000_TIPG_IPGR2_DEF);
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NDIS_DbgPrint(MID_TRACE, ("Setting up receive.\n"));
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@ -602,10 +648,10 @@ NICEnableTxRx(
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/* Receive descriptor tail / head */
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E1000WriteUlong(Adapter, E1000_REG_RDH, 0);
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E1000WriteUlong(Adapter, E1000_REG_RDT, NUM_RECEIVE_DESCRIPTORS - 1);
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Adapter->CurrentRxDesc = 0;
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/* Setup Interrupt Throttling */
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E1000WriteUlong(Adapter, E1000_REG_ITR, DEFAULT_ITR);
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/* Set up interrupt timers */
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E1000WriteUlong(Adapter, E1000_REG_RADV, 96);
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E1000WriteUlong(Adapter, E1000_REG_RDTR, 16);
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/* Some defaults */
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Value = E1000_RCTL_SECRC | E1000_RCTL_EN;
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@ -634,9 +680,9 @@ NICDisableTxRx(
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Value &= ~E1000_TCTL_EN;
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E1000WriteUlong(Adapter, E1000_REG_TCTL, Value);
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//E1000ReadUlong(Adapter, E1000_REG_RCTL, &Value);
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//Value &= ~E1000_RCTL_EN;
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//E1000WriteUlong(Adapter, E1000_REG_RCTL, Value);
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E1000ReadUlong(Adapter, E1000_REG_RCTL, &Value);
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Value &= ~E1000_RCTL_EN;
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E1000WriteUlong(Adapter, E1000_REG_RCTL, Value);
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return NDIS_STATUS_SUCCESS;
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}
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@ -724,7 +770,7 @@ NICApplyInterruptMask(
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{
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NDIS_DbgPrint(MAX_TRACE, ("Called.\n"));
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E1000WriteUlong(Adapter, E1000_REG_IMS, Adapter->InterruptMask);
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E1000WriteUlong(Adapter, E1000_REG_IMS, Adapter->InterruptMask /*| 0x1F6DC*/);
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return NDIS_STATUS_SUCCESS;
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}
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@ -747,13 +793,13 @@ NICInterruptRecognized(
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{
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ULONG Value;
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NDIS_DbgPrint(MAX_TRACE, ("Called.\n"));
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/* Reading the interrupt acknowledges them */
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E1000ReadUlong(Adapter, E1000_REG_ICR, &Value);
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*InterruptRecognized = (Value & Adapter->InterruptMask) != 0;
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NDIS_DbgPrint(MAX_TRACE, ("NICInterruptRecognized(0x%x, 0x%x).\n", Value, *InterruptRecognized));
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return (Value & Adapter->InterruptMask);
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}
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@ -762,55 +808,23 @@ NTAPI
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NICUpdateLinkStatus(
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IN PE1000_ADAPTER Adapter)
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{
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ULONG SpeedIndex;
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USHORT PhyStatus;
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ULONG DeviceStatus;
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SIZE_T SpeedIndex;
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static ULONG SpeedValues[] = { 10, 100, 1000, 1000 };
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NDIS_DbgPrint(MAX_TRACE, ("Called.\n"));
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#if 0
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/* This does not work */
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E1000ReadUlong(Adapter, E1000_REG_STATUS, &DeviceStatus);
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E1000ReadUlong(Adapter, E1000_REG_STATUS, &DeviceStatus);
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Adapter->MediaState = (DeviceStatus & E1000_STATUS_LU) ? NdisMediaStateConnected : NdisMediaStateDisconnected;
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SpeedIndex = (DeviceStatus & E1000_STATUS_SPEEDMASK) >> E1000_STATUS_SPEEDSHIFT;
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Adapter->LinkSpeedMbps = SpeedValues[SpeedIndex];
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#else
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/* Link bit can be sticky on some boards, read it twice */
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if (!E1000ReadMdic(Adapter, E1000_PHY_STATUS, &PhyStatus))
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NdisStallExecution(100);
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Adapter->MediaState = NdisMediaStateDisconnected;
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Adapter->LinkSpeedMbps = 0;
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if (!E1000ReadMdic(Adapter, E1000_PHY_STATUS, &PhyStatus))
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return;
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if (!(PhyStatus & E1000_PS_LINK_STATUS))
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return;
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Adapter->MediaState = NdisMediaStateConnected;
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if (E1000ReadMdic(Adapter, E1000_PHY_SPECIFIC_STATUS, &PhyStatus))
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{
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if (PhyStatus & E1000_PSS_SPEED_AND_DUPLEX)
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{
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SpeedIndex = (PhyStatus & E1000_PSS_SPEEDMASK) >> E1000_PSS_SPEEDSHIFT;
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Adapter->LinkSpeedMbps = SpeedValues[SpeedIndex];
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}
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else
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{
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NDIS_DbgPrint(MIN_TRACE, ("Speed and duplex not yet resolved, retry?.\n"));
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}
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}
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#endif
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}
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NDIS_STATUS
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NTAPI
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NICTransmitPacket(
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IN PE1000_ADAPTER Adapter,
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IN ULONG PhysicalAddress,
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IN PHYSICAL_ADDRESS PhysicalAddress,
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IN ULONG Length)
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{
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volatile PE1000_TRANSMIT_DESCRIPTOR TransmitDescriptor;
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@ -818,10 +832,10 @@ NICTransmitPacket(
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NDIS_DbgPrint(MAX_TRACE, ("Called.\n"));
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TransmitDescriptor = Adapter->TransmitDescriptors + Adapter->CurrentTxDesc;
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TransmitDescriptor->Address = PhysicalAddress;
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TransmitDescriptor->Address = PhysicalAddress.QuadPart;
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TransmitDescriptor->Length = Length;
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TransmitDescriptor->ChecksumOffset = 0;
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TransmitDescriptor->Command = E1000_TDESC_CMD_RS | E1000_TDESC_CMD_IFCS | E1000_TDESC_CMD_EOP;
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TransmitDescriptor->Command = E1000_TDESC_CMD_RS | E1000_TDESC_CMD_IFCS | E1000_TDESC_CMD_EOP | E1000_TDESC_CMD_IDE;
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TransmitDescriptor->Status = 0;
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TransmitDescriptor->ChecksumStartField = 0;
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TransmitDescriptor->Special = 0;
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@ -830,8 +844,6 @@ NICTransmitPacket(
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E1000WriteUlong(Adapter, E1000_REG_TDT, Adapter->CurrentTxDesc);
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NDIS_DbgPrint(MAX_TRACE, ("CurrentTxDesc:%u, LastTxDesc:%u\n", Adapter->CurrentTxDesc, Adapter->LastTxDesc));
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if (Adapter->CurrentTxDesc == Adapter->LastTxDesc)
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{
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NDIS_DbgPrint(MID_TRACE, ("All TX descriptors are full now\n"));
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